JP2011029303A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new strain technology capable of effectively applying a compressive stress to a channel region of a p-channel transistor and a tensile stress to the channel region of n-channel transistor, even with a miniaturized transistor. <P>SOLUTION: A gate electrode of the p-channel transistor 105 has a p-channel metal electrode 110 having an internal tensile stress. The gate electrode of the n-channel transistor 106 has an n-channel metal electrode 116 having an internal compressive stress. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a gate electrode structure having a high dielectric constant gate insulating film and a method for manufacturing the same.

  In complementary metal oxide semiconductor (CMOS) devices, two types of transistors, NMOS and PMOS, are used. Here, on / off control of current is performed by movement of electrons in the NMOS transistor, and on / off control of current is performed by movement of holes in the PMOS transistor.

  The magnitude Idmax of the on-current flowing through the channel when the transistor is on is expressed as follows.

Idmax = (1/2) · μ · (W / L) · Cox · (Vg−Vth) ² (Equation 1)
Here, μ is the carrier mobility in the inversion layer serving as the channel, W is the gate width of the transistor, L is the gate length of the transistor, Cox is the capacitance of the gate insulating film (hereinafter referred to as gate capacitance), and Vg is the gate. The voltage, Vth, is a threshold voltage.

  From (Formula 1), in order to increase the speed, that is, to obtain a larger on-current, μ, W, Cox or (Vg−Vth) is increased or L is decreased. It turns out that it is necessary. Conventionally, speeding up of a semiconductor device has been promoted by reducing L, that is, by miniaturizing a transistor shape. However, in recent years, the progress of lithography technology has stopped, and a technique for increasing μ or Cox has evolved instead of improving the on-current of a transistor by miniaturization.

  Cox is expressed by the following formula (Formula 2). In order to increase Cox, it is necessary to increase the relative dielectric constant εr of the gate insulating film or to reduce the physical film thickness Tox of the gate insulating film. . That is, among the factors described above, the factors relating to the gate insulating film are an increase in the relative dielectric constant εr and a reduction in the physical film thickness Tox of the gate insulating film. Therefore, conventionally, attempts have been made to make the physical film thickness (oxide film thickness) Tox of the gate insulating film extremely thin in order to improve the on-current.

Cox = ε0 · εr · (S / Tox) (Formula 2)
In (Equation 2), ε0 is the dielectric constant in vacuum, and S is the gate area.

  Conventionally, a silicon oxide film (having a relative dielectric constant of about 3.9) has been generally used as a gate insulating film of a CMOS device. However, when the gate insulating film made of a silicon oxide film is thinned with the miniaturization of the transistor, the leakage current increases, and the device has high power consumption and standby power. Therefore, by using a gate insulating film having a relative dielectric constant of 4.0 or higher (that is, a high dielectric constant gate insulating film), the effective film thickness ( The development of EOT (equivalent oxide thickness) thin film, that is, high-k gate insulating film technology is progressing.

  However, if the conventional polysilicon gate electrode and the high-k gate insulating film are combined, the depletion layer capacitance between the high-k gate insulating film and the polysilicon gate electrode is caused by a phenomenon called depletion of the gate electrode. As a result, the advantage of the high-k gate insulating film that the EOT is thin is lost. That is, in order to prevent the depletion of the gate electrode, a combination of the high-k gate insulating film and the metal gate electrode is essential, and an appropriate threshold voltage (Vt by the stacked body of the high-k gate insulating film / metal gate electrode is required. ) Control is an important issue in constructing a CMOS device.

  In a conventional silicon oxide gate insulating film / polysilicon gate electrode, impurities such as boron and phosphorus are ion-implanted into polysilicon and activated by heat treatment, whereby the polysilicon work function is 4.65 eV in a non-doped state. Thus, for example, when boron is ion-implanted, the voltage can be increased to 5.15 eV, thereby enabling control of Vt of each of NMOS and PMOS. However, if a high-k gate insulating film is used, a Fermi level pinning phenomenon occurs in which the Fermi level is fixed by a high-density trap existing in the high-k gate insulating film. The function can no longer be changed. That is, the threshold voltage cannot be controlled by ion implantation. Further, even in a structure called MIPS (Metal-Inserted-Poly-Si Stack) in which a metal gate electrode and a polysilicon gate electrode are combined, it is difficult to adjust the work function by ion implantation. Therefore, in the high-k gate insulating film / metal gate electrode, the work function of the metal used for the gate electrode becomes dominant over the Vt control.

  In the study of the work function in the high-k gate insulating film / metal gate electrode, a nitride of titanium, tungsten, tantalum or molybdenum is used as the metal gate electrode material. In particular, nitrides of titanium and tungsten that have been used as DRAM (dynamic random access memory) electrode materials are easy to handle as metal gate electrode materials in terms of processing characteristics such as dry etching and wet etching. It has been.

  By the way, in order to increase μ (mobility) in the above (Formula 1), a technique for increasing the speed of a transistor by applying strain to the channel region has been recently reported. In this technique, first, a strain generation layer for generating strain is formed in a source / drain region of a transistor. For example, in a PMOS transistor, a method has been reported in which germanium (Ge) having a lattice spacing larger than that of silicon (Si) atoms is introduced into a source / drain region to form a strain generation layer (see, for example, Patent Document 1). . By introducing germanium, compressive strain can be applied to the Si lattice in the channel region, thereby improving the mobility of holes and increasing the operation speed of the PMOS transistor. On the other hand, in an NMOS transistor, a method for forming a strain generating layer by introducing carbon (C) having a lattice spacing smaller than that of Si atoms into a source / drain region has been reported (see, for example, Patent Document 2). By introducing carbon, tensile strain can be applied to the Si lattice in the channel region, thereby improving the mobility of electrons, so that the operation of the NMOS transistor can be speeded up. There are two known methods for forming a strain generating layer by introducing carbon into a source / drain region (see, for example, Patent Document 2, Non-Patent Document 1, and Non-Patent Document 2). The first is a method in which a strain generation layer is selectively epitaxially grown in a recess formed by hollowing out a source / drain region using a silane-based silicon source gas and a carbon source gas such as monomethylsilane. The second is a method in which carbon is ion-implanted into the source / drain regions and a heat treatment at about 900 ° C. is performed to cause solid phase growth to bond silicon and carbon.

  In addition, there is an example in which a SiN film having a film stress is formed as a contact liner film in order to introduce strain into the channel region (see, for example, Patent Document 3). In this example, a stress is applied to the channel region using a liner film formed as an etching stop film when etching is performed to form a contact hole in the interlayer insulating film. More specifically, when a SiN film having a film stress is used as a liner film, a SiN film having a tensile stress is formed for NMOS and a SiN film having a compressive stress is formed for PMOS. In order to greatly improve the carrier mobility using this method, the strain applied to the channel region may be increased by increasing the thickness of the liner film. In many cases, the SiN film used in the NMOS uses a method of generating a tensile stress by causing film shrinkage by a post-deposition process.

  It is also known that the liner film has a multilayer structure when the film thickness of the liner film is increased. In this case, film shrinkage may be performed for each layer. For example, Patent Document 4 reports a structure in which a liner film is multilayered.

  In order to effectively strain the channel region, a film having a large stress is preferable as it approaches the channel region. In recent years, for example, a method of forming a liner film having stress after removing the sidewall before forming the liner film by a disposable sidewall technique has been proposed (for example, see Patent Document 5). Also, a method has been proposed in which the strain applied to the channel region is increased by forming the SiGe epitaxial layer as close to the channel region as possible by forming Σ-type SiGe source / drain regions (for example, non-patented). Reference 3). However, each of these methods requires a process of selectively forming a film using NMOS or PMOS, and thus has problems such as a large mask cost and a large number of processes. Small effect.

JP 2006-196549 A JP 2006-216955 A JP 2003-060076 A Japanese Patent No. 3050193 JP 2008-091536 A

Yee-Chia Yeo, "SSDM", 2006, p.162-163 Yaocheng Liu et al., "VLSI Tech. Dig.", 2007, p.44-45 Hiroyuki Ota et al., Technical report of IEICE. SDM 105 (541), January 13, 2006, p.13-16

  However, the above-described conventional technique for increasing the speed of the transistor by applying distortion to the channel region has the following problems.

  First, when miniaturization and high integration are further advanced, the distance between the elements is reduced, and the distance between the MOS transistors is also reduced. For this reason, when the liner film is increased in thickness, the liner film is also formed thickly on each of the source region and the drain region of the transistor. Therefore, the region between the gate electrodes of adjacent MOS transistors is also formed by the liner film. It will be buried. This causes problems such as difficulty in contact formation.

In addition, regarding a technique for forming a SiGe epitaxial layer in a source region and a drain region, for example, a region where NMOS and PMOS separated from each other by STI (shallow trench isolation) are crushed like a static random access memory (SRAM) region Then, since epitaxial growth does not occur at the STI end formed of SiO ₂ , it becomes difficult to apply strain to the channel. That is, as miniaturization progresses, it becomes difficult to apply SiGe epitaxial strained Si technology.

  As described above, the conventional strain technique has a problem that the amount of strain that can be applied to the channel region is reduced with miniaturization, so that it is difficult to deal with CMOS devices having a design rule of 32 nm or later.

  Accordingly, an object of the present invention is to provide a new strain technique that can effectively apply tensile strain to the channel region of an n-channel transistor and compressive strain to the channel region of a p-channel transistor even when miniaturized. And

  In order to achieve the above object, the inventors of the present application focused on the internal stress of the film constituting the metal (metal) gate electrode, and as a result of detailed evaluation, the following invention was conceived.

  That is, a first semiconductor device according to the present invention includes a gate electrode formed on a n-channel transistor formation region in a substrate via a gate insulating film, and the gate electrode is an n-channel metal electrode having a compressive internal stress. Have

  According to the first semiconductor device of the present invention, since the n-channel metal electrode has a compressive internal stress (that is, the n-channel metal electrode itself is about to expand), the n-channel metal electrode is provided in the channel region of the n-channel transistor. A tensile strain in the direction opposite to the internal stress is applied. Here, since the thickness of the gate insulating film (for example, High-k gate insulating film) on the lower side of the n-channel metal electrode is about several nanometers at most, the n-channel metal electrode is very close to the channel region. Compared with the stress application by the liner film formed on the upper side of the gate electrode, the channel region can be effectively strained by the n-channel metal electrode. Further, as will be described in detail in the embodiment, if the thickness of the n-channel metal electrode film is about 10 nm or more, effective strain application is possible. Tensile strain can be effectively applied to the substrate.

  The second semiconductor device according to the present invention further includes a gate electrode formed on a p-channel transistor formation region in the substrate via a gate insulating film, and the gate electrode is a p-channel metal electrode having a tensile internal stress. Have

  According to the second semiconductor device of the present invention, the p-channel metal electrode has tensile internal stress (that is, the p-channel metal electrode itself is about to contract), and therefore the p-channel metal electrode is provided in the channel region of the p-channel transistor. A compressive strain in the direction opposite to the internal stress is applied. Here, since the thickness of the gate insulating film (for example, High-k gate insulating film) below the p-channel metal electrode is about several nanometers at most, the p-channel metal electrode is very close to the channel region. Compared with the stress application by the liner film formed on the upper side of the gate electrode, the channel region can be effectively strained by the p-channel metal electrode. Further, as described in detail in the embodiment, since the effective strain application is possible if the thickness of the p-channel metal electrode film is about 10 nm or more, the channel region of the p-channel transistor can be obtained even if it is miniaturized. Tensile strain can be effectively applied to the substrate.

  A third semiconductor device according to the present invention includes a first gate electrode formed on a n-channel transistor formation region in a substrate through a first gate insulating film, and a p-channel transistor formation region in the substrate. And a second gate electrode formed through a second gate insulating film, wherein the first gate electrode has an n-channel metal electrode having a compressive internal stress, and the second gate electrode is , Having a p-channel metal electrode with tensile internal stress.

  According to the third semiconductor device of the present invention, it is possible to obtain the combined effect of the first and second semiconductor devices according to the present invention.

  According to the present invention, tensile strain can be effectively applied to the channel region of the n-channel transistor, and compressive strain can be effectively applied to the channel region of the p-channel transistor. Further, since strain is applied to the channel region using the internal stress of the film constituting the metal gate electrode, the liner film or SiGe source Unlike conventional strain techniques such as drains, there are no restrictions.

  Furthermore, according to the present invention, if the thickness of the metal electrode film is about 10 nm or more, effective strain application is possible, so that it is not necessary to form a thick metal electrode film that cannot be gated. Therefore, for example, a CMOS transistor having a high-k gate insulating film / metal gate electrode structure can be easily formed while enabling high speed and high integration of the CMOS transistor.

FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention. FIG. 2 shows the results of investigation by the inventors of the present invention on the amount of wafer warpage when a metal electrode film having a tensile internal stress and a metal electrode film having a compressive internal stress are respectively formed on a silicon wafer. FIG. 3 shows the results of investigation by the inventors of the present invention on the dependence of the strain amount on the channel region on the thickness of the metal electrode film (TiN film). FIG. 4 is a diagram showing the drive capability of the n-channel transistor in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram showing the drive capability of the p-channel transistor in the semiconductor device according to the first embodiment of the present invention. 6A to 6F are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 7A to 7E are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIGS. 8A to 8D are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention, specifically, a semiconductor device having a CMOS structure.

  As shown in FIG. 1, an element isolation layer 104 made of, for example, a silicon oxide film and having an STI shape is formed on a semiconductor substrate 101 made of, for example, silicon, whereby a p-channel transistor 105 and an n-channel transistor are formed. 106 is partitioned. For example, an n-type well region 102 is formed in the semiconductor substrate 101 of the p-channel transistor 105 by ion implantation, and a p-type well region 103 is formed in the semiconductor substrate 101 of the n-channel transistor 106 by, for example, ion implantation. .

  The p-channel transistor 105 includes a p-type source / drain region 107 and a p-type extension region 108 formed by, for example, ion implantation, and is formed on a gate insulating film 109 made of, for example, a high-k insulating film. The metal electrode 110 having a tensile internal stress, which is one of the features of the embodiment, is provided. On the metal electrode 110, a polysilicon electrode 111 in which an impurity such as boron is ion-implanted is formed. The metal electrode 110 and the polysilicon electrode 111 constitute a gate electrode of the p-channel transistor 105. In addition, an insulating sidewall spacer 112 made of, for example, a silicon nitride film or a silicon oxide film is formed on the side wall of the gate electrode.

  Although not shown, a silicide layer made of, for example, nickel silicide (NiSi) or nickel platinum silicide (NiPtSi) is formed on each surface portion of the p-type source / drain region 107 and the polysilicon gate electrode 111. It may be formed. Although not shown, a SiGe epitaxial layer containing germanium (Ge), for example, about 10 atomic% to 30 atomic% may be formed in the p-type source / drain region 107 and the p-type extension region 108.

  On the other hand, the n-channel transistor 106 includes an n-type source / drain region 113 and an n-type extension region 114 formed by, for example, ion implantation, and a gate insulating film 115 made of, for example, a high-k gate insulating film. On top, a metal electrode 116 having a compressive internal stress, which is a feature of the present embodiment, is provided. Note that a polysilicon electrode 117 into which an impurity such as phosphorus is ion-implanted is formed on the metal electrode 116, and the gate electrode of the n-channel transistor 106 is configured by the metal electrode 116 and the polysilicon electrode 117. In addition, an insulating sidewall spacer 118 made of, for example, a silicon nitride film or a silicon oxide film is formed on the side wall of the gate electrode.

  Although not shown, a silicide layer made of, for example, nickel silicide (NiSi) or nickel platinum silicide (NiPtSi) is formed on each surface portion of the n-type source / drain region 113 and the polysilicon gate electrode 117. It may be formed. Although not shown, a SiGe epitaxial layer containing germanium (Ge), for example, about 10 atomic% to 30 atomic% may be formed in the p-type source / drain region 107 and the p-type extension region 108. Although not shown, even if a carbon-doped Si epitaxial layer containing about 1 atomic% to 3 atomic% of carbon (C) is formed in the n-type source / drain region 113 and the n-type extension region 114, for example. good.

  In the present embodiment, the gate insulating film (High-k gate insulating film) 109 of the p-channel transistor 105 is formed in a High-k film made of an oxide film containing, for example, Hf or Zr and Si. Al and Ta for controlling the function are included. Further, the gate insulating film (High-k gate insulating film) 115 of the n-channel transistor 106 is for controlling a work function in a High-k film composed of, for example, an oxide film containing Hf or Zr and Si. La, Mg and the like are included.

  Further, in this embodiment, the metal electrode 110 of the p-channel transistor 105 and the metal electrode 116 of the n-channel transistor 106 are each one metal selected from a metal group including Al, Ti, Ta, W, and Ru. A metal film comprising a plurality of metals selected from the metal group, a nitride film or carbonitride film containing at least one metal selected from the metal group, or of the metal group It may be a nitride film containing at least one metal selected from the above and silicon. Here, as described above, the metal electrode 110 of the p-channel transistor 105 has a tensile internal stress, and the metal electrode 116 of the n-channel transistor 106 has a compressive internal stress.

By the way, in the conventional strain technique, a liner film serving as a contact etching stopper is formed of a silicon nitride film having a large internal stress, so that strain is applied to the channel region, or SiGe or SiC is epitaxially grown in the source / drain regions. For example, the channel region is distorted by embedding by. However, due to the miniaturization and high integration of transistors, there may be a case where a liner nitride film is not sufficiently embedded between adjacent gates. Further, due to the distance from the STI to the gate, that is, the reduction in the area of the source / drain region, epitaxial growth does not occur at the end of the STI formed by SiO ₂ instead of the Si crystal, and there is a burying failure or the source / drain. In some cases, the contact hole may be poorly connected. When these defects occur, problems such as a decrease in yield occur.

  On the other hand, in this embodiment, the strain to the channel region is controlled by the metal electrode formed on the gate insulating film closest to the channel region, so that regardless of the distance between the gates and the area of the source / drain regions. Thus, an appropriate distortion can be effectively applied to the channel region. Thereby, the driving capability of each of the p-channel transistor 105 and the n-channel transistor 106, that is, the driving capability of the CMOS transistor can be improved.

  Further, in this embodiment, if the thickness of the metal electrode film is about 10 nm or more, effective strain application is possible, so that it is not necessary to form a thick metal electrode film that cannot be gated. Therefore, for example, a CMOS transistor having a high-k gate insulating film / metal gate electrode structure can be easily formed while enabling high speed and high integration of the CMOS transistor.

  The amount of strain applied to the channel region is similar to the amount of strain applied to the bulk, as shown in (Equation 3) below (Hooke's law), and “stress” and “Young's modulus (longitudinal elastic modulus) that apply force. It is possible to estimate from Young's modulus is a constant that determines how much stress is required per unit strain in the elastic range.

[Strain ε] = [Stress σ] / [Young's modulus E] (Formula 3)
The amount of strain along the direction of tensile stress or compressive stress in which the stress direction is one direction can be obtained from the linear equation (Equation 3), but in an actual device, in a three-dimensional object Therefore, the distortion is simulated by displaying the tensor component using a cubic square matrix.

  In addition, for example, the Young's modulus of titanium nitride film (TiN) depends on the composition ratio of Ti and N, and while the Young's modulus increases with TiN close to the stoichiometric ratio, the nitrogen ratio is higher than the stoichiometric ratio. If it falls, Young's modulus will also fall.

  Young's modulus can be measured by the membrane deflection method, the indentation test, Brillouin scattering technique, ultrasonic microscopy, the resonance microscopy (the resonance) There are several types of static or dynamic methods such as vibration test). However, these methods are not suitable for measuring the Young's modulus of a film having a thickness of nanometer level used in a fine semiconductor device because it has a special feature such as requiring special sample preparation.

  Therefore, in this embodiment, laser-induced acoustic waves are used to measure the Young's modulus of a metal electrode film having a thickness of several tens of nm (specifically, a TiN film having a thickness of 15 nm). Specifically, the surface of the sample was irradiated with a pulse laser to generate surface acoustic waves, and the frequency dependence (dispersion curve) of the propagation velocity was measured. Since this dispersion curve is determined by four parameters of Young's modulus, density, Poisson's ratio, and film thickness, it is possible to obtain an unknown parameter by fitting by measuring the dispersion curve and inputting a known parameter. Become.

The Young's modulus measurement sample has a structure in which a 15 nm thick TiN film is formed on a 100 nm thick silicon oxide film formed on a silicon substrate. When the Young's modulus was calculated with the film density of the TiN film being 5.43 g / cm ³ and the Poisson's ratio being 0.21, the TiN film formed by, for example, PVD (physical vapor deposition) has a very large Young's modulus of 883 GPa. I understood. It was also found that the TiN film formed by ALD (Atomic Layer Deposition) also has a very large Young's modulus of 810 GPa.

  On the other hand, as a stress measuring method, a measuring method using a warp amount of a silicon substrate (wafer) is generally used. That is, when a film is formed on a silicon substrate, the thermal expansion coefficient of the silicon substrate and the thermal expansion coefficient of the film are different. Can be measured. In this wafer warpage measurement, the position of the light source is moved so that the focal length between the wafer and the light source at each measurement position is constant while the wafer is supported at three points so that the center and the center of gravity of the wafer coincide. This is implemented by measuring the transition of the light source position. Based on the change amount (curvature radius) of the warp of the wafer, the stress can be calculated using the Stony equation shown in the following (Equation 4).

(Stress) = (Young's modulus of substrate) · (Thickness of substrate) ² / (6 · Radius of curvature · Film thickness · (1−Poisson's ratio of substrate))
In this embodiment, the internal stress of the metal electrode film was measured using a 300 mm diameter silicon wafer having a thickness of 775 μm. The result is shown in FIG. FIG. 2A shows the amount of warpage of the wafer when a TiN film is formed by PVD. According to this, the TiN film formed by PVD distorts a 300 mm diameter silicon wafer in a convex shape up to about 50 μm, and according to (Equation 4), the TiN film formed by PVD is about 3.0 GPa. It can be seen that it has a compressive internal stress of FIG. 2B shows the amount of warpage of the wafer when a TiN film is formed by ALD. According to this, the TiN film formed by ALD distorts a 300 mm diameter silicon wafer into a concave shape up to about 30 μm, and according to (Equation 4), the TiN film formed by ALD is about 1.5 GPa. It can be seen that there is a tensile internal stress.

  When the inventors of the present application have investigated, when a film is thermochemically grown, such as a CVD (Chemical Vapor Deposition) method or an ALD method, the film often has tensile internal stress. Thus, it was found that the film often had compressive internal stress when the wafer was not heated. Specifically, the W (tungsten) film formed by CVD has a tensile internal stress of about 1.5 GPa, and the Ta (tantalum) film formed by PVD has a compressive internal stress of about 2.5 GPa and is formed by PVD. The TaN film has a compressive internal stress of about 1.6 GPa.

  FIG. 3 shows the result of simulating the distortion applied to the channel region. As shown in FIG. 3, when a TiN film is formed by PVD, the internal stress of the TiN film is a compressive stress, but the TiN film causes a tensile strain in the channel region under the gate. It can be seen that the TiN film is preferably used for the metal gate electrode of the n-channel transistor. On the other hand, as shown in FIG. 3, when a TiN film is formed by ALD, the internal stress of the TiN film is a tensile stress, but the compressive strain is applied to the channel region under the gate by the TiN film. It can be seen that the formed TiN film is preferably used for the metal gate electrode of the p-channel transistor.

  Further, as shown in FIG. 3, when the amount of strain that can be applied to the channel region according to the above (Equation 3) was simulated using the aforementioned Young's modulus and internal stress, both the n-channel transistor and the p-channel transistor were It has been found that the amount of strain in the direction from the source to the drain (hereinafter referred to as the X direction) becomes relatively large when the thickness of the TiN film is about 10 to 50 nm, and particularly about 15 to 25 nm. For example, when a TiN film formed by PVD is used for an n-channel transistor, a strain amount of about 350 can be applied when the thickness of the TiN film is about 20 nm. For example, when a TiN film formed by ALD is used for a p-channel transistor, a strain amount of about 240 can be applied when the thickness of the TiN film is about 20 nm.

  In the case of a liner film, which is another strain technique, the amount of strain increases as the film thickness is increased. In the case of SiGe source / drain, which is another strain technique, the Ge concentration in SiGe can be increased. Unlike the fact that the amount of strain increases as the number increases, the amount of strain applied by the metal electrode film of the present embodiment is characterized by saturation at a film thickness of about 15 to 25 nm.

  Further, in the method using the liner film described above, even if a silicon nitride film having a thickness of about 30 nm having a stress equivalent to 1.6 GPa is used, if an insulating sidewall spacer exists on the side wall of the gate electrode, X The amount of distortion in the direction is about 150. This is because the presence of the insulating sidewall spacer increases the distance between the liner film and the channel region under the gate, and as a result, the amount of strain decreases as the distance increases. However, according to the disposable sidewall technique in which the liner film is formed after removing the insulating sidewall spacer, it is possible to apply a strain amount of about 350 in the X direction. For example, when used in combination with a TiN film formed by PVD, a total amount of strain of about 700 or more can be applied to the channel region of the n-channel transistor. Alternatively, the SiC source / drain technology is used in combination with the metal electrode film (for example, TiN film formed by PVD) of this embodiment instead of or together with the liner film (for example, SiN film) having tensile stress. The strain amount may be applied to the channel region of the n-channel transistor.

  Similarly, if SiGe source / drain technology is used in combination with the metal electrode film of this embodiment (for example, TiN film formed by ALD), a large compressive strain is applied to the channel region of the p-channel transistor to improve the drive current. Can be made. Here, instead of the SiGe source / drain technology or together with the SiGe source / drain technology, a liner film (for example, SiN film) having compressive stress is combined with the metal electrode film (for example, TiN film formed by ALD) of the present embodiment. By using it, the amount of strain may be applied to the channel region of the p-channel transistor.

  FIG. 4 is a diagram showing an improvement in driving current when tensile strain is applied to the channel region by using a TiN film having compressive internal stress for the metal gate electrode of the n-channel transistor. As shown in FIG. 4, for example, when the off-current (Ioffs) is 1000 pA / μm, the on-current (Ion) is changed from 817 μA / μm (×) to 909 μA by using a TiN film having a compressive internal stress. / Μm (circle) is improved by 10% or more.

  FIG. 5 is a diagram showing an improvement in driving current when compressive strain is applied to the channel region by using a TiN film having tensile internal stress for the metal gate electrode of the p-channel transistor. As shown in FIG. 5, for example, when the off current (Ioffs) is 100 pA / μm, by using a TiN film having a tensile internal stress, the on current (Ion) is changed from 286 μA / μm (×) to 309 μA. It is improved by 8% or more to / μm (circle mark).

  As described above, the inventors of the present application examined in detail the internal stress of various metal electrode films used for the metal gate electrode, and as a metal electrode film on the gate insulating film (for example, a high-k gate insulating film), By forming a metal electrode film having a tensile internal stress in a p-channel transistor and forming a metal electrode film having a compressive internal stress in an n-channel transistor, a strain amount more than that which can be applied by a conventional liner film is applied to the channel region. It has been found that the drive current can be improved by application.

  In other words, the present embodiment is based on this new knowledge and exhibits features and effects different from those of the prior art. For example, in this embodiment, since the strain is applied to the channel region using the internal stress of the film constituting the metal gate electrode, even if it is miniaturized, that is, the pitch between the transistors is reduced, Unlike conventional strain techniques such as liner film and SiGe source / drain, there are no restrictions. Further, if the thickness of the metal electrode film is about 10 nm or more, effective strain application is possible, so that it is not necessary to form a thick metal electrode film that cannot be gated. Therefore, for example, a CMOS transistor having a high-k gate insulating film / metal gate electrode structure can be easily formed while enabling high speed and high integration of the CMOS transistor.

  In this embodiment, the material of the metal gate electrodes of the n-channel transistor and the p-channel transistor is not limited to the TiN film, and for example, the metal gate electrode of the p-channel transistor has the above-described tensile internal stress. A TaN film or W film formed by CVD or ALD may be used. For example, a TaN film or Ta film formed by PVD having the above-described compressive internal stress is used as a metal gate electrode of an n-channel transistor. May be.

  In this embodiment, a metal gate electrode having stress is used for each of the n-channel transistor and the p-channel transistor in the CMOS structure. Instead, only one of the transistors has a predetermined stress. A metal gate electrode may be used.

  In this embodiment, a polysilicon electrode is formed on the metal gate electrode in each of the n-channel transistor and the p-channel transistor. Instead, a silicon germanium electrode may be formed, or a metal gate may be formed. A polysilicon electrode or the like may not be formed on the electrode.

  Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 6A, an n-type well region 102 and a p-type semiconductor substrate 101 made of, for example, silicon are insulated and separated by an element isolation layer 104 made of, for example, a silicon oxide film and having an STI shape. After the well region 103 is formed, an insulating film 109A serving as a gate insulating film is formed on the entire surface of the semiconductor substrate 101, and then a tensile internal stress of a p-channel transistor (hereinafter referred to as PMOS) is formed on the insulating film 109A. A metal-containing film 110A to be a metal electrode is formed.

  Here, the insulating film 109A includes, for example, a silicon oxide film having a thickness of about 1.0 nm formed by oxidizing the surface of the semiconductor substrate 101 in a water vapor atmosphere or a nitrogen monoxide atmosphere, and Hf or An oxide mainly composed of a group 4 element such as Zr, an oxide of Hf or Zr and Si (silicate), an oxide of Hf or Zr and Al (aluminate), or plasma nitridation of these oxides It has a laminated structure with a high-k insulating film made of oxynitride to which nitrogen is added by ammonia nitriding. For example, a MOCVD (metal organic chemical vapor deposition) method, an ALD method, or a PVD method is used to form the high-k insulating film. In addition, when performing nitriding such as plasma nitriding or ammonia nitriding, it is preferable to perform heat treatment at, for example, 1000 ° C. or higher.

  In order to control the threshold voltage, it is preferable to add different high-k materials to the n-channel transistor (hereinafter referred to as NMOS) and PMOS high-k insulating films. For example, La oxide or Mg oxide is preferably added to the NMOS high-k insulating film, and Al oxide or Ta oxide is preferably added to the PMOS high-k insulating film.

In the present embodiment, as the metal-containing film 110A, a TiN film is formed by using, for example, an ALD method. Specifically, a liquid source such as titanium chloride (TiCl ₄ ) is used as the Ti source, and TiCl ₄ gas vaporized by bubbling the liquid source with an inert gas such as Ar is t1 second (for example, 0.05 seconds), and Ti is adsorbed on the insulating film 109A. Next, in order to discharge the TiCl ₄ gas filled in the chamber, nitrogen gas is supplied at a flow rate of 1000 mL / min (standard state) for t2 seconds (eg, 0.3 seconds). Thereafter, ammonia that is a nitrogen source gas is supplied at, for example, 1000 mL / min (standard state) for t3 seconds (for example, 1 second), thereby bonding Ti and N adsorbed on the insulating film 109A. Thereafter, in order to remove ammonia gas filled in the chamber, nitrogen gas is supplied at a flow rate of, for example, 1000 mL / min (standard state) for t4 seconds (for example, 0.3 seconds). By repeating the series of gas supply cycles described above, a TiN film is formed until a desired film thickness is reached. Here, the metal-containing film 110A made of a TiN film has a tensile internal stress of 1.0 GPa or more and a film thickness of 15 nm or more and 25 nm or less (for example, 20 nm) so that the strain amount to the channel region is maximized. ). Other deposition conditions for the metal-containing film 110A include, for example, a chamber pressure of 0.5 Torr (about 66.5 Pa) and a stage heater temperature of 550 ° C. Also, when a TiN film is manufactured as the metal-containing film 110A, instead of the combination of TiCl ₄ and ammonia, an amino or imide material is used as the Ti source, and plasma is applied to ammonia as the nitrogen source. It is also possible to use ammonia radicals obtained or ionized nitrogen.

  Subsequently, after applying a resist on the entire surface of the metal-containing film 110A, the resist in the NMOS region is removed by photolithography, and then the resist (not shown) covering the PMOS region is used as a mask in FIG. 6B. As shown, after removing the metal-containing film 110A in the NMOS region with a mixed solution of sulfuric acid and hydrogen peroxide, for example, the remaining resist is removed. Here, the insulating film 109A functions as an etching stopper. Alternatively, the metal-containing film 110A in the NMOS region may be removed by dry etching using a halogen-based etching gas instead of wet etching.

Next, as shown in FIG. 6C, a metal-containing film 116A serving as a metal electrode having a compressive internal stress of NMOS is formed on the entire surface of the substrate. In the present embodiment, as the metal-containing film 116A, a TiN film is formed using, for example, a PVD method. Here, the TiN film may be formed by sputtering a TiN target with Ar. Alternatively, a reactive sputtering method in which a TiN film is formed by reacting a nitrogen-based gas such as N ₂ and Ti after sputtering a Ti target with Ar may be used. In this embodiment, a TiN film having a thickness of about 15 to 25 nm is formed by using a reactive sputtering method under the conditions of DC power 1000 W, Ar flow rate 20 mL / min (standard state), and N ₂ flow rate 18 mL / min (standard state). Formed.

  Subsequently, after applying a resist on the entire surface of the metal-containing film 116A, the resist in the PMOS region is removed by photolithography, and then, for example, sulfuric acid and hydrogen peroxide are used with a resist (not shown) covering the NMOS region as a mask. After removing the metal-containing film 116A in the PMOS region with a mixed solution with water, the remaining resist is removed. At this time, the surface of the metal-containing film 110A in the PMOS region is covered with a natural oxide film. In etching with a mixed solution of sulfuric acid and hydrogen peroxide solution, the TiN film formed by PVD has a higher etching rate than the TiN film formed by ALD. A ratio arises. Therefore, the metal-containing film 116A formed on the metal-containing film 110A in the PMOS region can be easily removed.

Next, in order to remove the remaining metal-containing film 110A and the natural oxide film formed on the metal-containing film 116A and the TiN layer altered by the application and removal of the resist, the metal is removed by using an aqueous solution containing hydrofluoric acid, for example. After cleaning the surfaces of the containing film 110A and the metal-containing film 116A, a polysilicon film having a thickness of about 100 nm is formed on each of the metal-containing film 110A and the metal-containing film 116A. Here, if an oxide layer is present at the interface between the TiN film and the polysilicon film, the interface resistance increases. Therefore, before the formation of the polysilicon film, the respective surfaces of the metal-containing film 110A and the metal-containing film 116A are exposed. It is better to perform additional cleaning with ammonia and hydrogen peroxide. As a method for forming a polysilicon film, for example, a silicon film is formed at a temperature of 500 ° C. to 650 ° C. using silane (SiH ₄ ) or disilane (Si ₂ H ₆ ), and then the silicon film is subjected to heat treatment. There are a method for forming a polysilicon film and a method for forming a polysilicon film by flowing silane at 600 ° C. to 630 ° C. Further, instead of the polysilicon film, germanium (GeH ₄ ) may be added to silane to form a silicon germanium film.

  Next, a resist pattern (not shown) that covers the gate electrode formation region is formed using a photolithography technique and an etching technique, and then the above-described resist pattern is used as a mask, for example, with a halogen-based etching gas. Anisotropic etching is performed on the polysilicon film, the metal-containing film 110A, and the metal-containing film 116A. As a result, as shown in FIG. 6D, a stacked structure of the metal electrode 110 and the polysilicon electrode 111 is formed on the n-type well region 102 as a PMOS gate electrode via the gate insulating film 109. As a gate electrode of NMOS, a laminated structure of a metal electrode 116 and a polysilicon electrode 117 is formed on the p-type well region 103 with a gate insulating film 115 interposed therebetween. That is, a metal electrode having different internal stresses can be formed between the NMOS and the PMOS, so that a tensile stress can be applied to the NMOS channel region and a compressive stress can be applied to the PMOS channel region. Can do.

  In the above-described gate electrode etching, the metal-containing film 110A and the metal-containing film 116A are not the same film thickness, so that an etching selectivity is ensured between the metal-containing film 110A and the metal-containing film 116A and the insulating film 109A. Etching conditions that can be used are used. Thereby, the gate electrode etching can be stopped at the insulating film 109A. Note that if the insulating film 109A is subjected to nitriding treatment and subsequent heat treatment at 1000 ° C. or higher, an etching selectivity is ensured between each of the metal-containing film 110A and the metal-containing film 116A and the insulating film 109A. It's easy to do. Following the above-described gate electrode etching, the insulating film 109A (insulating film 109A outside each gate electrode) remaining during the gate electrode etching is removed using, for example, a hydrofluoric acid-based cleaning solution.

  In this embodiment, the metal-containing film 116A formed on the metal-containing film 110A in the PMOS region is removed. However, since the metal-containing film 116A and the channel region of the PMOS region are separated from each other by the total thickness of the thickness of the insulating film 109A and the thickness of the metal-containing film 110A of the PMOS region, the channel is separated from the metal-containing film 116A. The amount of distortion applied to the region is small. Therefore, the metal-containing film 116A formed on the metal-containing film 110A in the PMOS region is not necessarily removed.

  In addition, for lithography for forming a gate electrode whose design rule is finer than 45 nm, for example, an immersion lithography technique is used. For example, in a large-diameter wafer of 300 mm, the substrate active from the center part to the peripheral part of the wafer is used. It is difficult to keep the overlay accuracy of the region and the gate electrode high, and the warpage of the wafer caused by the metal gate electrode cannot be ignored. However, in this embodiment, since a film having a compressive internal stress is used as the n-channel metal gate electrode and a film having a tensile internal stress is used as the p-channel metal gate electrode, the warpage of the wafer caused by each metal gate electrode is offset. As a result, the overlay accuracy between the base active region and the gate electrode can be improved.

Next, a silicon nitride film (not shown) is formed on the entire surface of the substrate at a film formation temperature of 600 ° C. or less, for example. As a method for forming the silicon nitride film, for example, an ALD method is preferable. Specifically, for example, a silicon nitride film having a thickness of about 5 nm to 10 nm is formed by alternately supplying dichlorosilane (SiH ₂ Cl ₂ ) and ammonia. Subsequently, for example, by performing anisotropic dry etching on the silicon nitride film using a halogen-based gas, the silicon nitride film is left as an offset spacer only on the gate electrode sidewall of each transistor.

  Next, for example, phosphorus, arsenic, antimony, or the like is ion-implanted as an n-type impurity into the p-type well region 103 while protecting the NMOS region with a resist (not shown). Next, after removing the resist covering the NMOS region, boron or indium or the like is ion-implanted as a p-type impurity into the n-type well region 102 while protecting the PMOS region with a resist (not shown). Then, after removing the resist covering the PMOS region, the implanted ion species are activated by, for example, heat treatment at 1000 ° C. or more, thereby forming a p-type on the surface portion of the n-type well region 102 as shown in FIG. An extension region 108 is formed, and an n-type extension region 114 is formed on the surface portion of the p-type well region 103.

  Next, for example, a silicon oxide film having a thickness of about 5 nm to 10 nm and a silicon nitride film having a thickness of about 10 nm to 30 nm are successively stacked on the entire surface of the substrate, and then anisotropic dry etching is performed on each film. I do. As a result, as shown in FIG. 6F, an insulating sidewall spacer 112 is formed on the side wall of the PMOS gate electrode, and an insulating side wall spacer 118 is formed on the side wall of the NMOS gate electrode. In addition, as the structure of the insulating sidewall spacers 112 and 118, a two-layer structure of a silicon oxide film and a silicon nitride film is used. Instead, a one-layer structure of a silicon oxide film or a one-layer structure of a silicon nitride film is used. May be used.

  Next, for example, phosphorus, arsenic, antimony, or the like is ion-implanted as an n-type impurity into the p-type well region 103 while protecting the NMOS region with a resist (not shown). Next, after removing the resist covering the NMOS region, boron or indium or the like is ion-implanted as a p-type impurity into the n-type well region 102 while protecting the PMOS region with a resist (not shown). Thereafter, after removing the resist covering the PMOS region, the implanted ion species are activated by, for example, heat treatment at about 900 ° C. to 1050 ° C., so that the p-type is formed in the n-type well region 102 as shown in FIG. A source / drain region 107 is formed, and an n-type source / drain region 113 is formed in the p-type well region 103.

  Subsequently, although not shown, after siliciding the upper portions of the source / drain regions 107 and 113 and the upper portions of the polysilicon electrodes 111 and 117 using, for example, Ni or Pt, For example, a silicon nitride film serving as a contact hole etching stopper and, for example, a silicon oxide film serving as an interlayer insulating film are sequentially formed, and then a planarization process or the like is performed, whereby the semiconductor device of this embodiment shown in FIG. Finalize.

  According to the manufacturing method of the present embodiment described above, the metal-containing film 110A having a tensile internal stress and the metal-containing film 116A having a compressive internal stress are formed on the semiconductor substrate 101 when performing photolithography for gate patterning. Therefore, warping of the semiconductor substrate 101 can be suppressed, so that photolithography can be performed with high accuracy.

  In the manufacturing method of the present embodiment, after the metal-containing film 110A that becomes the PMOS metal electrode is formed, the metal-containing film 116A that becomes the NMOS metal electrode is formed, but instead, the metal-containing film 116A is formed. After the formation, the metal-containing film 110A may be formed.

  In the manufacturing method of the present embodiment, the ALD method is used when forming the metal-containing film 110A to be a metal electrode having a PMOS compressive internal stress. Instead, for example, a thermal CVD method, a plasma method is used. A CVD method, an MOCVD method, or the like may be used.

  Further, in the manufacturing method of the present embodiment, the reactive sputtering method is used when forming the metal-containing film 116A to be a metal electrode having an NMOS compressive internal stress. Alternatively, a direct current magnetron sputtering method, a high frequency magnetron sputtering method, an ionization sputtering method, an ion beam sputtering method, or the like may be used.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIGS. 7A to 7E and FIGS. 8A to 8D are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  First, as shown in FIG. 7 (a), an n-type well region 202 and a p-type semiconductor substrate 201 made of, for example, silicon and insulated by an element isolation layer 204 made of, for example, a silicon oxide film and having an STI shape. A well region 203 is formed.

  Next, after a silicon oxide film 205A having a thickness of about 4 nm is formed on the semiconductor substrate 201 by, for example, a thermal oxidation method, a polysilicon film 206A having a thickness of about 100 nm to 200 nm is formed on the silicon oxide film 205A by, for example, a CVD method. Then, a silicon nitride film 207A having a film thickness of, for example, about 30 nm to 100 nm is deposited on the polysilicon film 206A.

  Next, the silicon nitride film 207A, the polysilicon film 206A, and the silicon oxide film 205A are sequentially etched using a resist pattern (not shown) covering the gate electrode formation region as a mask, so that FIG. As shown, a dummy gate insulating film 205 made of a silicon oxide film, a dummy gate electrode 206 made of polysilicon, and a hard mask layer made of a silicon nitride film on each of the n-type well region 202 and the p-type well region 203. A dummy gate structure in which (protective film) 207 is sequentially stacked is formed. Subsequently, for example, phosphorus is shallowly implanted as an n-type impurity into the p-type well region 203 using, for example, the hard mask layer 207 as a mask, thereby forming an n-type extension region 208. Further, for example, boron is shallowly ion-implanted as a P-type impurity into the n-type well region 202 using the hard mask layer 207 as a mask, thereby forming the p-type extension region 209.

  Next, after a silicon oxide film is deposited on the entire surface of the substrate by, for example, CVD, anisotropic dry etching is performed on the entire surface of the silicon oxide film, as shown in FIG. Insulating sidewall spacers 210 are formed on the sidewalls of the dummy gate structures in the NMOS region and the PMOS region, respectively. Subsequently, n-type source / drain regions 211 are formed by deeply implanting n-type impurities into the p-type well region 203 using, for example, the insulating sidewall spacers 210 and the hard mask layer 207 as a mask. For example, the p-type source / drain region 212 is formed by deeply implanting p-type impurities into the n-type well region 202 using the insulating sidewall spacer 210 and the hard mask layer 207 as a mask.

  Next, although not shown, the entire surface of each of the n-type source / drain region 211 and the p-type source / drain region 212 contains any of titanium, cobalt, nickel, or platinum by sputtering, for example. After the refractory metal film is deposited, a silicidation reaction is caused when the refractory metal film is in contact with each source / drain region (silicon region). As a result, a refractory metal silicide film is formed on the respective surface portions of the n-type source / drain region 211 and the p-type source / drain region 212. Thereafter, the unreacted refractory metal film is removed.

  Next, as shown in FIG. 7D, an interlayer insulating film 213 made of a silicon oxide film is deposited by, for example, a CVD method so as to cover the entire surface of the substrate including the hard mask layer 207, and then the hard mask is formed. CMP (chemical mechanical polishing) is performed on the interlayer insulating film 213 until the upper surface of the layer 207 is exposed.

  Next, as shown in FIG. 7E, the interlayer insulating film 213, that is, the silicon oxide film has an etching resistance and the hard mask layer 207 is easily etched, for example, an etching process using hot phosphoric acid. The mask layer 207 is removed. Subsequently, the dummy gate electrode 206 is removed with a cleaning liquid having a selection ratio between the dummy gate electrode 206 and the dummy gate insulating film 205, for example, an alkaline aqueous solution such as potassium hydroxide. Subsequently, the surface of the dummy gate insulating film 205 exposed by the above-described etching is treated with, for example, an etching gas containing ammonia and hydrogen fluoride, and the product generated thereby is decomposed and evaporated to cause the dummy. The gate insulating film 205 is removed. As described above, the gate electrode trench 214 is formed in the NMOS region and the gate electrode trench 215 is formed in the PMOS region.

  Next, the inner wall surfaces and bottom surfaces of the gate electrode trenches 214 and 215 and the upper surface of the interlayer insulating film 213 are covered with a silicon oxide film by, for example, thermal oxidation, and then Hf or Zr or the like is formed on the silicon oxide film. Oxides mainly composed of Group 4 elements, oxides of Hf or Zr and Si (silicates), oxides of Hf or Zr and Al (aluminates), or plasma nitriding or ammonia nitriding of these oxides A high-k insulating film made of oxynitride to which nitrogen is added is formed. As a result, a gate insulating film 216 composed of a silicon oxide film and a high-k insulating film is formed. Here, for example, the MOCVD method, the ALD method, or the PVD method can be used for forming the high-k insulating film.

  Next, as shown in FIG. 8A, an n-channel metal having a thickness of about 10 to 50 nm (preferably about 15 to 25 nm) having a compressive internal stress is formed on the entire surface of the gate insulating film 216 by, eg, sputtering. An electrode film 217 is formed. The n-channel metal electrode film 217 is, for example, a metal film made of a metal material such as Al, Ta, or Ti, a nitride film containing such a metal material, a silicide film, a nitrogen carbide film, or a carbide film, or a metal material thereof. It consists of an alloy film containing two or more kinds of metals.

  Next, as shown in FIG. 8B, the n-channel metal electrode film 217 formed in the PMOS region is removed. Specifically, for example, a resist is applied to the entire surface of the substrate by a resist coating device such as a spin coater, and then the resist is selectively exposed, and then developed by a resist developing device such as a spin developer. Thus, a resist pattern (not shown) covering the NMOS region is formed. Next, the n-channel metal electrode film 217 formed in the PMOS region is selectively removed by an etching process such as a wet etching method using the resist pattern as a mask. At this time, the n-channel metal electrode film 217 formed in the NMOS region is not removed because it is covered with the aforementioned resist pattern. Subsequently, the aforementioned resist pattern is removed by, for example, plasma ashing.

Next, as shown in FIG. 8C, a thickness of 10 to 50 nm having a tensile internal stress is formed on the entire surface of the gate insulating film 216 including on the n-channel metal electrode film 217 by, for example, the ALD method or the CVD method. A p-channel metal electrode film 218 having a thickness (preferably about 15 to 25 nm) is formed. The p-channel metal electrode film 218 includes, for example, a metal film made of a metal material such as Ti, Ta, Ru, Pt, Mo, W, Ni, and Co, a nitride film containing the metal material, a silicide film, and a carbide film (carbonized film). ), Or an alloy film containing two or more of these metal materials. Subsequently, a conductor material film 219 is formed on the p-channel metal electrode film 218 by, for example, CVD or ALD so that the gate electrode trenches 214 and 215 are filled. The conductor material film 219 is made of, for example, metal, polysilicon, or silicon germanium, and is preferably made of tungsten. The conductive material film 219 is formed by, for example, a process gas such as WF ₆ , H ₂ , SiH ₄ , a substrate temperature of 350 ° C. to 450 ° C., and a pressure of 1 Torr (about 133 Pa) to 100 Torr (about 13300 Pa). ).

  Subsequently, as shown in FIG. 8D, the gate insulating film 216, the n-channel metal electrode film 217, and the p-channel metal electrode formed outside the gate electrode trenches 214 and 215 by polishing such as CMP, for example. The transistor structure is completed by removing the film 218 and the conductor material film 219.

  According to the semiconductor device obtained by the manufacturing method of the present embodiment described above, in addition to the same effects as those of the semiconductor device of the first embodiment, the following effects can be obtained. That is, according to the manufacturing method of the present embodiment, since each metal electrode film 217 and 218 is not cut at the end of the channel region as in the first embodiment, in other words, each metal electrode film 217 and 218. Since the gate electrode trenches 214 and 215 are continuously formed from the bottom surface to the inner wall surface, it is possible to effectively apply a larger strain from the metal electrode films 217 and 218 to the channel region.

  In this embodiment, the p-channel metal electrode film 218 formed on the n-channel metal electrode film 217 in the NMOS region is not removed, but the p-channel metal electrode film 218 and the channel region in the NMOS region are not removed. Since the gate insulating film 216 and the n-channel metal electrode film 217 are interposed between the p-channel metal electrode film 218 and the channel region of the NMOS region, the p-channel metal electrode film The inside of the tensile stress of 218 hardly affects the NMOS. However, it goes without saying that the p-channel metal electrode film 218 formed on the n-channel metal electrode film 217 in the NMOS region may be removed.

  In this embodiment, the n-channel metal electrode film 217 serving as the NMOS metal electrode is formed, and then the p-channel metal electrode film 218 serving as the PMOS metal electrode is formed. Instead, a p-channel metal electrode is formed. After forming the film 218, an n-channel metal electrode film 217 may be formed.

  In the present embodiment, the sputtering method is used when forming the n-channel metal electrode film 217 serving as a metal electrode having the compressive internal stress of NMOS. However, the present invention is not limited to this. A magnetron sputtering method, a high frequency magnetron sputtering method, an ionization sputtering method, an ion beam sputtering method, or the like may be used.

  In the present embodiment, the ALD method or the CVD method is used when forming the p-channel metal electrode film 218 serving as the metal electrode having the compressive internal stress of the PMOS. However, the present invention is not limited to this. Alternatively, a plasma CVD method, an MOCVD method, or the like may be used.

  In the present embodiment, the n-channel metal electrode film 217 and the p-channel metal electrode film 218 are not limited to the material films described above, and the same material films as the metal electrode films in the first embodiment can be used. .

  Further, in the present embodiment, carbon may be introduced into the n-type source / drain region 211 of the NMOS, or a liner film having a tensile stress (on the semiconductor substrate 201 including the gate electrode structure of the NMOS) ( For example, a SiN film) may be formed.

  In the present embodiment, germanium may be introduced into the n-type source / drain region 212 of the PMOS, or a liner film having compressive stress (on the semiconductor substrate 201 including the top of the gate electrode structure of the PMOS). For example, a SiN film) may be formed.

  The semiconductor device and the manufacturing method thereof according to the present invention are preferably used for various electronic devices using a semiconductor integrated circuit.

101 Semiconductor substrate 102 n-type well region 103 p-type well region 104 element isolation layer 105 PMOS (p-channel transistor)
106 NMOS (n-channel transistor)
107 p-type source / drain region 108 p-type extension region 109 gate insulating film 109A insulating film 110 metal electrode 110A metal-containing film 111 polysilicon electrode 112 insulating sidewall spacer 113 n-type source / drain region 114 n-type extension region 115 gate Insulating film 116 Metal electrode 116A Metal-containing film 117 Polysilicon electrode 118 Insulating sidewall spacer 201 Semiconductor substrate 202 N-type well region 203 P-type well region 204 Element isolation layer 205 Dummy gate insulating film 205A Silicon oxide film 206 Dummy gate electrode 206A Polysilicon film 207 Hard mask layer (protective film)
207A Silicon nitride film 208 n-type extension region 209 p-type extension region 210 insulating sidewall spacer 211 n-type source / drain region 212 p-type source / drain region 213 interlayer insulating film 214 gate electrode trench 215 gate electrode trench 216 gate Insulating film 217 n-channel metal electrode film 218 p-channel metal electrode film 219 Conductor material film

Claims (30)

A gate electrode formed on the n-channel transistor formation region in the substrate via a gate insulating film;
The semiconductor device according to claim 1, wherein the gate electrode includes an n-channel metal electrode having a compressive internal stress. The semiconductor device according to claim 1,
The n-channel metal electrode has a thickness of 10 nm or more and 50 nm or less. The semiconductor device according to claim 2,
The n-channel metal electrode has a thickness of 15 nm or more and 25 nm or less. The semiconductor device according to any one of claims 1 to 3,
The n-channel metal gate electrode includes a metal film made of one metal selected from a metal group containing Al, Ti, Ta, W, and Ru, and a metal made of a plurality of metals selected from the metal group. An alloy film, a nitride film or carbonitride film containing at least one metal selected from the metal group, or a nitride film containing at least one metal selected from the metal group and silicon. A featured semiconductor device. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein the n-channel metal electrode is in contact with the gate insulating film. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the gate electrode further includes a polysilicon electrode or a silicon germanium electrode formed on the n-channel metal electrode. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device according to claim 1, wherein the gate insulating film has a high dielectric constant film. In the semiconductor device according to claim 1,
The substrate is a silicon substrate;
A source / drain region into which carbon is introduced is formed on both sides of the gate electrode in the silicon substrate. The semiconductor device according to any one of claims 1 to 8,
A semiconductor device, wherein a liner film having a tensile stress is formed on the substrate including the gate electrode. The semiconductor device according to claim 9.
The semiconductor device according to claim 1, wherein the liner film is a SiN film. A method for manufacturing the semiconductor device according to claim 1,
Forming the gate insulating film on the substrate;
(B) forming a conductive film having at least a metal-containing film to be the n-channel metal electrode on the gate insulating film;
(C) forming the gate electrode by patterning the conductive film;
A step (d) of forming an extension region by introducing an n-type impurity into the substrate after the step (c);
A step (e) of forming an insulating sidewall spacer on the side wall of the gate electrode after the step (d);
After the step (e), a method (f) for forming a source / drain region by introducing an n-type impurity into the substrate is provided. A method for manufacturing the semiconductor device according to claim 1,
Forming a dummy gate structure on the substrate;
(B) after the step (a), introducing an n-type impurity into the substrate to form an extension region;
(C) forming an insulating sidewall spacer on the side wall of the dummy gate structure after the step (b);
After the step (c), a step (d) of forming source / drain regions by introducing n-type impurities into the substrate;
(E) covering the substrate with an insulating film so that the top of the dummy gate structure is exposed after the step (d);
Removing the dummy gate structure to form a recess in the insulating film (f);
A step (g) of forming the gate insulating film on the bottom and side walls of the recess;
Forming a conductive film having at least a metal-containing film serving as the n-channel metal electrode on the gate insulating film so as to fill the recess;
And (i) forming the gate electrode by removing the conductive film located outside the recess. In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the dummy gate structure includes a dummy gate insulating film, a dummy polysilicon electrode, and a protective film sequentially stacked. In the manufacturing method of the semiconductor device of any one of Claims 11-13,
A method of manufacturing a semiconductor device, wherein the metal-containing film to be the n-channel metal electrode is formed by a bipolar sputtering method, a direct current magnetron sputtering method, a high-frequency magnetron sputtering method, an ionization sputtering method, or an ion beam sputtering method. . A gate electrode formed on a p-channel transistor formation region in the substrate via a gate insulating film;
The semiconductor device, wherein the gate electrode has a p-channel metal electrode having a tensile internal stress. The semiconductor device according to claim 15,
The p-channel metal electrode has a thickness of 10 nm or more and 50 nm or less. The semiconductor device according to claim 16, wherein
The p-channel metal electrode has a thickness of 15 nm or more and 25 nm or less. The semiconductor device according to any one of claims 15 to 17,
The p-channel metal gate electrode includes a metal film made of one metal selected from a metal group including Al, Ti, Ta, W, and Ru, and a metal made of a plurality of metals selected from the metal group. An alloy film, a nitride film or carbonitride film containing at least one metal selected from the metal group, or a nitride film containing at least one metal selected from the metal group and silicon. A featured semiconductor device. The semiconductor device according to any one of claims 15 to 18,
The semiconductor device, wherein the p-channel metal electrode is in contact with the gate insulating film. The semiconductor device according to any one of claims 15 to 19,
The semiconductor device, wherein the gate electrode further includes a polysilicon electrode or a silicon germanium electrode formed on the p-channel metal electrode. 21. The semiconductor device according to claim 15, wherein:
The semiconductor device according to claim 1, wherein the gate insulating film has a high dielectric constant film. The semiconductor device according to any one of claims 15 to 21,
The substrate is a silicon substrate;
A source / drain region into which germanium is introduced is formed on both sides of the gate electrode in the silicon substrate. The semiconductor device according to any one of claims 15 to 22,
A semiconductor device, wherein a liner film having a compressive stress is formed on the substrate including the gate electrode. 24. The semiconductor device according to claim 23, wherein
The semiconductor device according to claim 1, wherein the liner film is a SiN film. A method for manufacturing the semiconductor device according to any one of claims 15 to 24, comprising:
Forming the gate insulating film on the substrate;
Forming a conductive film having at least a metal-containing film to be the p-channel metal electrode on the gate insulating film (b);
(C) forming the gate electrode by patterning the conductive film;
A step (d) of forming an extension region by introducing p-type impurities into the substrate after the step (c);
A step (e) of forming an insulating sidewall spacer on the side wall of the gate electrode after the step (d);
And (f) forming a source / drain region by introducing a p-type impurity into the substrate after the step (e). A method for manufacturing the semiconductor device according to any one of claims 15 to 24, comprising:
Forming a dummy gate structure on the substrate;
After the step (a), a step (b) of introducing an p-type impurity into the substrate to form an extension region;
(C) forming an insulating sidewall spacer on the side wall of the dummy gate structure after the step (b);
After the step (c), a step (d) of forming a source / drain region by introducing a p-type impurity into the substrate;
(E) covering the substrate with an insulating film so that the top of the dummy gate structure is exposed after the step (d);
Removing the dummy gate structure to form a recess in the insulating film (f);
A step (g) of forming the gate insulating film on the bottom and side walls of the recess;
Forming a conductive film having at least a metal-containing film to be the p-channel metal electrode on the gate insulating film so as to fill the recess;
And (i) forming the gate electrode by removing the conductive film located outside the recess. 27. The method of manufacturing a semiconductor device according to claim 26,
The method of manufacturing a semiconductor device, wherein the dummy gate structure includes a dummy gate insulating film, a dummy polysilicon electrode, and a protective film sequentially stacked. In the manufacturing method of the semiconductor device of any one of Claims 25-27,
A method of manufacturing a semiconductor device, wherein the metal-containing film to be the p-channel metal electrode is formed by a thermal CVD method, a plasma CVD method, an MOCVD method, or an ALD method. A first gate electrode formed on the n-channel transistor formation region in the substrate via a first gate insulating film;
A second gate electrode formed on a p-channel transistor formation region in the substrate via a second gate insulating film;
The first gate electrode has an n-channel metal electrode having a compressive internal stress,
The semiconductor device, wherein the second gate electrode has a p-channel metal electrode having a tensile internal stress. A method for manufacturing the semiconductor device according to claim 29, comprising:
The n-channel metal electrode and the p-channel metal electrode have stresses in directions opposite to each other, thereby suppressing the warpage of the substrate during lithography for forming the gate electrodes, and thereby the gates. A method for manufacturing a semiconductor device, characterized in that the overlay accuracy between an electrode and an active region serving as an underlayer thereof is improved.

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