JP2011027887A - Electro-optic device, electronic apparatus, and control method of electro-optic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve noise resistance while preventing increase in power consumption in an electro-optic device having a memory circuit holding data signals in a pixel circuit. <P>SOLUTION: The memory circuit holding the data signals is arranged in the pixel circuit. A display data writing period is a period for performing display based on a written data signal while writing a data signal in the pixel circuit. A display data holding period is a period for performing display based on a data signal held in the memory circuit while stopping writing of a data signal in the pixel circuit. When the display data holding period is started (T1), a switching circuit sets power supply potentials (VDH, VDD) to be supplied to power lines for a driving circuit to a second constant potential (3V) lower than first constant potentials (12V, 6V) to be supplied to the power lines in the display data writing period. Before the display data holding period ends (T2), the switching circuit changes the power supply potential to be supplied to the power lines from the second constant potential to the first constant potentials. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electro-optical device, an electronic apparatus, and a control method for the electro-optical device.

  For example, Patent Document 1 describes a liquid crystal display device in which an SRAM portion for holding video data is built in a pixel. This liquid crystal display device stops the supply of power supply voltage to the X driver and Y driver during a period in which video data held in the SRAM portion is supplied to the pixels and static display is performed.

JP 2002-162938 A

  However, when power supply to the X driver and Y driver is stopped, the power supply wiring to the X driver and the power supply wiring to the Y driver are in a floating state (indeterminate state). For this reason, during the period of static display, there arises a problem that malfunctions occur due to the influence of noise and display cannot be performed accurately.

  The present invention has been made in view of the above-described problems, and in an electro-optical device including a memory circuit that holds a data signal in a pixel circuit, by increasing noise resistance while suppressing an increase in power consumption. is there.

  In order to solve the above problems, an electro-optical device according to the present invention includes a pixel circuit provided corresponding to an intersection of a scanning line and a data line, a driving circuit that drives the pixel circuit, and the driving circuit An electro-optical device including a power supply line that supplies a power supply potential to the power supply line and a switching circuit that switches a power supply potential supplied to the power supply line, wherein the pixel circuit includes a pixel electrode and data supplied to the data line A memory circuit that holds a signal and a selection circuit that selects, based on the data signal held in the memory circuit, one of two AC signals having opposite logic levels as an AC signal supplied to the pixel electrode The switching circuit has a display data holding period in which writing of the data signal to the pixel circuit is stopped and display is performed based on the data signal held in the memory circuit. When the power supply potential is supplied, the power supply potential supplied to the power supply line is supplied to the power supply line in a display data writing period in which display is performed based on the written data signal while writing a data signal to the pixel circuit. A second constant potential lower than one constant potential is set, and a power supply potential supplied to the power supply line is changed from the second constant potential to the first constant potential before the display data holding period ends. To do.

According to the above configuration, when the display data holding period is started, the power line for the drive circuit is supplied during the display data writing period until the display data holding period ends. A second constant potential lower than one constant potential is supplied.
Therefore, even during display of a still image, the power line for the drive circuit does not enter a floating state as in the invention described in Patent Document 1. Therefore, malfunction display due to noise can be prevented. In addition, since the second constant potential supplied to the power supply line is lower than the first constant potential supplied during the display data writing period, power consumption increases compared to the invention described in Patent Document 1, Power consumption can be reduced compared to the case where the power supply potential is not switched. Therefore, noise resistance can be enhanced while suppressing an increase in power consumption.

  In the electro-optical device described above, the driving circuit includes a decoder circuit that turns on a scanning signal supplied to the scanning line, and a buffer circuit that level-shifts the output of the decoder circuit. The power supply line may be a power supply line that supplies a power supply potential to the decoder circuit or a power supply line that supplies a power supply potential to the buffer circuit. In this case, the floating state of the power supply line for the decoder circuit provided in the scanning line driving circuit and the power supply line for the buffer circuit provided in the scanning line driving circuit can be eliminated.

  The electro-optical device may further include a selection line corresponding to the data line, and the driving circuit may be configured to turn on a selection signal supplied to the selection line, and to output the decoder circuit at a level. A data signal output circuit comprising a buffer circuit for shifting and a sample and hold circuit for supplying a data signal to the data line when the selection signal is on, and the power supply line supplies a power supply potential to the decoder circuit Or a power supply line for supplying a power supply potential to the buffer circuit. In this case, the floating state of the power supply line for the decoder circuit provided in the data signal output circuit and the power supply line for the buffer circuit provided in the data signal output circuit can be eliminated.

  In the electro-optical device described above, the pixel circuit, the driving circuit, the power supply line, and the switching circuit may be provided in an electro-optical panel. In this case, the power supply potential can be switched in the electro-optical panel.

Also, in the above-described electro-optical device, the first control signal indicating the timing of every predetermined cycle at which writing of the data signal to the pixel circuit can be started, and whether the data signal is written at each timing And a generation circuit that generates a switching signal that defines a timing for switching the power supply potential based on the second control signal indicating whether or not the power supply potential is switched, the switching circuit based on the switching signal generated by the generation circuit The power supply potential supplied to the power supply line may be switched. In this case, the switching signal can be easily generated.
In the electro-optical device described above, the generation circuit may be provided in an electro-optical panel. In this case, the switching signal can be generated in the electro-optical panel.

  An electronic apparatus according to the present invention includes the above-described electro-optical device. Electronic devices include, for example, personal computers, mobile phones, portable information terminals, and the like.

The control method of the electro-optical device according to the invention includes a pixel electrode, a memory circuit that holds a data signal supplied to the data line, and is provided corresponding to an intersection of the scanning line and the data line. A pixel circuit comprising: a selection circuit that selects one of two AC signals having opposite logic levels as an AC signal supplied to the pixel electrode based on a data signal held in the memory circuit; An electro-optical device control method comprising a drive circuit for driving a pixel circuit and a power supply line for supplying a power supply potential to the drive circuit, wherein writing of a data signal to the pixel circuit is stopped and the memory circuit is stopped. When a display data holding period in which display is performed based on the held data signal is started, a power supply potential supplied to the power supply line is written to the pixel circuit. The second constant potential lower than the first constant potential supplied to the power supply line in the display data writing period in which display is performed based on the written data signal, and before the display data holding period ends, The power supply potential supplied to the line is changed from the second constant potential to the first constant potential.
According to the above configuration, the same effect as the electro-optical device according to the invention can be obtained.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment. It is a circuit diagram which shows the structure of the pixel circuit with which the same apparatus is equipped. It is a circuit diagram which shows the structure of the switching circuit with which the apparatus is equipped. It is a timing chart for demonstrating operation | movement of the apparatus. It is a figure for demonstrating the power supply potential supplied to each part of a liquid crystal panel. FIG. 10 is a circuit diagram illustrating a configuration of a power supply switching signal generation circuit according to a second embodiment. 6 is a timing chart for explaining the operation of the power supply switching signal generation circuit. It is a perspective view which shows the specific example of the electronic device which concerns on this invention. It is a perspective view which shows the specific example of the electronic device which concerns on this invention. It is a perspective view which shows the specific example of the electronic device which concerns on this invention.

<1. First Embodiment>
FIG. 1 is a block diagram illustrating a configuration of an electro-optical device 1 according to the first embodiment.
The electro-optical device 1 uses liquid crystal as an electro-optical material, and includes a liquid crystal panel 2 (an example of an electro-optical panel) as a main part. The liquid crystal panel 2 has an element substrate on which a pixel electrode or a thin film transistor (hereinafter referred to as TFT) as a switching element is formed for each pixel, and a counter substrate on which a common electrode common to all pixels is formed. . The element substrate and the counter substrate are attached with a certain gap so that the electrode formation surfaces face each other, and liquid crystal is sandwiched between the gaps. The liquid crystal panel 2 is a reflection type, but may be a transmission type or a semi-transmission type.

  The liquid crystal panel 2 includes an image display region 3, a V driver (scanning line driving circuit) 4, an H driver (data signal output circuit) 5, an IF circuit 6, and an / F generation circuit 7 on the element substrate. . In addition, a row designation signal, a column designation signal, a data signal, an F signal, a power supply switching signal, a plurality of fixed potentials (for example, 0 V, 3 V, 6 V, 12 V) and the like are externally supplied to the liquid crystal panel 2 through the flat cable 8. Supplied.

  In the image display area 3, a plurality of pixel circuits P are formed in a matrix. The V driver 4 has a decoder circuit and a buffer circuit. The decoder circuit selects one scanning line from the plurality of scanning lines arranged in the row direction one by one based on the row designation signal, and sets the scanning signal supplied to the selected scanning line to the Hi level. The scanning signal supplied to the other scanning lines is set to the Low level. The buffer circuit level shifts the output from the decoder circuit. In the V driver 4, a VDD power supply wiring for supplying a logic drive potential VDD to the decoder circuit and a VDH power supply wiring for supplying a matrix selection potential VDH to the buffer circuit are formed. .

  The H driver 5 includes a column selection unit (decoder circuit and buffer circuit) and a data signal output unit (sample hold circuit). The decoder circuit sequentially selects one or more selection lines from a plurality of selection lines arranged in the column direction together with the data signal based on the column designation signal, and selects the selection signal supplied to the selected selection line at the Hi level. In addition, the selection signals supplied to the other selection lines are set to the Low level. The buffer circuit level shifts the output from the decoder circuit. The sample hold circuit includes a plurality of transistors and supplies a data signal to the data line of the column selected by the column selection unit. Also in the H driver 5, a VDD power supply wiring for supplying a logic drive potential VDD to the decoder circuit and a VDH power supply wiring for supplying a matrix selection potential VDH to the buffer circuit are formed. .

  A row designation signal, a column designation signal, a data signal, a power supply switching signal, and fixed potentials 0 V, 3 V, 6 V, and 12 V are input to the IF circuit 6 via the flat cable 8. The IF circuit 6 has a level shift circuit. This level shift circuit shifts the row designation signal from 3V to 6V and supplies it to the V driver 4, and shifts the column designation signal from 3V to 6V to shift the H driver. 5 is supplied. The level shift circuit shifts the data signal from 3V to 6V and supplies it to the H driver 5, and shifts the power supply switching signal from 3V to 12V and supplies it to the switching circuit 10 (FIG. 3) described later.

  The IF circuit 6 supplies a ground potential VSS (0 V), a logic drive potential VDD (6 V or 3 V), and a matrix selection potential VDH (12 V or 3 V) to the V driver 4 and the H driver 5. The 6V logic drive potential VDD is a potential required to drive the decoder circuit of the V driver 4 and the decoder circuit of the H driver 5. The 12V matrix selection potential VDH is a potential required to turn on the TFTs 21 to 24 (FIG. 2) provided as switching elements in each pixel circuit P. The IF circuit 6 includes a switching circuit 10 (FIG. 3), and can switch between the logic driving potential VDD and the matrix selection potential VDH.

  The / F generation circuit 7 (inverter circuit) inverts the F signal supplied to the liquid crystal panel 2 via the flat cable 8 to generate the / F signal. The F signal and the / F signal are AC signals for driving the liquid crystal element 14 and are commonly supplied to all the pixel circuits P. The F signal is supplied to the counter substrate via the conductive members 9a and 9b and applied to the common electrode. The liquid crystal, which is an electro-optic material, is sandwiched between the element substrate and the counter substrate in the portion of the image display region 3, and a desired image is displayed in the image display region 3 by controlling the transmittance of the liquid crystal for each pixel circuit P. Is displayed.

FIG. 2 is a circuit diagram showing a configuration of the pixel circuit P.
The pixel circuit P includes a static memory circuit 12 such as an SRAM, a selection circuit 13, and a liquid crystal element 14. The memory circuit 12 includes four n-channel TFTs 21, 22, 23, and 24 that function as switching elements, and two NOT circuits 25 and 26, respectively. The TFT 21 has a source connected to the data line DATA from the H driver 5, a drain connected to the source of the TFT 22, and a gate connected to the scanning line VGATE from the V driver 4. The TFT 22 has a drain connected to the input terminal of the NOT circuit 25 and a gate connected to the selection line HGATE from the H driver 5.

  The output terminal of the NOT circuit 25 is connected to the input terminal of the NOT circuit 26, and the output terminal of the NOT circuit 26 is fed back to the input terminal of the NOT circuit 25. Here, the input terminal of the NOT circuit 25 (the output terminal of the NOT circuit 26) is the terminal Q of the normal rotation terminal of the memory circuit 12, and the input terminal of the NOT circuit 26 (the output terminal of the NOT circuit 25) is the inversion of the memory circuit 12. Terminal terminal / Q.

  Since the memory circuit 12 is a complementary type, the TFT 24 has its source connected to the complementary data line / DATA from the H driver 5, its drain connected to the source of the TFT 23, and its gate scanned from the V driver 4. Connected to line VGATE. The drain of the TFT 23 is connected to the input terminal of the NOT circuit 26, and the gate thereof is connected to the selection line HGATE from the H driver 5.

  In the memory circuit 12, when the scanning signal supplied to the scanning line VGATE and the selection signal supplied to the selection line HGATE are both at the Hi level, all of the TFTs 21 to 24 are simultaneously turned on and supplied to the data line DATA. The terminal / Q is configured to hold a signal obtained by inverting the data signal supplied to the data line DATA.

  The selection circuit 13 has two transfer gates 27 and 28. The / F signal is supplied to the input terminal of the transfer gate 27, and the F signal is supplied to the input terminal of the transfer gate 28. The output terminals of the transfer gates 27 and 28 are commonly connected to the pixel electrode 29. The forward control gate of the transfer gate 27 and the inversion control gate of the transfer gate 28 are connected to the terminal Q of the memory circuit 12, and the inversion control gate of the transfer gate 27 and the forward control gate of the transfer gate 28 are connected to the memory circuit. 12 terminals / Q.

  The F signal and the / F signal are AC signals that turn on or off the liquid crystal element 14. The liquid crystal element 14 includes an individual pixel electrode 29 for each pixel, a common electrode 30 common to all pixels, and a liquid crystal between both electrodes. Further, an F signal is applied to the common electrode 30.

  When the forward rotation control gate is at the Hi level (the inversion control gate is at the Low level), the transfer gates 27 and 28 are turned on (conductive state) between the input end and the output end. Therefore, when the terminal Q of the memory circuit 12 is at the Hi level, the transfer gates 27 and 28 are turned on and off, respectively, and the / F signal is applied to the pixel electrode 29. As a result, in the normally white mode, the pixel is in a dark ON state. On the other hand, when the terminal Q of the memory circuit 12 is at the low level, the transfer gates 27 and 28 are turned off and on, respectively, and the F signal is applied to the pixel electrode 29. As a result, in the normally white mode, the pixel is in a bright off state.

  For example, when writing a data signal to the pixel circuit P (j, k) located in the j-th row and the k-th column, a control circuit (not shown) provided outside the liquid crystal panel 2 in the electro-optical device 1. Supplies to the liquid crystal panel 2 via the flat cable 8 a row designating signal designating the jth row, a column designating signal designating the kth column, and a data signal to be written to the pixel circuit P (j, k). . The V driver 4 sets the scanning signal supplied to the j-th scanning line VGATE to Hi level based on the row designation signal, and the H driver 5 is supplied to the k-th selection line HGATE based on the column designation signal. Set the selection signal to Hi level. At the same time, the H driver 5 (sample hold circuit) supplies a data signal to the k-th column data line DATA and supplies an inverted signal of the data signal to the k-th column complementary data line / DATA. As a result, in the pixel circuit P (j, k), the TFTs 21 to 24 are simultaneously turned on, the data signal supplied to the data line DATA is held at the terminal Q, and the inverted signal is held at the terminal / Q.

  In this state, when one or both of the scanning line VGATE and the selection line HGATE are at the low level, in the pixel circuit P (j, k), the TFTs 21 and 24 or the TFTs 22 and 23 are turned off, or all the TFTs 21 to 24 are turned off. Become. As a result, in the memory circuit 12, the terminal Q is electrically disconnected from the data line DATA and the terminal / Q is electrically disconnected from the complementary data line / DATA, but the memory circuit 12 continues to hold the written data signal.

  Note that during the period in which the data signal is written to the pixel circuit P (j, k), in the other pixel circuits P, the scanning signal supplied to the scanning line VGATE or the selection signal supplied to the selection line HGATE. Is at the low level, one or both of the TFTs 21 and 22 and the TFTs 23 and 24 are off. Therefore, in the pixel circuits P other than the pixel circuit P (j, k), the terminals Q and / Q of the memory circuit 12 are electrically disconnected from the data lines DATA and / DATA, respectively. Therefore, the pixel circuit P to which no data signal is written is not affected by the voltage change of the data line DATA and the complementary data line / DATA.

  Thus, if the data signal has already been written, the memory circuit 12 continues to hold the data signal regardless of the voltage states of the data line DATA and the complementary data line / DATA. In addition, once a data signal is written in the memory circuit 12, the state is kept thereafter (holding state), and there is no need to perform refresh.

FIG. 3 is a circuit diagram showing a configuration of the switching circuit 10.
The switching circuit 10 is provided in the IF circuit 6 and includes four transfer gates 31, 32, 33, and 34 and one NOT circuit 35. A fixed potential of 12V is supplied to the input terminal of the transfer gate 31, and a fixed potential of 3V is supplied to the input terminal of the transfer gate 32. A fixed potential of 6V is supplied to the input terminal of the transfer gate 33, and a fixed potential of 3V is supplied to the input terminal of the transfer gate 34. The output terminals of the transfer gates 31 and 32 are commonly connected to the VDH power supply wiring. The VDH power supply wiring is a power supply line for supplying the matrix selection potential VDH to the buffer circuit of the V driver 4 and the buffer circuit of the H driver 5. The output terminals of the transfer gates 33 and 34 are commonly connected to the VDD power supply wiring. This VDD power supply wiring is a power supply line for supplying the logic drive potential VDD to the decoder circuit of the V driver 4 and the decoder circuit of the H driver 5.

  The forward switching control gates of the transfer gates 31 and 33 and the inversion control gates of the transfer gates 32 and 34 are supplied with a power supply switching signal level-shifted to 12V by the IF circuit 6. Further, an inversion signal of the power supply switching signal is supplied to the inversion control gates of the transfer gates 31 and 33 and the normal control gates of the transfer gates 32 and 34.

  The transfer gates 31 to 34 are turned on between the input end and the output end when the normal rotation control gate is at the Hi level (the inversion control gate is at the Low level). Therefore, when the power supply switching signal supplied to the switching circuit 10 is at the Hi level, the transfer gates 31 and 32 are turned on and off, respectively, and a fixed potential of 12 V is supplied to the VDH power supply wiring, so that the transfer gates 33 and 34 are supplied. Are turned on and off, respectively, and a fixed potential of 6 V is supplied to the VDD power supply wiring. On the other hand, when the power supply switching signal supplied to the switching circuit 10 is at a low level, the transfer gates 31 and 32 are turned off and on, respectively, a fixed potential of 3V is supplied to the VDH power supply wiring, and the transfer gates 33 and 34 are supplied. Are turned off and on, respectively, and a fixed potential of 3 V is also supplied to the VDD power supply wiring. As described above, the switching circuit 10 switches between the matrix selection potential VDH supplied to the VDH power supply wiring and the logic drive potential VDD supplied to the VDD power supply wiring based on the power supply switching signal.

In the present embodiment, a power supply switching signal is generated by a control circuit provided outside the liquid crystal panel 2. Since the display data to be displayed in the image display area 3 is supplied to the control circuit, the control circuit analyzes the display data and switches the signal level of the power switching signal from Low to Hi, or conversely from Hi to Low. Switch to. For example, the control circuit determines whether the image displayed in the image display area 3 is a moving image or a still image, and sets the power switch signal to Hi level during the moving image display period in which the moving image is displayed. The control circuit sets the power switch signal to the low level when the still image display period for displaying the still image is started, and returns the power switch signal to the hi level before the end of the still image display period. Here, since the display data displayed in the image display area 3 is supplied to the control circuit at a stage much before the actual display timing, the control circuit sets the timing at which the still image display period ends in advance. Can be specified.
Even when the image displayed in the image display area 3 is a still image, the control circuit sets the power switch signal to the Hi level in a still image rewriting period in which, for example, a still image is rewritten to another still image. To do. In addition, even when the image displayed in the image display area 3 is a still image, the control circuit sets the power switch signal to the Hi level when rewriting an image in a partial area. For example, when a still image is displayed as a background image, such as a standby screen of a mobile phone, but the image of the time display area that displays the current time or the radio wave intensity display area that displays the radio field intensity is rewritten. The power supply switching signal is set to Hi level.

FIG. 4 is a timing chart for explaining the operation of the electro-optical device 1.
In the figure, the display data writing period is a period during which a data signal needs to be written to at least one pixel circuit P among all the pixel circuits P provided in the image display area 3. That is, it is a period in which display is performed based on the written data signal while writing the data signal to at least one pixel circuit P every vertical scanning period. This display data writing period corresponds to, for example, a moving image display period in which a moving image is displayed in the image display area 3. The display data holding period is a period during which display is performed based on the data signal held in the memory circuit 12 by stopping writing data signals to all the pixel circuits P provided in the image display area 3. is there. This display data holding period corresponds to, for example, a still image display period in which a still image is displayed in the image display area 3.
VCC is a logic drive potential (3V) supplied to a part of the IF circuit 6 and the / F generation circuit 7, and VSS is a ground potential (0V).

  First, in the display data writing period shown in FIG. 4, a data signal must be written to at least one pixel circuit P every vertical scanning period. That is, since it is necessary to drive the V driver 4 and the H driver 5, the control circuit sets the power supply switching signal to the Hi level. Therefore, the switching circuit 10 supplies the 12V matrix selection potential VDH to the VDH power supply wiring and the 6V logic drive potential VDD to the VDD power supply wiring. That is, a power supply potential of 12 V is supplied to the buffer circuit of the V driver 4 and the buffer circuit of the H driver 5, and a power supply potential of 6 V is supplied to the decoder circuit of the V driver 4 and the decoder circuit of the H driver 5. Therefore, the V driver 4 and the H driver 5 can operate, and perform a data signal writing process on the pixel circuit P in the display data writing period.

  Next, no data signal is written to the pixel circuit P in the display data holding period. That is, it is not necessary to drive the V driver 4 and the H driver 5. Therefore, when the timing T1 shown in the figure, that is, when the display data writing period ends and the display data holding period starts, the control circuit switches the power supply switching signal from the Hi level to the Low level. Therefore, the switching circuit 10 switches the matrix selection potential VDH supplied to the VDH power supply wiring from 12V to 3V, and switches the logic drive potential VDD supplied to the VDD power supply wiring from 6V to 3V. As a result, a constant potential of 3 V is supplied to both the decoder circuit and buffer circuit provided in the V driver 4 and the decoder circuit and buffer circuit provided in the H driver 5.

  In the display data holding period, no data signal is written to the pixel circuit P. However, in each pixel circuit P, the liquid crystal element 14 is driven based on the data signal held in the memory circuit 12. . For this reason, a still image is displayed in the image display area 3. Further, as described above, it is not necessary to drive the V driver 4 and the H driver 5 in the display data holding period, but in order to prevent the VDH power supply wiring and the VDD power supply wiring from being in a floating state (undefined state), A constant potential of 3 V is supplied to the VDH power supply wiring and the VDD power supply wiring.

  Further, when the timing T3 at which the display data holding period ends is specified, the control circuit switches the power supply switching signal from the Low level to the Hi level at a timing T2 that is a predetermined time Δt before the specified timing T3. Note that the timing T3 shown in FIG. 4 is also the timing at which the next display data writing period starts. When the power supply switching signal is switched from the Low level to the Hi level in this way, the switching circuit 10 switches the matrix selection potential VDH supplied to the VDH power supply wiring from 3V to 12V, and the logic drive potential VDD supplied to the VDD power supply wiring. Switch from 3V to 6V. As a result, a power supply potential of 12 V is supplied to the buffer circuit of the V driver 4 and the buffer circuit of the H driver 5, and a power supply potential of 6 V is supplied to the decoder circuit of the V driver 4 and the decoder circuit of the H driver 5. Therefore, the V driver 4 and the H driver 5 become operable, and when the timing T3 comes, the data signal writing process is started again.

FIG. 5 is a diagram for explaining the power supply potential supplied to each part of the liquid crystal panel 2.
As shown in FIG. 5A, in the display data writing period, the matrix selection potential VDH of 12V is supplied to the buffer circuit of the V driver 4, the buffer circuit of the H driver 5, and the level shift circuit of the IF circuit 6. Is supplied. Further, the logic drive potential VDD of 6V is supplied to the decoder circuit of the V driver 4 and the decoder circuit of the H driver 5. Further, a part of the IF circuit 6 and the / F generation circuit 7 are supplied with a 3V logic drive potential VCC. On the other hand, as shown in FIG. 5B, in the period from the timing T1 to the timing T2 in the display data holding period, all the drive circuits except for a part of the IF circuit 6 (the switching circuit 10) are used. On the other hand, a constant potential of 3 V is supplied. Depending on the circuit configuration, the IF circuit 6, the / F generation circuit 7, and the like may be included in the drive circuit that is the target of switching the power supply potential.

  As described above, according to the present embodiment, the VDH power supply wiring and the VDD power supply wiring are supplied to the VDH power supply wiring and the VDD power supply wiring during the display data writing period in the period from the timing T1 to the timing T2 in the display data holding period. A constant potential (3V) lower than the potential (12V, 6V) is supplied. For this reason, even when a still image is displayed, the VDH power supply wiring and the VDD power supply wiring do not enter a floating state. Therefore, malfunction display due to noise can be prevented. In addition, the constant potential (both 3 V) supplied to the VDH power supply wiring and the VDD power supply wiring in the period from timing T1 to timing T2 is lower than the constant potential (12 V, 6 V) supplied during the display data writing period. Therefore, the power consumption of the V driver 4, the H driver 5, and the IF circuit 6 can be reduced as compared with the case where the power supply potential is not switched.

<2. Second Embodiment>
This embodiment is different from the first embodiment in that a power supply switching signal is generated in the liquid crystal panel 2. The same code | symbol is used about the element which is common in 1st Embodiment.
FIG. 6 is a circuit diagram showing a configuration of the power supply switching signal generation circuit 11. FIG. 7 is a timing chart for explaining the operation of the power supply switching signal generation circuit 11.
The power supply switching signal generation circuit 11 is provided in the IF circuit 6 and includes a D-type flip-flop 41 and four NOT circuits 42, 43, 44, and 45 as shown in FIG. The output terminal of the NOT circuit 42 is connected to the D input terminal of the D-type flip-flop 41, and the output terminal of the NOT circuit 43 is connected to the C (CLOCK) terminal of the D-type flip-flop 41. The Q output terminal of the D flip-flop 41 is connected to the input terminal of the NOT circuit 44, and the output terminal of the NOT circuit 44 is connected to the input terminal of the NOT circuit 45. The / CE signal is supplied to the input terminal of the NOT circuit 42, and the / WE signal is supplied to the input terminal of the NOT circuit 43.

  Further, as shown in FIG. 7, the / WE signal is a signal that can specify the start timing S for each vertical scanning period (1 V). In other words, the / WE signal is a signal indicating the timing of every predetermined period at which data signal writing can be started for all the pixel circuits P provided in the image display area 3. The / CE signal is a signal indicating whether or not to write a data signal to at least one pixel circuit P in each vertical scanning period. This / CE signal indicates that data signals are written to one or more pixel circuits P within the next one vertical scanning period when the signal level is Low during the period when the / WE signal is Low level. When the signal level is Hi during the period when the / WE signal is at Low level, it indicates that no data signal is written within the next one vertical scanning period. The / WE signal and the / CE signal are supplied from the outside of the liquid crystal panel 2 via the flat cable 8.

  As shown in FIG. 7, the power switching signal generation circuit 11 switches the power switching signal from the Low level to the Hi level at the timing Ta when both the / WE signal and the / CE signal are at the Low level. The power supply switching signal generation circuit 11 switches the power supply switching signal from the Hi level to the Low level at the timing Tb when the / WE signal is at the Low level and the / CE signal is at the Hi level. Thus, the power supply switching signal generation circuit 11 generates a power supply switching signal based on the / WE signal and the / CE signal. Further, by providing the power switch signal generation circuit 11 as described above, the power switch signal can be easily generated in the liquid crystal panel 2.

<3. Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 1 is applied will be described.
FIG. 8 shows the configuration of a mobile personal computer to which the electro-optical device 1 is applied. The personal computer 2000 includes the electro-optical device 1 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.
FIG. 9 shows a configuration of a mobile phone to which the electro-optical device 1 is applied. The cellular phone 3000 includes an electro-optical device 1 as a display unit, a plurality of operation buttons 3001, and a scroll button 3002. By operating the scroll button 3002, the image displayed on the electro-optical device 1 is scrolled.
FIG. 10 shows a configuration of a portable information terminal (PDA: Personal Digital Assistants) to which the electro-optical device 1 is applied. The information portable terminal 4000 includes the electro-optical device 1 as a display unit, a plurality of operation buttons 4001, and a power switch 4002. By operating the operation button 4001, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.
Electronic devices to which the electro-optical device 1 is applied include televisions, digital still cameras, video cameras, car navigation devices, electronic notebooks, calculators, video phones, POS terminals, printers, in addition to those shown in FIGS. , Scanners, copiers, video players, electronic paper, digital signage (electronic signage / electronic posters), and the like.

<4. Modification>
In the period from the timing T1 to the timing T2 in the display data holding period, the fixed potential supplied to the VDH power supply wiring and the VDD power supply wiring is arbitrarily fixed as long as it is lower than the constant potential supplied during the display data writing period. Potential can be used. The fixed potential may be supplied from the outside of the liquid crystal panel 2 or may be generated in the liquid crystal panel 2. Further, the constant potentials supplied to the VDH power supply wiring and the VDD power supply wiring in the period from the timing T1 to the timing T2 may be different from each other. Further, the power supply potential switching target may be either the VDH power supply wiring or the VDD power supply wiring, or may be either the V driver 4 or the H driver 5.

  The switching circuit 10 can be provided not only in the IF circuit 6 but also in any place on the liquid crystal panel 2. The switching circuit 10 may be configured to be provided outside the liquid crystal panel 2 (for example, in the control circuit). In this case, outputs (matrix selection potential VDH and logic drive potential VDD) from the switching circuit 10 are supplied to the liquid crystal panel 2 via the flat cable 8. The power switch signal generation circuit 11 is not limited to the IF circuit 6 but can be provided at any location on the liquid crystal panel 2 and is provided outside the liquid crystal panel 2 (for example, in the control circuit). May be. In addition, the number of scanning lines, data lines, complementary data lines, and selection lines may be one or more. There may be one or more pixel circuits. The present invention can also be applied to an electro-optical device that does not include a selection line and performs line-sequential driving.

  The present invention can be applied not only to an active matrix liquid crystal display device but also to a passive matrix liquid crystal display device and a liquid crystal display device including a TFD (thin film diode) as a switching element. Further, the present invention can be applied to a transmissive or transflective liquid crystal display device. The present invention is not limited to a liquid crystal display device that displays an image using a liquid crystal element. For example, an inorganic EL element, an organic EL element, a field electron emission element, a surface conduction electron emission element, a ballistic electron emission element, and an LED The present invention is also applicable to an electro-optical device that displays an image using an electro-optical element such as an element, an electrophoretic element, or an electrochromic element.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 2 ... Liquid crystal panel, 3 ... Image display area, 4 ... V driver, 5 ... H driver, 6 ... IF circuit, 7 ... / F generation circuit, 8 ... Flat cable, 9a, 9b ... Conductive member , P ... pixel circuit, F ... F signal, /F.../F signal, 10 ... switching circuit, 11 ... power supply switching signal generation circuit, 12 ... memory circuit, 13 ... selection circuit, 14 ... liquid crystal element, 21-24 ... TFT, 25, 26 ... NOT circuit, 27, 28 ... transfer gate, 29 ... pixel electrode, 30 ... common electrode, VGATE ... scanning line, HGATE ... selection line, DATA ... data line, / DATA ... complementary data line, 31- 34 ... Transfer gate, 35 ... NOT circuit, VDH ... Matrix selection potential, VDD ... Logic drive potential, VCC ... Logic drive potential, VSS ... Ground potential, 41 ... D-type flip Flop, 42~45 ... NOT circuit, / WE ... / WE signal, / CE ... / CE signal, 2000 ... personal computer, 3000 ... mobile phone, 4000 ... portable information terminal.

Claims (8)

A pixel circuit provided corresponding to the intersection of the scanning line and the data line;
A drive circuit for driving the pixel circuit;
A power supply line for supplying a power supply potential to the drive circuit;
A switching circuit that switches a power supply potential supplied to the power supply line,
The pixel circuit includes:
A pixel electrode;
A memory circuit for holding a data signal supplied to the data line;
A selection circuit that selects one of two alternating signals having opposite logic levels as an alternating signal supplied to the pixel electrode based on a data signal held in the memory circuit;
The switching circuit is
When a display data holding period in which writing based on the data signal held in the memory circuit is stopped and writing of the data signal to the pixel circuit is started, the power supply potential supplied to the power supply line is supplied to the pixel circuit. In the display data writing period in which the data signal is written to the display data based on the written data signal, a second constant potential lower than the first constant potential supplied to the power supply line is set, and the display data holding period is The electro-optical device, wherein the power supply potential supplied to the power supply line is changed from the second constant potential to the first constant potential before the end. The drive circuit is
A decoder circuit for turning on a scanning signal supplied to the scanning line;
A scanning line driving circuit comprising: a buffer circuit for level shifting the output of the decoder circuit;
The electro-optical device according to claim 1, wherein the power supply line is a power supply line that supplies a power supply potential to the decoder circuit or a power supply line that supplies a power supply potential to the buffer circuit. A selection line corresponding to the data line;
The drive circuit is
A decoder circuit for turning on a selection signal supplied to the selection line;
A buffer circuit for level shifting the output of the decoder circuit;
A data signal output circuit comprising: a sample hold circuit that supplies a data signal to the data line when the selection signal is on;
The electro-optical device according to claim 1, wherein the power supply line is a power supply line that supplies a power supply potential to the decoder circuit or a power supply line that supplies a power supply potential to the buffer circuit. 4. The electro-optical device according to claim 1, wherein the pixel circuit, the driving circuit, the power supply line, and the switching circuit are provided in an electro-optical panel. 5. A first control signal indicating a timing for every predetermined period at which writing of a data signal to the pixel circuit can be started, and a second control signal indicating whether or not to write a data signal at each timing Further comprising a generation circuit for generating a switching signal defining the timing for switching the power supply potential,
The electro-optical device according to claim 1, wherein the switching circuit switches a power supply potential supplied to the power supply line based on the switching signal generated by the generation circuit. The electro-optical device according to claim 5, wherein the generation circuit is provided in an electro-optical panel.   An electronic apparatus comprising the electro-optical device according to claim 1. A pixel electrode, a memory circuit that holds a data signal supplied to the data line, and a logic circuit based on the data signal held in the memory circuit are provided corresponding to the intersections of the scanning line and the data line. A pixel circuit including a selection circuit that selects one of two alternating signals of opposite levels as an alternating signal supplied to the pixel electrode, a driving circuit that drives the pixel circuit, and a power source for the driving circuit A control method of an electro-optical device including a power supply line for supplying a potential,
When a display data holding period in which writing based on the data signal held in the memory circuit is stopped and writing of the data signal to the pixel circuit is started, the power supply potential supplied to the power supply line is supplied to the pixel circuit. In the display data writing period in which the data signal is written to the display data based on the written data signal, a second constant potential lower than the first constant potential supplied to the power supply line is set, and the display data holding period is A control method for an electro-optical device, wherein the power supply potential supplied to the power supply line is changed from the second constant potential to the first constant potential before finishing.

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