JP2011027467A - Semiconductor test apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect whether a fail occurs in all DUTs when the DUTs have a plurality of pins, while setting the connection relationship between a semiconductor test apparatus and DUTs freely. <P>SOLUTION: The semiconductor test apparatus having a PE unit 3 for generating the pass/fail information on a plurality of DUTs 2 on the basis of output signals output from the DUTs 2 includes: a conversion unit 11 for grouping pass/fail information by DUT and outputting it on the basis of an association table storing the association relationship between a plurality of DUT pins of the PE unit 3 and DUT 2 connected to the DUTs 2; a plurality of logical OR operation units 12 for inputting the pass/fail information grouped by DUT 2 and performing logical OR operations to output DUT information; and a logical AND operation unit 14 for performing logical AND operations on all pieces of DUT information output from the plurality of logical OR operation units 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for testing a device under test.

  2. Description of the Related Art Conventionally, a semiconductor test apparatus for testing a device under test (DUT) has been known. As shown in FIG. 6, the conventional semiconductor test apparatus 101 is connected to a plurality of (N: N is an integer of 2 or more) DUTs 102. The DUT 102 is a device under test such as an IC, LSI, or memory. A predetermined test signal is output from the semiconductor test apparatus 101 to the DUT 102, and the semiconductor test apparatus 101 compares the output signal output from the DUT 102 with an expected value, and passes the pass fail information as a result of the pass fail determination (pass / fail determination) obtain.

  6A and 6B, the semiconductor test apparatus 101 side is provided with N pins (tester pins P (1) to P (N): collectively referred to as tester pins P). Yes. The DUT 101 is also provided with a pin (referred to as a DUT pin). In the figure (a), one DUT 101 is provided with one DUT pin, and in the same figure (b), one DUT 101 is provided with two DUT pins. Shows the case. In any case, one tester pin P is connected to one DUT pin of the DUT 101.

  The connection relationship between the tester pin P and the DUT 102 is basically fixed. In other words, which DUT 102 is connected to the tester pin P is defined in advance, and the connection relationship cannot be freely changed. On the other hand, the tester pin P and the DUT 102 each have a physical positional relationship, and the physical positional relationship between the two may not be favorable under the restriction of a predetermined connection relationship. In particular, in recent years, the tester pins P have a tendency to increase the number of pins, so that the physical connection relationship is often extremely complicated. As a result, the connection line must be detoured and the waveform quality deteriorates.

  Therefore, Patent Document 1 discloses a technique for converting a physical connection relationship between a DUT pin and a tester pin P into a logical connection relationship. In this technology, the correspondence between logical pin information for specifying a physical pin (tester pin) and a physical pin is arbitrarily converted according to the connection relationship between the DUT pin and the physical pin. For this conversion, a table format conversion rule is used, which makes it possible to identify the physical pin even if the DUT pin and the physical pin are freely connected.

JP 2009-42085 A

  Meanwhile, in the semiconductor test apparatus 101 shown in FIG. 6, the pass / fail judgment process based on the output signal output from the DUT 102 is performed in parallel with the input of the test signal to the DUT 102. A plurality of DUTs 102 are connected to the semiconductor test apparatus 101 such as N or N / 2. At this time, if the result of the pass / fail judgment of all the DUTs 102 is a failure, even if the test signal is being input, the process is forcibly terminated at that time.

  The result that all the DUTs 102 fail is, for example, when there is a contact failure between the semiconductor test apparatus 101 and each DUT 102 or when there is an error in setting test conditions. The test shall not be continued under conditions that cause damage. Therefore, in this case, after the failure is immediately recovered, the test of the DUT 102 is restarted.

  For this reason, it is detected whether or not a failure (hereinafter referred to as an all DUT failure) has occurred in the results of all the DUTs 102, and when all the DUT failures are detected, the recovery process is immediately performed. In order to detect all DUT failures, attention must be paid to the pass fail information for all DUTs 102.

  In this case, if the connection relationship between the DUT 102 and the tester pin P is fixed, it becomes clear which DUT 102 the pass fail information belongs to. That is, since the tester pin P is uniquely assigned to the DUT 102, the DUT 102 is always specified by the tester pin P. Thereby, if attention is paid only to the pass fail information corresponding to the tester pin P, all DUT failures can be easily detected. However, if the connection relationship is fixed, there arises a problem such as the deterioration of the waveform quality described above.

  On the other hand, when the connection relationship between the DUT 102 and the tester pin P is freely set, it becomes unclear which DUT 102 the pass fail information corresponding to each tester pin P belongs to. In this case, it is possible to specify the connection relationship between the DUT 102 and the tester pin P by using the conversion rule used in the above-described technique. However, this technique is intended for a semiconductor test apparatus in which one DUT is connected, and is not intended for a semiconductor test apparatus 101 in which a plurality of DUTs 102 are connected as shown in FIG.

  When one DUT 102 has a plurality of pins as shown in FIG. 6B, two tester pins P corresponding to the DUT 102 must be specified from among the plurality of tester pins P of the semiconductor test apparatus 101. Don't be. Since all DUT failures are detected not in units of tester pins P but in units of DUTs 102, all DUT failures cannot simply be detected from the correspondence between tester pins P and DUTs 102.

  Therefore, in the present invention, whether or not a failure occurs in all the devices under test when the device under test is provided with a plurality of pins while freely setting the connection relationship between the semiconductor test apparatus and the device under test. The purpose is to detect.

  In order to solve the above problems, a semiconductor test apparatus according to a first aspect of the present invention includes a test unit that generates pass fail information of the device under test based on output signals output from a plurality of devices under test. A semiconductor test apparatus, wherein the pass fail information is grouped for each device under test based on a correspondence table storing a correspondence relationship between a plurality of pins of the test unit connected to the device under test and the device under test. A plurality of logical sum operation units that perform logical sum operation by inputting path fail information grouped for each device under test and output as device information under test, A logical product operation unit that performs logical product operation on all device-under-test information output from the logical sum operation unit.

  According to this semiconductor test apparatus, the conversion unit groups the pass fail information for each device under test, and the logical sum operation unit generates the device under test information by calculating the logical sum of the pass fail information for each group. The logical product of all the device under test information is calculated. This makes it possible to detect whether or not a failure has occurred in all the devices under test while freely setting the connection relationship between the pins of the semiconductor test apparatus and the devices under test.

  In the present invention, path fail information is grouped for each device under test, logical OR operation is performed to generate device under test information, and logical product operation of all device under test information is performed. As a result, even if the connection relationship between the device under test and the pins of the semiconductor test equipment is arbitrarily changed, the pass fail information is grouped and ORed, so the pass fail information in units of the device under test (Device under test information) is obtained. This makes it possible to detect whether or not a failure has occurred in all the devices under test while freely setting the connection relationship between the devices under test and the pins of the semiconductor test apparatus.

It is a block diagram which shows schematic structure of a semiconductor test apparatus. It is a figure which shows an example of a correspondence table. It is a flowchart which shows the flow of a process of this invention. It is a block diagram which shows schematic structure of the semiconductor test apparatus of the modification 1. It is a block diagram which shows schematic structure of the semiconductor test apparatus of the modification 2. It is a block diagram which shows schematic structure of the conventional semiconductor test apparatus.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the relationship between the semiconductor test apparatus 1 and the DUT 2. The semiconductor test apparatus 1 is a test apparatus for testing the DUT 2, and the DUT 2 is a device under test such as an IC, LSI, or memory. As shown in FIG. 1, the semiconductor test apparatus 1 includes N (N is an integer of 2 or more) pins (tester pins P (1) to P (N)), and the semiconductor test apparatus 1 includes N pins. / 2 DUTs 2 (DUT (1) to DUT (N / 2)) are connected.

  The semiconductor test apparatus 1 includes a PE unit 3, an arithmetic circuit 4, a correspondence table storage unit 5, and a correspondence table setting unit 6. The PE unit 3 is a pin electronics card unit including one or a plurality of pin electronics cards, and includes the N tester pins P. The PE unit 3 inputs a test signal for performing a test on the DUT 2 and performs pass / fail determination (pass / fail determination) based on the output signal output from the DUT 2.

  As shown in FIG. 1, the DUT 2 includes two pins (DUT pins), and the DUT pins and the tester pins P are connected in a one-to-one relationship. The tester pin P has an upper limit on the number of DUTs 2 that can be connected to the semiconductor test apparatus 1, that is, the number of DUTs 2 that can be tested. For this reason, since there are N tester pins P, the number of DUTs 2 is N / 2.

  The PE unit 3 includes a driver and a comparator (not shown), and a test signal is output to the DUT 2 by the driver. The comparator has an expected value. By comparing the output signal output from the DUT 2 with the expected value and determining pass or fail, 1-bit pass fail information (pass = “0”, fail = "1"). Pass fail information is generated for each of the N tester pins P of the PE unit 3, and each pass fail information is output to the arithmetic circuit 4 without changing the order.

  The arithmetic circuit 4 is a circuit for detecting whether or not all the DUTs 2 have failed (all DUT fail), that is, becomes an all DUT fail detection unit. As shown in FIG. 1, the arithmetic circuit 4 includes a conversion unit 11, an OR operation unit 12, N / 2 DUT information output units 13, an AND operation unit 14, and a determination unit 15.

  The conversion unit 11 divides each piece of pass-fail information output from the PE unit 3 for each DUT 2 and outputs the grouped information. The conversion unit 11 is a programmable logic circuit such as an FPGA (Field Programmable Gate Array), and arbitrarily converts input and output based on a correspondence table. A correspondence table storage unit 5 is connected to the conversion unit 11, and a correspondence table setting unit 6 is connected to the correspondence table storage unit 5. The correspondence table is as shown in FIG. 2, in which the DUT number indicates the number of DUT2, and the tester pin number indicates the number of tester pin P.

  As shown in the correspondence table, DUT number 1 corresponds to tester pin numbers 1 and 3, and DUT number 2 corresponds to tester pin numbers 2 and 4. The N tester pins P of the PE unit 3 are fixed, but any DUT 2 can be freely connected to each tester pin P. The user can optimize the physical positional relationship between the DUT 2 and the semiconductor test apparatus 1 by arbitrarily setting the connection relationship. Therefore, the user needs to set the connection relationship, and this setting is performed by the correspondence table setting unit 6.

  The correspondence table set by the correspondence table setting unit 6 is stored in the correspondence table storage unit 5 and output to the conversion unit 11. The conversion unit 11 converts the path between the input and output of the path fail information based on the correspondence table. For example, DUT number 1 and tester pin numbers 1 and 3 are stored in the correspondence table, and pass-fail information input from tester pin numbers 1 and 3 is output as one group.

  As shown in FIG. 1, the path fail information output from the PE unit 3 is in a state where those output from the same DUT 2 are not grouped. For this reason, the conversion unit 11 performs grouping by outputting adjacent path fail information corresponding to the same DUT 2. Thereby, the pass fail information corresponding to the same DUT 2 is adjacent to each other, and one group can be formed. Note that the pass-fail information may adopt any output relationship as long as it forms one group without being adjacent to each other.

  The logical sum operation unit 12 includes a plurality of logical sum circuits 21 (21 (1) to 21 (N / 2)). The OR circuit 21 inputs the pass / fail information of each group grouped by the conversion unit 11. In the example of FIG. 1, each group is composed of two pieces of pass-fail information, which matches the number of DUT pins of one DUT 2. Therefore, the OR circuit 21 has two input terminals.

  For example, since the logical sum circuit 21 (1) performs a logical sum operation on the pass fail information of the group corresponding to the DUT 2 (1), the pass fail information P (1) grouped into one group by the conversion unit 11 is performed. And P (3) two pieces of pass / fail information are input. Similarly, the OR circuit 21 (2) inputs two pieces of pass / fail information, ie, pass / fail information P (2) and P (4). The pass fail information P is pass fail information corresponding to the tester pin P.

  The logical sum circuit 21 performs a logical sum operation on the two pieces of pass-fail information. That is, the logical sum of the pass fail information of two DUT pins corresponding to one DUT 2 is taken. The fact that one of these two pieces of pass / fail information is “fail” indicates that the corresponding DUT itself has failed. Therefore, it is possible to detect whether or not a failure has occurred in the DUT 2 itself by taking the logical sum of two pieces of pass fail information corresponding to the same DUT 2.

  In the example of FIG. 1, since the DUT 2 includes two DUT pins, the number of OR circuits 21 is N / 2. Of course, the number of DUT pins of DUT 2 can be arbitrarily set, and if the number of DUT pins of one DUT 2 is M (M is an integer of 2 or more), the number of OR circuits 21 is N / M (described below). The same applies to the DUT information to be performed.

  The operation result of each OR circuit 21 is output to the DUT information output unit 13. The DUT information output unit 13 outputs DUT information. Here, the DUT information is information (device under test information) indicating whether or not a failure has occurred in the corresponding DUT, that is, information on the operation result of the OR circuit 21. The pass fail information becomes a 1-bit signal, and the signal obtained by performing the logical sum operation of the two pass fail information becomes the DUT information. Therefore, the DUT information also becomes a 1-bit signal.

  FIG. 1 shows the numbers of N / 2 DUT information output units 13. The DUT information output from each DUT information output unit 13 is input to the logical product operation unit 14. Although the DUT information output unit 13 is provided in FIG. 1, the DUT information may be input directly from the logical sum operation unit 12 to the logical product operation unit 14.

  The logical product operation unit 14 performs the logical product operation of each DUT information, thereby generating all DUT fail information (information indicating whether or not all DUTs have failed). The DUT information is a 1-bit signal, and all DUT fail information can be detected by taking the logical product of all the DUT information. That is, the DUT information is information of pass “0” or fail “1” with respect to one DUT, and logical operation is performed only when all the DUT information is “1” by performing a logical product operation of all the DUT information. The result of product operation is “1”, otherwise it is “0”. This is all DUT fail information.

  All DUT fail information generated by the AND operation unit 14 is output to the determination unit 15. Based on all DUT fail information, the determination unit 15 detects that all DUT failures have occurred if “1”, and that no all DUT failures have occurred if “0”.

  Next, the operation in the above configuration will be described using the flowchart of FIG. First, the correspondence table is transferred to the conversion unit 11 (step S1). The user sets a correspondence table in the correspondence table setting unit 6 based on the relationship between the tester pin P and the DUT 2 in advance. The correspondence table set in the correspondence table setting unit 6 is stored in the correspondence table storage unit 5. When the operation of the semiconductor test apparatus 1 is started, the correspondence table first stored in the correspondence table storage unit 5 is transferred to the conversion unit 11. Is done.

  Next, test conditions based on the test contents according to various purposes such as the type and number of DUTs 2 to be tested by the semiconductor test apparatus 1 are set (step S2). After the setting of the test conditions is completed, preparation for starting the test of the DUT 2 is completed. Then, the DUT 2 test is executed (step S3).

  The test of the DUT 2 is performed by inputting a test signal from the PE unit 3 to the DUT 2 based on a test pattern set by a computer or the like (not shown). Each DUT 2 outputs an output signal based on the test signal, and this output signal is input to each tester pin P of the PE unit 3. The PE unit 3 compares the expected value with the output signal input from the tester pin P, and generates pass / failure information.

  The N pieces of pass-fail information generated by the PE unit 3 are output to the conversion unit 11 according to the arrangement of the tester pins P. Since the connection relationship between the DUT 2 and the tester pins P is freely changed, the path fail information output from the PE unit 3 to the conversion unit 11 is irregularly arranged. Therefore, the conversion unit 11 performs path conversion so that the path fail information is grouped for each group based on the correspondence table stored in the correspondence table storage unit 5 (step S4).

  As shown in FIG. 2, in the correspondence table, the correspondence relationship in which the tester pin numbers 1 and 3 are DUT number 1 is clearly shown, and the conversion unit 11 changes the logic circuit based on this correspondence table. This makes it possible to group irregularly arranged pass-fail information for each DUT 2.

  The conversion unit 11 groups and outputs the pass fail information for each DUT 2. The logical sum operation unit 12 receives the pass fail information of each group and performs a logical sum operation to generate DUT information (step S5). The logical sum circuit 21 of the logical sum operation unit 12 outputs “1” as DUT information when one of the two pieces of input pass-fail information is “1”. As a result, DUT information indicating whether or not a failure has occurred in units of DUT2 is generated.

  The operation result of the logical sum operation unit 12 is output to the logical product operation unit 14 by the DUT information output unit 13, and the logical product operation unit 14 performs a logical product operation on all the DUT information (step S6). As a result, all DUT fail information indicating whether or not all DUTs 2 have failed is obtained. Then, the determination unit 15 determines whether all the DUTs 2 have failed by referring to all the DUT fail information (step S7).

  If the determination unit 15 determines that all DUTs 2 have not failed (that is, if all DUT fail information is “0”), the processing is continued. In this case, it is determined whether or not the current test pattern has been completed (step S8). If not completed, the process returns to step S3 to continue the test using the current test pattern.

  On the other hand, if it is determined in step S7 that all DUTs 2 have failed (that is, if all DUT fail information is “1”), the test processing is interrupted and error processing is performed (step S9). When all the DUTs fail, there may be a case where a failure occurs in the connection relationship between the semiconductor test apparatus 1 and the DUT 2 or a case where an error occurs in the setting of test conditions. In other words, a failure occurs. Therefore, all the test processes are temporarily interrupted to recover the fault that has occurred. A series of processes for recovering from a failure from the interruption of the test process becomes an error process. By performing error handling, the test can be resumed.

  When the test pattern is completed in step S8 and when the error process of step S9 is performed, it is determined whether or not all tests are completed (step S10). When one test pattern is completed, if there is a next test pattern, the process of step S2 starting from the process of setting the test conditions is performed again to perform the test with the test pattern. If there is no test pattern, the test is terminated. On the other hand, when error processing is performed, either the test condition setting processing in step S2 or the test end is performed depending on whether or not there is a next test pattern.

  As described above, even if the connection relationship between the plurality of tester pins P and the plurality of DUTs 2 in the semiconductor test apparatus 1 is freely set due to physical restrictions, the conversion unit 11 groups them for each DUT 2 and All DUT failures can be detected by performing a logical sum operation on the pass fail information to generate DUT information and performing a logical product operation on all the DUT information.

  FIG. 1 shows an example in which the positional relationship between the tester pin P and DUT 2 is freely changed. FIG. 4 shows an example in which the positional relationship between the tester pin P and DUT 2 is not changed (Modification 1). . In this case, the DUT (1) is connected to the tester pins P (1) and P (2), and the DUT (2) is connected to the tester pins P (3) and P (4). .

  In the case of FIG. 4, even if the conversion based on the correspondence table is not performed, the path fail information is adjacent to each other and is in a substantially grouped state. In this case, the pass / failure information can be directly input to the OR operation unit 12 without using the conversion unit 11. Of course, if the correspondence table in which DUT number 1 is associated with tester pin numbers 1 and 2 and DUT number 2 is associated with tester pin numbers 3 and 4 is used, the conversion unit 11 may be interposed. .

  FIG. 5 shows an example (Modification 2) in the case where there is one DUT pin of DUT 2. In this case, it is not necessary to group the pass fail information for each DUT 2. For this reason, the logical sum operation part 12 becomes unnecessary. In the case of FIG. 5, the DUT 2 and the tester pin P have a one-to-one relationship. However, the connection relationship between the DUT 2 and the tester pin P can be freely changed due to restrictions on the physical positional relationship.

  Therefore, the DUT information output unit 13 outputs the corresponding DUT information by converting the path fail information by the conversion unit 11 based on the correspondence table. Then, logical product is calculated by the logical product operation unit 14 to generate all DUT fail information, and the determination unit 15 detects whether or not all DUT fail has occurred.

  In the case of FIG. 5, since the logical product operation unit 14 finally performs logical product operation on all DUT information, the pass fail information output from the PE unit 3 corresponds to any DUT 2. It is not necessary to clarify the relationship. That is, the conversion unit 11 is not necessary because the conversion unit 11 does not have to convert the correspondence relationship of the path fail information.

  However, when the pass fail information is individually required for each DUT 2 and the detection of all DUT failures is also required, the DUT information is obtained for each DUT 2 by adopting the configuration shown in FIG. At the same time, all DUT failures can be detected.

1 Semiconductor Test Equipment 2 DUT
3 PE unit 4 arithmetic circuit 5 correspondence table storage unit 6 correspondence table setting unit 11 conversion unit 12 logical sum operation unit 13 DUT information output unit 14 logical product operation unit 15 determination unit 21 logical sum circuit

Claims (1)

A semiconductor test apparatus including a test unit that generates pass-fail information of the device under test based on output signals output from a plurality of devices under test,
A conversion unit that groups and outputs the pass-fail information for each device under test based on a correspondence table storing a correspondence relationship between a plurality of pins of the test unit connected to the device under test and the device under test; ,
A plurality of OR operation units that perform path OR operation by inputting path fail information grouped for each device under test, and output as device under test information;
An AND operation unit that performs an AND operation on all the device-under-test information output from the multiple OR operation units, and
A semiconductor test apparatus comprising:

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