JP2011018355A - Information processing apparatus and memory access arbitration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a small scale mechanism for inputting/outputting data to/from a memory at high speed having always high priority for a built-in memory of a processor.SOLUTION: An information processing apparatus includes a processor for executing pipeline processing to instructions, a memory built in the processor, and an input/output control means for accessing the memory with high priority. A memory access arbitration method includes the steps of suspending clock supply to the processor when accesses to the memory from the processor and the input/output control means compete (S512), executing the access to the memory from the input/output control means (S506), and releasing the clock wait of the processor after the access to the memory from the input/output control means ends and executing the access to the memory from the processor (S507, S511).

Description

  The present invention relates to an information processing apparatus having an external input / output mechanism capable of high-speed writing or reading from the outside with respect to a memory device incorporated in a processor, and a memory access arbitration method when access to the memory device competes. Is.

  Conventionally, when writing to and reading from a plurality of control devices with respect to one memory device, it has been the easiest implementation method to use a dual port memory. However, since the LSI market has recently shifted to emphasis on system LSIs and the circuit scale has increased, dual-port memory that occupies a large chip area is a cost viewpoint in system LSIs that require large-capacity memories. Is disadvantageous. In order to reduce the chip area, it is conceivable to use a single-port memory. However, depending on the timing when accessing from a plurality of control devices, access contention occurs, so it is necessary to arbitrate access.

  As a method for arbitrating access from a plurality of control devices, the conventional method arbitrates access as follows. When there is an access from a second control device having a higher priority than the first control device while the first control device is accessing the memory, until the access to the memory of the first control device is completed The second control device waits (waits), and when the access to the memory of the first control device is completed, the access to the memory of the second control device is started. In addition, while the second control device is accessing the memory, access to the memory of the first control device is completely prohibited, and the second control device preferentially uses the memory as the first control device. It can be accessed (see, for example, Patent Document 1).

  In other words, while the control device that has performed the access first is executing the access, the control device that has performed the access later cannot access the memory until the access of the control device that has performed the access first is completed.

Japanese Patent Laid-Open No. 9-198298

  However, there may be a case where priority is given to access from one of a plurality of control devices. For example, when considering access from an external processor via an external input / output mechanism to the processor's internal memory, access from the external processor to the processor's internal memory does not take a long time, but the external processor needs to operate at high speed. Therefore, there is a demand to always give priority to access from an external processor.

  When the above method is applied to a processor having an external input / output mechanism that requires high-speed access to such a processor built-in memory, the external input / output mechanism to the memory while the processor core is accessing the memory. When an access occurs, the external input / output mechanism waits until the access of the processor core is completed, and the access speed of the external input / output mechanism decreases.

  That is, there is a case where the access speed of the external input / output mechanism decreases depending on the access state of the processor to the memory. Therefore, when this mechanism is applied to data transfer from an external processor to a processor built-in memory via an external input / output mechanism, the external access speed is lowered, and the operation speed of the final set is also lowered.

  The present invention solves the above-described conventional problems, and realizes an external input / output mechanism that is always preferential and capable of high-speed access without a wait, regardless of the access state of the processor to the memory. An object is to provide an information processing apparatus and a memory access arbitration method.

  The information processing apparatus according to the present invention includes a data storage means, first and second data input / output means for accessing the data storage means, and a normal clock signal supplied to the second data input / output means. A clock generation unit including a clock oscillation unit to generate, and a clock wait control unit to generate a wait clock signal having a cycle that is an integral multiple of the cycle of the normal clock signal; the first data input / output unit; Control data selector means for switching access to the data storage means of the second data input / output means, and access to the data storage means by the first data input / output means and the second data input / output means The normal clock signal for the second data input / output means is applied to the clock for one clock cycle. And the second data input / output unit supplies the wait clock signal to the clock wait control unit, and accesses the data storage unit for one clock cycle. The input / output means is disabled, the first data input / output means is accessed during the one clock cycle, and the second data is accessed after the access of the first data input / output means during the one clock cycle. Access arbitration means for starting access to the data input / output means.

  According to the above configuration, when access contention occurs in the first and second data input / output means accessing the data storage means, the access arbitration is performed by waiting the clock of one data input / output means. Thus, it is possible to realize high-speed access that always has priority and no wait from either one of the first and second data input / output means.

  An information processing apparatus according to the present invention includes an internal memory, a processor that processes data stored in the internal memory, a clock oscillation unit that generates a normal clock signal supplied to the processor, and a cycle that the normal clock signal has A clock wait control unit that generates a wait clock signal having a cycle that is an integer multiple of the input, an input / output control unit that executes an access to the internal memory in response to an instruction from an external control device, When the access to the internal memory of the processor and the input / output control means competes, the normal clock signal is stopped by the clock oscillation unit for one clock cycle, and the wait clock signal is sent to the clock to the processor. The weight control unit supplies the signal to the input / output control means. Characterized in that it comprises an access arbitration unit for executing the processes preferentially, the.

  According to the above configuration, when an access conflict occurs between the processor accessing the internal memory and the external control device, the access control of the external control device is prioritized and access arbitration is performed, so that the external control device transfers to the internal memory. The speed of data exchange can be improved.

  In the above configuration, the processor and the input / output control unit further include a selection unit that switches access to the built-in memory, and the access arbitration unit includes the input / output control unit during access to the built-in memory. When an access request to the built-in memory is generated, the control unit outputs a control signal to the selection unit, and the selection unit that receives the control signal changes the access of the processor to access to the built-in memory of the input / output control unit. It is characterized by switching.

  According to the above configuration, when the processor accesses the built-in memory, when data is written to or read from the external memory from the external control device, the processor access is switched to the input / output control unit access. It is possible to realize high-speed access of an external control device that has priority over the above.

  In the above configuration, the memory device further comprises holding means for holding the read data output from the built-in memory before the wait operation of the processor during the wait operation of the processor, and the access arbitration means supplies the processor to the processor The read data is switched between the read data output from the built-in memory and the read data held by the holding means.

  According to the above configuration, even when the processor continuously accesses the memory, the read data output from the built-in memory and the read data held by the holding means are switched, so that it does not depend on the access state. High-speed access can be realized.

  The memory access arbitration method of the present invention comprises a data storage means, first and second data input / output means for accessing the data storage means, and a normal clock signal supplied to the second data input / output means. And a clock generation unit including a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of a cycle of the normal clock signal. Providing the normal clock signal to the first and second data input / output means, and accessing the data storage means by the first data input / output means and the second data input / output means. The normal clock signal for the second data input / output means is 1 clock. Providing a clock wait signal for stopping the clock wait signal during a clock cycle and disabling access to the data storage means for the second data input / output means during one clock cycle; Executing the access of the first data input / output means earlier than the input / output means, and releasing the stop of the clock signal of the second data input / output means after the access of the first data input / output means is completed. And a step of executing access to the second data input / output means.

  According to the above method, when an access conflict occurs between the first and second data input / output means accessing the data storage means, the access arbitration is performed by waiting the clock of one data input / output means. Thus, it is possible to realize high-speed access that always has priority and no wait from either one of the first and second data input / output means.

  The memory access arbitration method of the present invention includes a processor that pipelines an instruction, a memory provided in the processor, an input / output control unit that accesses the memory with higher priority than the processor, A clock including a clock oscillation unit that generates a normal clock signal to be supplied to the processor and the data input / output unit, and a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of the cycle of the normal clock signal A memory access arbitration method for an information processing apparatus, comprising: a step of providing the normal clock signal to the processor and the data input / output unit; and the processor and the input / output control unit to the memory. If access conflicts, the pro Generating a wait request signal for stopping the clock signal supplied to the memory for one clock cycle, and when the processor and the input / output control means access to the memory competes, Providing a clock wait signal for stopping a normal clock signal for one clock cycle, disabling access to the memory by the processor for one clock cycle; and accessing the processor by the memory of the input / output control means Switching to access to the memory, and releasing the wait request signal of the processor after the access of the input / output control means to the memory is completed, and executing the access to the memory of the processor.

  According to the above method, when the processor accesses the internal memory, when data is written to or read from the external to the internal memory, the processor access is switched to the input / output control means to give priority to the processor. High speed access can be realized. In addition, when access to the external input / output means competes with the processor, it is possible to realize high-speed access that can resume access only by waiting for one pipeline stage.

  The memory access arbitration method of the present invention includes a processor that pipelines an instruction, a memory provided in the processor, an input / output control unit that accesses the memory with higher priority than the processor, A clock including a clock oscillation unit that generates a normal clock signal to be supplied to the processor and the data input / output unit, and a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of the cycle of the normal clock signal A memory access arbitration method for an information processing apparatus, comprising: generating means; and holding means for holding read data output from the memory before the wait operation of the processor during the wait operation of the processor, Before the processor and the data input / output means When the read access of the input / output control means competes during the period in which the normal clock signal is provided and the processor has continuous read access to the memory, the memory outputs before the wait operation of the processor. Holding the read data, providing the clock wait signal for stopping the normal clock for the processor, executing the access of the input / output control means to the memory, and Releasing the stop of the clock signal of the processor after the access to the memory is completed, supplying the data held in the holding means to the processor, and resuming the access of the processor to the memory. .

  According to the above method, even when the processor continuously accesses the memory, the data held in the holding means is supplied to the processor, and the access of the processor to the memory is resumed. High-speed access can be realized without dependence.

  According to the present invention, when an access conflict occurs in two data input / output means accessing the data storage means, the access arbitration circuit performs access arbitration only by waiting for the clock of one data input / output means. Can be realized with a small circuit.

  According to the present invention, when the processor accesses the built-in memory in a single shot, when data is written to or read from the processor built-in memory from the outside, the processor is given high-speed access without waiting. Can be realized by a small-scale circuit that simply adds a circuit that waits for a clock supplied to the processor. Further, an access arbitration circuit capable of resuming access by simply waiting for one pipeline stage when access to the external input / output means competes with the processor can be realized.

  According to the present invention, it is possible to realize an external input / output unit that can be executed without depending on the access state even when the processor continuously accesses the memory.

The lineblock diagram showing the information processor of a 1st embodiment of the present invention. 3 is a flowchart showing the operation of the information processing apparatus shown in FIG. The block diagram which shows schematic structure of the information processing apparatus of the 2nd Embodiment of this invention. The circuit diagram which shows the structure of the read data holding | maintenance part in embodiment of this invention. 4 is a flowchart showing an operation of the information processing apparatus shown in FIG. 3. FIG. 4 is a timing chart illustrating an example of an operation of the information processing apparatus illustrated in FIG. 3 (when a processor performs single access). FIG. 4 is a timing chart illustrating an example of the operation of the information processing apparatus illustrated in FIG. 3 (when the processor continuously accesses).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing an information processing apparatus according to the first embodiment of this invention. In FIG. 1, the information processing device 150 includes a data storage device 101, a first data input / output device 102 having a high access priority with respect to the data storage device 101, and a second data input / output device having a low access priority. 103, a clock generation device 104 that supplies a clock to the second data input / output device 103, an access arbitration device 109, and a control signal selector 112.

  The access arbitration device 109 monitors the control signal 106 of the first data input / output device 102 and the control signal 108 of the second data input / output device 103, and sends the control signal 114 and write data 113 supplied to the data storage device 101. , An access selection signal 110 for switching between the first data input / output device 102 and the second data input / output device 103, and data storage of the first data input / output device 102 and the second data input / output device 103 When access to the device 101 competes, a clock wait request signal 111 for waiting for the second data input / output device 103 is generated.

  The control signal selector 112 receives the access selection signal 110 output from the access arbitration device 109, receives the write data 105 and the control signal 106 supplied from the first data input / output device 102 to the data storage device 101, and the second The write data 107 and the control signal 108 supplied from the data input / output device 103 to the data storage device 101 are switched.

  The operation of the embodiment configured as described above will be described below with reference to the flowchart of FIG. The access arbitration device 109 monitors the access status of the first data input / output device 102 and the second data input / output device 103 to the data storage device 101 (S201). When only the first data input / output device 102 is accessed from the state where the data storage device 101 is not accessed (S200) (A in S201), the access arbitration device 109 sets the control signal selector 112 to the first data input device. Switching to the output device 102 side (S202), the first data input / output device 102 accesses the data storage device 101 (S203). Thereafter, when the access to the data storage device 101 of the first data input / output device 102 is completed (A in S203), the access to the data storage device 101 is completed (S204).

  On the other hand, when there is an access from the second data input / output device 103 before the access to the data storage device 101 of the first data input / output device 102 is completed (B in S203), the access arbitration device 109 accesses A conflict is detected, a clock wait request signal 111 is output to the second data input / output device 103, and the second data input / output device 103 enters a wait state (S205). Thereafter, the first data input / output device 102 accesses the data storage device 101 (S206).

  When the access of the first data input / output device 102 to the data storage device 101 is completed, the wait state of the second data input / output device 103 is released (S207), and the access arbitration device 109 sets the control signal selector 112 to the second state. Switch to the data input / output device 103 side (S208), and the second data input / output device 103 accesses the data storage device 101 (S209).

  Even when only the second data input / output device 102 is accessed from the state where the data storage device 101 is not accessed (S200) (C of S201), the access arbitration device 109 sets the control signal selector 112 to the second data Switching to the input / output device 103 side (S208), the second data input / output device 103 accesses the data storage device 101 (S209). Thereafter, when the access to the data storage device 101 of the second data input / output device 103 is completed (B in S209), the access to the data storage device 101 is ended (S204).

  On the other hand, when there is an access from the first data input / output device 102 before the access to the data storage device 101 of the second data input / output device 103 ends (A in S209), or to the data storage device 101 When the first data input / output device 102 and the second data input / output device 103 simultaneously access the data storage device 101 (B in S201) from the state where there is no access (S200), the access arbitration device 109 causes access contention. Then, a clock wait request signal 111 is output to the second data input / output device 103, and the second data input / output device 103 enters a wait state (S210). Thereafter, the access arbitration device 109 switches the control signal selector 112 to the first data input / output device 102 side (S211), and the first data input / output device 102 accesses the data storage device 101 (S206). The operations after step S207 are as described above.

  As described above, according to the present embodiment, the data storage device 101 serving as the data storage unit, the first data input / output device 102 serving as the first data input / output unit, and the second data input / output unit are provided. A second data input / output device 103, a clock generation device 104 serving as clock generation means, a control signal selector 112 serving as switching means for switching access, and an access arbitration device 109 serving as access arbitration means for arbitrating access. When access to the data storage device 101 from the first data input / output device 102 and the second data input / output device 103 competes, the clock of the second data input / output device 103 is waited and the first data input / output device 103 is The access to the output device 102 is executed first, and the second data input / output device at the end of the access to the first data input / output device 102 Since the clock wait of 03 is released and the second data input / output device 103 is accessed, the access arbitration that allows the first data input / output device 102 to always access the data storage device 101 with priority is provided. This can be realized with a small circuit configuration that only performs weight control.

(Second Embodiment)
FIG. 3 is a block diagram showing a schematic configuration of an information processing apparatus according to the second embodiment of this invention. In FIG. 3, an information processing device 350 includes a clock generation unit 301, a processor built-in memory unit 304 that is built in the processor and can be accessed from outside the processor, a processor core unit 305 that pipelines instructions, and a processor core unit. An external input / output control unit 310 having higher access priority to the processor built-in memory 304 than the 305, a read data holding unit 322 that holds the processor-side read data 320 output from the external input / output control unit 310, and a processor core unit 305 and an access arbitration unit 315 that generates a wait request signal 316 when accesses from the external input / output control unit 310 occur simultaneously.

  The clock generation unit 301 includes a clock oscillation unit 338 and a clock wait control unit 337 that stops the clock supplied from the clock oscillation unit 338 while the wait request signal 316 is being input, and generates a clock having an integer multiple cycle. Prepare. A clock 302 is a clock without wait control output from the clock oscillation unit 338. A clock 303 is a wait-controlled clock output from the clock wait control unit 337.

  The processor core unit 305 includes a memory access control unit 330 that receives read data 323 from the memory unit 304 and a plurality of flip-flops 331, 332, 333, and 334, and a processor side address for accessing the memory unit 304 306, a memory device control signal 308 such as a processor side chip select (CS) signal 307, a read enable signal (RE), a write enable signal (WE), and the processor side write data 309 are generated.

  The external input / output control unit 310 includes an external input / output signal synchronization unit 336 and a memory access selector unit 335. The external input / output signal synchronization unit 336 is used to write and read data to / from the memory unit 304 from the outside of the processor, the external input / output address 325, the external input / output read enable / write enable (RE / WE) signal 326, the external Synchronized external input / output side address 311, external input / output side chip select (CS) signal 312, external input / output side write enable / read enable for receiving input / output write data 327 and accessing the processor built-in memory unit 304 A memory device control signal such as a (WE / RE) signal 313 and external input / output side write data 314 are generated. The memory access selector unit 335 switches between the memory control signal and write data from the external input / output signal synchronization unit 336 and the memory control signal and write data from the processor core unit 305, and writes the write data 317 and the write data to the processor built-in memory 304. By supplying the memory control signal 318 and switching the read data 319 from the processor built-in memory 304 to the processor core unit 305 and the external processor 328, the processor side read data (without holding) 320 is supplied to the read data holding unit 322, External input / output side read data 321 is supplied to the external processor 328. The processor built-in memory 304 outputs read data 319 to the memory access selector unit 335.

  The access arbitration unit 315 monitors the write enable signal and read enable signal 308 from the processor core unit 305, and the write enable signal and read enable signal 313 generated in the external input / output control unit 310, and the processor core unit 305 side The selector control signal 324 is sent to the memory access selector unit 335 in the external input / output control unit 310 in order to switch the memory control signal and write / read data of the memory and the memory control signal and write / read data on the external input / output control unit 310 side. Supply. Further, the access arbitration unit 315 transfers the processor core unit 305 to the processor core unit 305 when access from the processor core unit 305 to the processor built-in memory unit 304 and access from the external input / output control unit 310 to the processor built-in memory unit 304 occur simultaneously. A wait request signal 316 for causing the supplied clock to wait is generated.

  The read data holding unit 322 holds the processor side read data (no holding) 320 output from the memory access selector unit 335 in the external input / output control unit 310 and supplies the processor side read data 323 to the processor core unit 305. .

  FIG. 4 is a circuit diagram showing a configuration of the read data holding unit 322. In FIG. 4, the read data holding unit 322 updates the data at the rising edge of the clock next to the cycle in which the flip-flop enable signal 411 is “1”, and the read data output from the memory access selector unit 335 of the external input / output control unit 310. The flip-flop 401 that holds the data 320, the flip-flop 403 that delays the timing of the processor-side read enable (RE) signal 308 by one cycle of the clock 302 without wait control, and the wait request signal 316 that does not have wait control And a flip-flop 405 for delaying the timing of one cycle of 302. Further, an AND gate 407 that performs a logical product of a processor side read enable (RE) signal 308, a processor side read enable signal 404 delayed by one cycle, and a wait request signal 406 delayed by one cycle, and an output signal of the AND gate 407 When the selector control signal 408 is “1”, the held data output 402 is output to the processor side read data 323, and when the selector control signal 408 is “0”, the read data 320 is output to the processor side read data 323. And an AND gate 410 that takes a negative logical product of the processor side read enable signal 404 delayed by one cycle and the wait request signal 406 delayed by one cycle and generates a flip-flop enable signal.

  The operation of the embodiment configured as described above will be described below with reference to the flowchart of FIG. The memory 304 monitors the access state of the external input / output control unit 310 and the processor core unit 305 to the memory 304 (S501). When only the external input / output control unit 310 is accessed from a state where there is no access to the memory 304 (S500) (A in S501), the access arbitration unit 315 switches the memory access selector unit 335 in the external input / output control unit 310. Switching to the external input / output control unit 310 side (S502), the external input / output control unit 310 accesses the memory 304 (S503). Thereafter, when the access to the memory 304 of the external input / output control unit 310 is completed (A in S503), the access to the memory 304 is completed (S504).

  On the other hand, if there is an access from the processor core unit 305 before the access to the memory 304 of the external input / output control unit 310 is completed (B in S503), the access arbitration unit 315 detects an access conflict and detects the processor core unit 305. In response to this, a wait request signal 316 is output, and the processor core unit 305 enters a wait state (S505). Thereafter, the external input / output control unit 310 accesses the memory 304 (S506). When the access to the memory 304 of the external input / output control unit 310 is completed, the wait state of the processor core unit 305 is released (S507).

  If access contention occurred during continuous read access to the memory 304 of the processor core unit 305 (Y in S508), the data held in the read data holding unit 322 is supplied as read data of the processor core unit 305. (S509).

  On the other hand, when the occurrence of the access conflict is not during the continuous read access to the memory 304 of the processor core unit 305 (N in S508), the processor side read data (no holding) 320 is supplied as the read data of the processor core unit 305. To do. Thereafter, the access arbitration unit 315 switches the memory access selector unit 335 in the external input / output control unit 310 to the processor core unit 305 side (S510), and the processor core unit 305 accesses the memory 304 (S511).

  Even when only the processor core unit 305 is accessed from the state where there is no access to the memory 304 (S500) (C in S501), the access arbitration unit 315 also performs the memory access selector unit 335 in the external input / output control unit 310. Is switched to the processor core unit 305 side (S510), and the processor core unit 305 accesses the memory 304 (S511). Thereafter, when the access to the memory 304 of the processor core unit 305 is completed (B in S511), the access to the memory 304 is completed (S504).

  On the other hand, when there is an access from the external input / output control unit 310 before the access to the memory 304 of the processor core unit 305 is completed (A in S511), or when there is no access to the memory 304 (S500) When the input / output control unit 310 and the processor core unit 305 simultaneously access the memory 304 (B in S501), the access arbitration unit 315 detects an access conflict and outputs a wait request signal 316 to the processor core unit 305. The core unit 305 enters a wait state (S512). Thereafter, the access arbitration unit 315 switches the memory access selector unit 335 in the external input / output control unit 310 to the external input / output control unit 310 side (S513), and the external input / output control unit 310 accesses the memory 304 ( S506). The subsequent operation is as described above.

  Further, the details of the operation of the information processing apparatus according to the embodiment of the present invention will be described below with reference to the timing charts of FIGS. The timing chart of FIG. 6 shows a case where access to the processor internal memory 304 from the external input / output control unit 310 causes a conflict when the processor core unit 305 accesses the processor internal memory 304 in a single shot. The timing chart of FIG. 7 shows a case where access from the external input / output control unit 310 to the processor built-in memory 304 is in contention while the processor core unit 305 continuously performs read access to the processor built-in memory 304.

  In FIG. 6, when the processor side read enable signal 308 and the external input / output side read enable signal 313 are simultaneously generated at the timing of FIG. 6A, the access arbitration unit 315 of FIG. A wait request signal 316 is supplied to the clock generation unit 301.

  As a result, the clock generation unit 301 in FIG. 3 causes the wait-controlled clock 303 supplied to the processor core unit 305 to wait for one cycle at the B timing in FIG. The processor side address 306, the processor side CS signal 307, and the processor side read enable (RE) signal 308 output from the processor core unit 305 are output via the flip-flops 331 to 334 in the processor core unit 305, respectively. Therefore, at the timing B during the wait period of the processor core unit 305, the output state at the timing A is held.

  At this time, the access arbitration unit 315 in FIG. 3 controls the memory access selector unit 335 in the external input / output control unit 310 in FIG. Then, the memory access selector unit 335 in the external input / output control unit 310 is externally input / output with respect to the processor built-in memory 304 during the period of timing A in FIG. 6, that is, the period one cycle before the processor core unit 305 performs the wait operation. The memory control signal is supplied from the control unit 310, and the memory control signal from the processor core unit 305 is supplied during the period of timing B in FIG.

  Accordingly, the processor built-in memory 304 outputs the read data by the external input / output control unit 310 as read data 319 during the period of timing B in FIG. In the period of timing C, that is, in the period of the first cycle in which the processor returns from the wait state, the read data by the access of the processor core unit 305 is output as the read data 319. In the period of timing C in FIG. 6, the selector control signal 408 in FIG. 4 is “0”, and the read data 319 is supplied to the processor side read data 323 via the processor side read data (without holding) 320. Is done.

  In the timing chart of FIG. 7, while the processor core unit 305 is continuously performing read access to the processor built-in memory 304, the processor built-in memory 304 is transferred to the processor built-in memory 304 from the external input / output control unit 310 during the period of timing A in FIG. 7. When there is an access, the wait request signal 316 is generated in the period of timing A in FIG. 7 as in the case of FIG. 6, and the processor core unit 305 enters the wait operation in the period of timing B.

  At this time, similarly to the case of FIG. 6, the processor built-in memory 304 outputs the read data by the access of the external input / output control unit 310 to the read data 319 in the period of timing B in FIG. Thus, the read data by the access of the processor core unit 305 is output to the read data 319.

  However, at this time, in the read instruction to the processor built-in memory 304 of the processor core unit 305 one cycle before in which the access to the processor built-in memory 304 of the processor core unit 305 and the access of the external input / output control unit 310 compete, The read data is output at timing A in FIG. 7, and at the next timing B, the processor core unit 305 is in the wait operation. Therefore, at the timing C when the processor core unit 305 returns from the wait state, the processor core unit 305 The necessary read data cannot be imported.

  Therefore, the read data output at the timing A by the flip-flop 401 in FIG. 4 is held until the timing B and output to the retained data output 402. Further, the AND gate 407 in FIG. , The selector control signal 408 is set to “1” at timing B, whereby the selector 409 supplies the retained data output 402 to the processor-side read data 323, and the data at timing C of the processor core unit 305. The acquisition is possible.

  On the other hand, since the wait state is released at timing C, the selector control signal 408 is returned to “0”, and the selector 409 supplies the read data 319 to the processor side read data 323.

  As described above, even when access from the external input / output control unit 310 competes during continuous access to the processor built-in memory unit 304 of the processor core unit 305 as shown in FIG. .

  As described above, according to the present embodiment, the processor core unit 305 serving as a processor for pipeline processing of instructions, the processor built-in memory 304 serving as a memory built in the processor, and an input for executing preferential access to the memory. To an external input / output control unit 310 serving as an output control unit, a clock generation unit 301 serving as a clock generation unit that supplies a clock to the processor core unit 305, and a processor built-in memory 304 of the processor core unit 305 and the external input / output control unit 310 The access arbitration unit 315 is an access arbitration unit that monitors access and performs access arbitration. When the external input / output control unit 310 competes for access while the processor core unit 305 is accessing the processor built-in memory 304, the external input / output control unit 310 waits for the clock supplied to the processor core unit 305. The processor core unit 305 is accessed and the processor core unit 305 is accessed when the access to the processor built-in memory 304 of the external input / output control unit 310 is completed.

  As a result, when the processor core unit 305 accesses the processor built-in memory 304 in a single shot, the external input / output control unit 310 that can access the processor built-in memory 304 at high speed without waiting is supplied with a clock to be supplied to the processor core unit 305. This can be realized with a small-scale circuit that simply adds a circuit to wait.

  Furthermore, for the processor core unit 305, it is possible to realize access arbitration that can resume access only by waiting for one pipeline stage when access with external input / output means competes. In addition, a read data holding unit 322 serving as a holding unit for holding output data from the memory is provided, and the external input / output control unit 310 is built in the processor when the processor core unit 305 continuously accesses the processor built-in memory 304 for reading. Even when access to the memory 304 occurs and access contention occurs, the data held in the read data holding unit 322 is supplied to the processor core unit 305 and access to the processor built-in memory 304 is resumed. Access from the external input / output control unit 310 during continuous access is also possible.

DESCRIPTION OF SYMBOLS 101 Data storage device 102 1st data input / output device 103 2nd data input / output device 104 Clock generator 105 Write data 106 Control signal 107 Write data 108 Control signal 109 Access arbitration device 110 Access selection signal 111 Clock wait request signal 112 Control signal selector 113 Write data 114 Control signal 115 Read data 301 Clock generation unit 302 Clock without wait control 303 Wait-controlled clock 304 Processor built-in memory unit 305 Processor core unit 306 Processor side address 307 Processor side CS signal 308 Processor side WE / RE signal 309 Processor side write data 310 External input / output control unit 311 External input / output side address 312 External input / output side CS signal 313 External input WE / RE signal on output side 314 External I / O side write data 315 Access arbitration unit 316 Wait request signal 317 Write data 318 Memory control signal 319 Read data 320 Processor side read data (no hold)
321 External input / output read data 322 Read data holding unit 323 Processor side read data 324 Selector control signal 325 External input / output address 326 External input / output WE / RE signal 327 External input / output write data 328 External processor 330 Memory access control unit 331-334 Flip-flop 335 Memory access selector section 336 External input / output signal synchronization section 337 Clock wait control section 338 Clock oscillation section 401 Flip-flop 402 Holding data output 403 Flip-flop 404 Processor-side RE signal delayed by one cycle 405 Flip-flop 406 One cycle delayed Wait request signal 407 AND gate 408 selector control signal 409 selector 410 AND gate

Claims (7)

Data storage means;
First and second data input / output means for accessing the data storage means;
A clock oscillation unit that generates a normal clock signal supplied to the second data input / output unit; and a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of the cycle of the normal clock signal. Clock generation means;
Control signal selector means for switching access to the data storage means of the first data input / output means and the second data input / output means;
When the access to the data storage means of the first data input / output means and the second data input / output means competes, the normal clock signal for the second data input / output means is changed to the normal data signal for one clock cycle. The clock oscillation unit is stopped, the wait clock signal is supplied to the clock wait control unit to the second data input / output unit, and access to the data storage unit is input to the second data input unit for one clock cycle. The output means is disabled, the first data input / output means is accessed during the one clock cycle, and the second data input is terminated after the access of the first data input / output means during the one clock cycle. Access arbitration means for starting access to the data input / output means;
An information processing apparatus comprising: Built-in memory,
A processor for processing data stored in the internal memory;
A clock generation unit including a clock oscillation unit that generates a normal clock signal supplied to the processor, and a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of the cycle of the normal clock signal;
Input / output control means for receiving an instruction from an external control device and executing access to the internal memory;
When the access to the internal memory of the processor and the input / output control unit competes, the normal clock signal is stopped by the clock oscillation unit for one clock cycle, and the wait clock signal is sent to the processor. An access arbitration unit that supplies the clock wait control unit and preferentially executes the access of the input / output control unit;
An information processing apparatus comprising: An information processing apparatus according to claim 2,
A selection means for switching access to the internal memory of the processor and the input / output control means;
The access arbitration means outputs a control signal to the selection means when an access request to the internal memory of the input / output control means occurs during access to the internal memory of the processor,
The information processing apparatus, wherein the selection unit that receives the control signal switches the access of the processor to access to the internal memory of the input / output control unit. An information processing apparatus according to claim 2,
Further comprising holding means for holding the read data output from the built-in memory before the wait operation of the processor during the wait operation of the processor;
The information processing apparatus, wherein the access arbitration unit switches read data supplied to the processor between read data output from the built-in memory and read data held by the holding unit. Data storage means; first and second data input / output means for accessing the data storage means; a clock oscillation unit for generating a normal clock signal supplied to the second data input / output means; A clock generation unit including a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of a cycle of a normal clock signal, and a memory access arbitration method for an information processing device,
Providing the normal clock signal to the first and second data input / output means;
When the access to the data storage means of the first data input / output means and the second data input / output means competes, the normal clock signal for the second data input / output means is changed to the normal data signal for one clock cycle. Providing a clock wait signal for stopping the clock wait signal and disabling access to the data storage means to the second data input / output means for one clock cycle;
Executing the access of the first data input / output means earlier than the second data input / output means;
Canceling the stop of the clock signal of the second data input / output means after the access of the first data input / output means is completed, and executing the access of the second data input / output means;
A memory access arbitration method comprising: A processor that pipelines instructions, a memory provided in the processor, an input / output control unit that executes access to the memory with a higher priority than the processor, and a supply to the processor and the data input / output unit An information processing apparatus comprising: a clock generation unit that generates a normal clock signal to be generated; and a clock generation unit that includes a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of a cycle of the normal clock signal. Memory access arbitration method of
Providing the normal clock signal to the processor and the data input / output means;
Generating a wait request signal for stopping a clock signal supplied to the processor for one clock cycle when access to the memory of the processor and the input / output control means competes;
When the access of the processor and the input / output control means to the memory competes, a clock wait signal is provided to stop the normal clock signal for the processor for one clock cycle, and the access of the processor to the memory is 1 A step that is disallowed during the clock cycle;
Switching access of the processor to access to the memory of the input / output control means;
Canceling the wait request signal of the processor after the access to the memory of the input / output control means is completed, and executing the access to the memory of the processor;
A memory access arbitration method including: A processor that pipelines instructions, a memory provided in the processor, an input / output control unit that executes access to the memory with a higher priority than the processor, and a supply to the processor and the data input / output unit A clock generation unit including a clock oscillation unit that generates a normal clock signal to be transmitted, a clock wait control unit that generates a wait clock signal having a cycle that is an integral multiple of a cycle of the normal clock signal, and a wait operation of the processor A memory access arbitration method for an information processing apparatus, comprising: holding means for holding read data previously output from the memory during a wait operation of the processor;
Providing the normal clock signal to the processor and the data input / output means;
The step of holding the read data output from the memory before the wait operation of the processor when the read access of the input / output control means competes during the period in which the processor continuously accesses the memory When,
Providing the clock wait signal for stopping the normal clock for the processor;
Executing access to the memory of the input / output control means;
After the access of the input / output control means to the memory is completed, the stop of the clock signal of the processor is released, the data held in the holding means is supplied to the processor, and the processor's access to the memory is resumed. And steps to
A memory access arbitration method including:

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