JP5445385B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus including an accelerator that executes specific processing at high speed in addition to a CPU.

  In a data processing apparatus (computer system) connected with modules such as a CPU, ROM, and RAM, and a large-scale SoC (silicon-on-chip) in which those functions are mounted on one chip, an accelerator is combined. . The accelerator is a dedicated processor designed to execute specific processing such as image processing at high speed, and reduces processing load on the CPU to improve processing speed when executing specific processing.

  An access method (protocol) for a storage area of a master operation module that performs a master operation such as an accelerator may be different from an access protocol of another element such as a CPU. In such a case, the master operation module cannot directly access a normal storage area such as an external memory constituted by a NAND ROM or the like.

  In such a case, a module capable of accessing an external memory such as a CPU (Central Processing Unit) or DMAC (Direct Memory Access Control) serves as a master to transfer target data from the external memory to a dedicated internal memory. A method of transferring to an area is taken. Hereinafter, an example in which an accelerator is used as a master operation module and the DMAC performs data transfer will be described, but it is needless to say that the present invention is not limited to this.

  FIG. 1 is a diagram showing a configuration of a data processing apparatus that executes such an access method and a data access path.

  As shown in FIG. 1, the data processing apparatus 10 includes an internal bus 11, a CPU 12, a DMAC 13, an accelerator (ACC) 14, an internal memory 15, and a memory controller 16. The data processing device 10 is realized as an SoC chip, for example. In FIG. 1, an operation memory 17 provided externally is connected to the internal bus 11 of the data processing apparatus 10, but the operation memory 17 may be provided in the SoC chip.

  Hereinafter, an example in which the data processing device 10 is realized as an SoC chip will be described. However, the data processing apparatus 10 can also be realized by connecting the modules of the CPU 12, the DMAC 13, the accelerator (ACC) 14, the internal memory 15, and the memory controller 16 with wiring corresponding to the internal bus 11. It is.

  The external memory 18 is a memory that stores data to be processed by the ACC 14 and is connected to the memory controller 16. Since the access protocol of the ACC 14 is different from the access protocol of the external memory 18, the ACC 14 cannot directly access the external memory 18. In the example of FIG. 1, the DMAC 13 reads data from the external memory 18 via the memory controller 16, expands the internal memory 15 with sequential addresses, and writes the data in a form accessible to the accelerator 14. The ACC 14 reads data stored in the internal memory 15.

  However, this method has a problem that it is necessary to transfer all data necessary for the processing of the accelerator (ACC) 14 to the internal memory 15 and the memory capacity necessary for the data processing device 10 increases.

  Therefore, a method of reducing the capacity of the internal memory 15 by configuring the internal memory 15 with a FIFO memory is used. In this case, data transfer from the external memory 18 to the internal memory 15 is sequentially performed, and the ACC 14 reads data from the internal memory 15. The area read by the ACC 14 is released, and new data is transferred to that area. Thereby, the transferred data is always read in the order of transfer, and the data is sequentially transferred so as to fill the free space in the internal memory 15.

  However, in the method using the FIFO memory, the accelerator needs to access all the transferred data in order, and cannot access the necessary data by skipping intermediate data in image processing or the like. In other words, there is a problem that the accelerator cannot acquire only necessary data.

JP-A-11-167480 JP 2001-92778 A JP 2002-513955 A JP 2005-44361 A JP-A-9-212661 JP-A-9-198301 Japanese Patent Laid-Open No. 7-20833

  It has been desired that the master operation module can read out only necessary data by diversifying the access method when accessing the internal memory and reduce the capacity of the internal memory.

  According to one aspect of the invention, the CPU, the master operation module, the internal memory directly accessible from the master operation module, and the external memory not directly accessible from the master operation module are accessed and stored in the external memory in the external memory. A data transfer unit that transfers the received data, and the internal memory has two or more page storage areas logically divided in units of pages, and the data transferred from the external memory by the data transfer unit is an address of the internal memory And a write address conversion unit for writing to two or more page storage areas, and a read address of the master operation module in accordance with a read operation of the master operation module, converting the read address of the master operation module into an address of the internal memory. A read address conversion unit for reading data stored in the area; A state transition control unit having a state flag corresponding to each of the above page storage areas, and the read address conversion unit performs a read operation on the page storage area written by the write address conversion unit, and performs writing There is provided a data processing device characterized in that the address conversion unit controls to perform a write operation on a page storage area for which the read operation by the read address conversion unit has been completed.

  According to the above aspect, the internal memory for the master operation module to read data stored in memories having different access protocols can be realized with a small capacity, and the master operation module access method can be diversified.

FIG. 1 is a diagram showing a configuration of a data processing apparatus that performs access via an internal memory and data access paths in order to enable access using different protocols. FIG. 2 is a diagram illustrating a configuration of the data processing apparatus according to the first embodiment and a data access path. FIG. 3 is a diagram showing the configuration of the internal memory in the first embodiment. FIG. 4 is a diagram illustrating an access operation in which the DMAC writes data in the external memory to the internal memory via the memory controller and the ACC reads the data transferred to the internal memory in the internal memory of the first embodiment. FIG. 5 is a time chart showing changes in write data and read data in the access operation of the internal memory in the first embodiment. FIG. 6 is a diagram showing a state transition of the page area of the internal memory core in the first embodiment. FIG. 7 is a flowchart showing a process of writing data transferred by the DMAC to the internal memory (page area of the internal memory core) in the first embodiment. FIG. 8 is a flowchart showing a process of reading data from the internal memory (page area of the internal memory core) by ACC in the first embodiment. FIG. 9 is a diagram illustrating the configuration of the data processing apparatus and the data access path according to the second embodiment. FIG. 10 is a diagram showing a configuration of the internal memory in the second embodiment. FIG. 11 shows an access operation in which two DMACs write data of two external memories to the internal memory via the memory controller and ACC reads the data transferred to the internal memory in the internal memory of the second embodiment. FIG. FIG. 12 is a time chart showing changes in write data and read data in the access operation of the internal memory in the second embodiment. FIG. 13 is a flowchart showing a process of writing the transferred data to the internal memory (page area of the internal memory core) in the second embodiment. FIG. 14 is a diagram showing the configuration of the internal memory in the third embodiment. FIG. 15 shows an access operation in which two DMACs write data in two external memories to the internal memory via the memory controller and ACC reads the data transferred to the internal memory in the internal memory of the third embodiment. FIG. FIG. 16 is a flowchart showing a process of writing transferred data to the internal memory (page area of the internal memory core) in the third embodiment. FIG. 17 is a diagram illustrating a configuration of a data processing device and a data access path according to the fourth embodiment. FIG. 18 is a diagram showing the configuration of the internal memory in the fourth embodiment. FIG. 19 illustrates an access operation in which the DMAC writes the data in the external memory to the internal memory via the memory controller and the two ACCs read the data transferred to the internal memory in the internal memory of the fourth embodiment. FIG. FIG. 20 is a time chart showing changes in write data and read data in the access operation of the internal memory in the fourth embodiment. FIG. 21 is a flowchart showing a process of reading data from the internal memory (page area of the internal memory core) by two ACCs in the fourth embodiment. FIG. 22 is a diagram illustrating a configuration of the internal memory according to the fifth embodiment. FIG. 23 is a diagram illustrating an access operation in which the DMAC writes data in the external memory to the internal memory via the memory controller and the ACC reads the data transferred to the internal memory in the internal memory of the fifth embodiment. . FIG. 24 is a flowchart showing a process of reading data from the internal memory (page area of the internal memory core) by ACC in the fourth embodiment. FIG. 20 is a time chart for explaining the problem even when reading is stopped halfway without reading all the data written in the internal memory in the fourth embodiment. FIG. 26 is a diagram illustrating a configuration of a data processing apparatus and a data access path according to the sixth embodiment. FIG. 27 is a diagram showing the configuration of the internal memory in the sixth embodiment. FIG. 28 is a diagram illustrating state transition of the page area of the internal memory core in the sixth embodiment. FIG. 29 is a flowchart showing a process of writing transferred data to the internal memory (page area of the internal memory core) in the sixth embodiment. FIG. 30 is a flowchart showing a process of reading data from the internal memory (page area of the internal memory core) by ACC in the sixth embodiment. FIG. 31 is a flowchart illustrating processing performed when the read processing by ACC is completed in the sixth embodiment. FIG. 32 is a diagram showing the configuration of the internal memory in the seventh embodiment. FIG. 33 is a diagram showing state transition of the page area of the internal memory core in the seventh embodiment. FIG. 34 is a time chart showing changes in write data and read data in the access operation of the internal memory in the seventh embodiment. FIG. 35 is a flowchart showing a process of reading data from the internal memory (page area of the internal memory core) by ACC in the seventh embodiment.

  FIG. 2 is a diagram illustrating a configuration of the data processing apparatus 10A according to the first embodiment and a data access path.

  As shown in FIG. 2, the data processing apparatus 10A includes an internal bus 11, a CPU 12, a DMAC 13, an accelerator (ACC) 14, a memory controller 16, and an internal memory 20A. The data processing apparatus 10A is realized as a SoC chip, for example. In FIG. 2, the operation memory 17 provided outside is connected to the internal bus 11 of the data processing apparatus 10, but the operation memory 17 may be provided in the SoC chip. In the first embodiment, the example in which the data processing device 10A is realized as an SoC chip has been described. However, the data processing device 10A includes a CPU 12, a DMAC 13, an accelerator (ACC) 14, a memory controller 16, an internal You may implement | achieve in the form which connects each module of the memory 20A with the wiring corresponding to the internal bus 11. FIG.

  The external memory 18 is a memory that stores data to be processed by the ACC 14 and is connected to the memory controller 16. Since the access protocol of the ACC 14 is different from the access protocol of the external memory 18, the ACC 14 cannot directly access the external memory 18. In the data processing apparatus 10A of the first embodiment, the DMAC 13 reads data from the external memory 18 via the memory controller 16, expands the internal memory 20A with sequential addresses, and writes the data in a form accessible to the accelerator 14. The ACC 14 reads data stored in the internal memory 20A. Note that the CPU 12 can read the data in the external memory 18 and write the data in the internal memory 20A without using the DMAC 13.

  As shown in FIG. 2, the internal memory 20 </ b> A includes an internal memory core 21, a write address conversion mechanism 22, a read address conversion mechanism 23, and a state transition control unit 24. The write address conversion mechanism 22 converts the write address output from the DMAC 13 into the address of the internal memory core 21 and writes the transferred write data to the converted address of the internal memory core 21. The read address conversion mechanism 23 converts the read address output from the ACC 14 into an address of the internal memory core 21 and reads data from the converted address of the internal memory core 21.

  FIG. 3 is a diagram showing a configuration of the internal memory 20A in the first embodiment.

  The internal memory core 21 is composed of a plurality of pages 31 </ b> A to 31 </ b> D, and is accessed by the write address conversion mechanism 22 and the read address conversion mechanism 23 with the internal memory address. The internal core memory 21 is divided into a plurality (four in FIG. 3) of page areas 31A to 31D as will be described later. Each page area can be independently accessed from the outside, and when writing or reading to a certain page area, it seems that writing or reading to another page area is possible. A memory capable of such an operation can be realized by providing a bus arbitration circuit if a high-speed accessible memory is used. For example, a double buffer configuration or a two-port memory can be used. It is.

  The write address conversion mechanism 22 includes a write operation control unit 41, an internal memory capacity register 42, and a page capacity register 43. The internal memory capacity register 42 stores information on the entire capacity of the internal memory core 21, and the page capacity register 43 stores information on the capacity of each page. For example, the CPU 12 determines and sets the value of the internal memory core 21 according to the capacity used by the ACC 14 in the process, and the value of the page capacity register 43 according to the page size of the ACC 14 in the process. Thus, the page size and the number of pages can be arbitrarily set without redesigning the hardware.

  The write operation control unit 41 generates an internal memory write address based on the write address from the DMAC 13, the values of the internal memory capacity register 42 and the page capacity register 43, and the status flag, and outputs the internal memory write address to the internal memory core 21. Write data from the DMAC 13 is output to the internal memory core 21 in synchronization with the internal memory write address. Further, the write operation control unit 41 sends a write page instruction signal, a write notification and a write completion notification based on the write address, the values of the internal memory capacity register 42 and the page capacity register 43, and the status flag. Generate and output to the state transition control unit 24. The state flag is output from the state transition control unit 24.

  The read address conversion mechanism 23 includes a read operation control unit 51, an internal memory capacity register 52, and a page capacity register 53. The internal memory capacity register 52 and the page capacity register 53 store the same values as the internal memory capacity register 42 and the page capacity register 43, and can be omitted. If the values of the internal memory capacity registers 42 and 52 and the page capacity registers 43 and 53 are fixed, the internal memory capacity registers 42 and 52 and the page capacity registers 43 and 53 need not be provided.

  The read operation control unit 41 generates an internal memory read address based on the read address from the ACC 14, the values of the internal memory capacity register 52 and the page capacity register 53, and the status flag, and outputs the internal memory read address to the internal memory core 21. The read data read from the internal memory core 21 in accordance with the internal memory read address is transmitted to the ACC 14. Further, the read operation control unit 51 sends a read page instruction signal, a read (Read) notification, and a read (Read) completion notification based on the read address, the values of the internal memory capacity register 52 and the page capacity register 53, and the status flag. Generate and output to the state transition control unit 24.

  The state transition control unit 24 has state flags 61A to 61D for each page corresponding to the plurality of pages 31A to 31D of the internal memory core 21, and controls access to the internal memory core 21 based on the flags.

  FIG. 4 illustrates an access operation in which the DMAC 13 writes the data in the external memory 18 to the internal memory 20A via the memory controller 16 and the ACC 14 reads the data transferred to the internal memory 20A in the internal memory 20A of the first embodiment. It is a figure to do. FIG. 4 shows an example in which the areas 31A and 31B for two pages of the internal memory core 21 are used.

  First, a transfer operation by the DMAC 13, that is, a write operation to the internal memory 20A will be described. As shown in FIG. 4, the external memory 18 stores data of a plurality of pages (eight pages here) processed by the ACC 14. The DMAC 13 reads the data stored in the external memory 18 in order from the first page via the memory controller 16, and transfers the data to the write address conversion mechanism 22 of the internal memory 20A by direct memory access (DMAC). The write address conversion mechanism 22 performs address conversion to convert to the internal memory write address based on the write address from the DMAC 13, the values of the internal memory capacity register 42 and the page capacity register 43, and the status flag. Further, the write address conversion mechanism 22 determines the corresponding page area in the internal memory core 21 from the internal memory write address, checks the status flag of the page, and waits until it becomes possible if writing is impossible. If writing is possible, write data is written. The write address conversion mechanism 22 outputs a write notification to the state transition control unit 24 when writing to the internal memory core 21. Further, the write address conversion mechanism 22 outputs a write completion notification to the state transition control unit 24 when writing to the final address of the page. When the state transition control unit 24 receives the write completion notification, the state transition control unit 24 transitions the status flag of the page to “waiting for reading”. In FIG. 4, when the writing of the area 31A of the first page is completed, the corresponding status flag 61A transitions to “Read wait”.

  Thereafter, the DMAC 13 reads the second page data stored in the external memory 18 via the memory controller 16 and transfers it to the write address conversion mechanism 22 of the internal memory 20A. Write to 21.

  On the other hand, when the writing of the data for the first page to the internal memory 20A is completed, the ACC 14 starts the operation of reading the data for the first page from the internal memory 20A. During this time, the DMAC 13 writes the second page data in the internal memory 20A in parallel.

  A data read operation from the internal memory 20A by the ACC 14 will be described. As shown in FIG. 4, the ACC 14 first outputs a read address to the read address conversion mechanism 23. The read address conversion mechanism 23 performs address conversion for conversion into an internal memory read address based on the read address from the ACC 14, the values of the internal memory capacity register 52 and the page capacity register 53, and the status flag. Further, the read address conversion mechanism 23 determines the corresponding page area in the internal memory core 21 from the internal memory read address, checks the status flag of the page, and if it cannot be read, waits until it becomes possible, If data can be read, data is read. When reading data from the internal memory core 21, the read address conversion mechanism 23 outputs a read notification to the state transition control unit 24. Further, when reading from the final address of the page, the read address conversion mechanism 23 outputs a read completion notification to the state transition control unit 24. When the state transition control unit 24 receives the Read completion notification, the state transition control unit 24 causes the state flag of the page to transition to “Waiting for writing”. In FIG. 4, when the reading of data from the area 31A of the first page is completed, the corresponding status flag 61A transitions to “Waiting for writing”.

  Thereafter, the ACC 14 performs the same process for reading data of the second page stored in the internal memory 20A.

  FIG. 5 is a time chart showing changes in write data and read data in the access operation of the internal memory 20A. This time chart is an operation time chart when the data transfer speed from the external memory 18 to the internal memory 20A by the DMAC 13 and the read speed from the internal memory 20A by the ACC 14 are substantially equal. In FIG. 5, single-line rectangles in the first page area and the second page area indicate writing of transfer data to the internal memory 20A by the DMAC 13, and double-lined rectangles at both ends indicate data from the internal memory 20A by the ACC 14. Read of.

  As shown in FIG. 5, the data transfer of the first page by the DMAC 13 and the writing of the transferred data to the first page area 31A are performed. When the data transfer for the first page is completed, data transfer for the second page by the DMAC 13 and writing of the transferred data to the second page area 31B are subsequently performed. Immediately after the data transfer of the first page is completed (here, after the data transfer of the second page is started), the ACC 14 reads the data of the first page from the first page area 31A. When the reading of the first page data by the ACC 14 is completed, the data transfer of the second page by the DMAC 13 is completed, and the data transfer of the third page by the DMAC 13 and the writing of the transferred data to the first page area 31A are completed. Has been started. Therefore, reading of the second page data from the second page area 31B by the ACC 14 is started. Thereafter, such an operation is repeated. Thereby, data writing to and reading from the second page area 31B to the first page area 31A are alternately performed in parallel, and the ACC 14 stores the data stored in the external memory 18 in different forms. It can be read at high speed.

  In general, the data transfer speed from the external memory 18 to the internal memory 20A by the DMAC 13 and the read speed from the internal memory 20A by the ACC 14 are different. When the data transfer rate by the DMAC 13 is faster than the read rate by the ACC 14, there may occur a case where newly transferred data is written in a page area where reading is not performed. On the contrary, when the data transfer rate by the DMAC 13 is slower than the read rate by the ACC 14, data may be read from a page area where writing is not performed (data of the previous page is written). When such a state occurs, the ACC 14 cannot read correct data.

  Therefore, in the data processing apparatus 10A of the first embodiment, when a read operation is requested for data and a page that have not yet been written, the read address conversion mechanism 23 waits for the read operation. In addition, when a write operation is requested for data and a page that have not yet been read, the write address conversion mechanism 22 waits for the write operation.

  FIG. 6 is a diagram illustrating state transitions of the page areas 31A to 31D of the internal memory core 21 in the data processing device 10A of the first embodiment. There are four possible states: Write Wait (00), Write (01), Read Wait (10) and Read (11), depending on the operation. Changes as shown in FIG. When the operation starts, the state waits for writing (00) and waits in that state until the next operation is performed. When writing (Write) is performed, it changes to (01) during writing (Write), the state is maintained until writing (Write) is completed, and when writing (Write) is completed, it waits for (Read) (10) Become. Wait for (Read) (10) and wait in that state until the next operation is performed.When reading (Read) is performed, it changes to (11) during reading (Read), and reading (Read) is completed This state is maintained until reading is completed, and when reading is completed, writing is waited for (00).

  FIG. 7 is a flowchart showing a process of writing data transferred by the DMAC 13 to the internal memory 20A (page areas 31A to 31D of the internal memory core 21).

  In step S11, the DMAC 13 issues a write process to the write address conversion mechanism 22 of the internal memory 20A.

  In step S12, the write address conversion mechanism 22 calculates an internal memory write address and a write page from the input write address based on the set register information.

  In step S13, the write address conversion mechanism 22 determines whether the state of the write page is waiting for reading (10) or reading (11). Since writing cannot be performed when the writing page is waiting for reading or reading, the process waits until these states are completed, and proceeds to the next step when these states are completed.

  In step S14, the write address conversion mechanism 22 determines whether the state of the write page is Write wait (00). If it is Write wait (00), the process proceeds to Step S15. Proceed to S16.

  In step S15, the state transition control unit 24 causes the state flag of the write page to transition to “writing” (01).

  In step S <b> 16, the write address conversion mechanism 22 writes the transferred data to the internal memory write address of the internal memory core 21.

  In step S17, the write address conversion mechanism 22 determines whether the internal memory write address is the final address of the write page based on the set register information. If it is the final address, the process proceeds to step S18. Otherwise it ends. Thereafter, steps S11 to S17 are repeated for the same written page.

  In step S18, the state transition control unit 24 causes the state flag of the write page to transition to Read wait (10), and the process ends.

  FIG. 8 is a flowchart showing a process of reading data from the internal memory 20A (page areas 31A to 31D of the internal memory core 21) by the ACC 14.

  In step S21, the ACC 14 issues a read process to the read address conversion mechanism 23 of the internal memory 20A.

  In step S22, the read address conversion mechanism 23 calculates an internal memory read address and a read page from the input read address based on the set register information.

  In step S <b> 23, the read address translation mechanism 23 determines whether the state of the read page is waiting for writing (010) or writing (01). Since reading cannot be performed when the read page is waiting for writing or writing, the process waits until these states are completed, and proceeds to the next step when these states are completed.

  In step S24, the read address translation mechanism 23 determines whether or not the read page state is waiting for read (10). If the read page is waiting for read (10), the process proceeds to step S25. Proceed to S26.

  In step S25, the state transition control unit 24 changes the state flag of the read page to “Reading” (11).

  In step S <b> 26, the read address conversion mechanism 23 reads data from the internal memory read address of the internal memory core 21.

  In step S27, the read address conversion mechanism 23 determines whether the internal memory read address is the final address of the read page based on the set register information. If it is the final address, the process proceeds to step S28. Otherwise it ends. Thereafter, steps S21 to S27 are repeated for the same read page.

  In step S28, the state transition control unit 24 changes the status flag of the read page to wait for writing (00), and the process ends.

  Summarizing the items described above, the data processing apparatus 10A of the first embodiment has the following configuration.

  (1) Although the internal memory 20A (internal memory core 21) is provided, the capacity thereof may be smaller than the memory capacity required for processing of the accelerator (ACC) 14.

  (2) It has a write-only area and a read-only memory space.

  (3) The write / read (WRITE / READ) address conversion mechanism converts the address of the write access to the write-only area and the read access to the read-only area into the address of the internal memory.

  (4) A write / read (WRITE / READ) address conversion mechanism is provided, and address conversion can be set according to information in a setting register.

  (5) The read (READ) address conversion mechanism makes a read wait for the access when a read is requested for a page that has not been written yet.

  (6) Write (WRITE) When a write request is made for data (page) that has not yet been read, the address conversion mechanism causes the access to wait for writing.

  The data processing apparatus 10A of the first embodiment uses the external memory 18, the DMAC 13, the ACC 14, and the like, but any module that can perform writing to and reading from the write / read address conversion mechanism of the internal memory. There is no need to be limited to these. For example, the same operation is established even when the CPU reads data. The same applies to other embodiments described below.

  FIG. 9 is a diagram illustrating a configuration of the data processing device 10B according to the second embodiment and a data access path. The data processing device 10B of the second embodiment is an example in which the processing speed at which the accelerator (ACC) 14 processes data is faster than the speed at which the DMAC 13 transfers data. In such a case, the ACC 14 always waits for the data transferred by the DMAC 13, and the processing efficiency of the ACC 14 decreases. Therefore, in the data processing device 10B of the second embodiment, a plurality of DACs are used to increase the data transfer rate by the DMAC.

  As shown in FIG. 9, the data processing apparatus 10B of the second embodiment has a first DMAC 13A and a second DMAC 13B, and the two first and second external memories 18A are connected to the first embodiment. Different. The internal memory 20B of the data processing device 10B of the second embodiment is also different from the internal memory 20A of the data processing device 10A of the first embodiment, but the other parts are the same. In the second embodiment, two DMACs are provided and two external memories are connected. However, three or more can be used.

  The external memories 18A and 18B store data processed by the ACC 14 in units of pages. For example, the external memory 18A stores odd-numbered page data, and the external memory 18B stores even-numbered page data. .

  FIG. 10 is a diagram showing a configuration of the internal memory 20B in the second embodiment.

  As shown in FIG. 10, the internal memory 20B has a first write address conversion mechanism 22A and a second write address conversion mechanism 22B. Unlike the internal memory 20A of the first embodiment, the other parts are the first implementation. The form is the same. The first write address conversion mechanism 22A and the second write address conversion mechanism 22B can access the page areas 31A to 31D independently. The first write address conversion mechanism 22A and the second write address conversion mechanism 22B include a base address register 44 and a stride amount register 45 in addition to the internal memory capacity register 42 and the page capacity register 43. The base address register 44 stores an address value that designates where to start writing from the top of the internal memory core 21 when data input to each address conversion mechanism is stored in the internal memory core 21. The stride amount register 45 stores the sum of page capacities of all write address translation mechanisms other than itself. From this sum value, it is possible to obtain the offset of the write start address for the next page.

  FIG. 11 shows that in the internal memory 20B of the second embodiment, the first and second DMACs 13A and 13B write the data of the first and second external memories 18A and 18B to the internal memory 20B via the memory controller 16, and the ACC 14 It is a figure explaining the access operation which reads the data transferred to the internal memory 20B.

  As described above, it is assumed that the first external memory 18A stores odd-numbered page data, and the second external memory 18B stores even-numbered page data.

  First, the first DMAC 13A reads the data of the first page stored in the first external memory 18A via the memory controller 16, and transfers it to the first write address conversion mechanism 22A of the internal memory 20B. The first write address conversion mechanism 22A is based on the write address from the first DMAC 13A, the value of the internal memory capacity register 42, the value of the page capacity register 43, the value of the base address register 44, the value of the stride amount register 45, and the status flag. Then, address conversion is performed to convert to an internal memory write address. Further, the write address conversion mechanism 22 determines the corresponding page area in the internal memory core 21 from the internal memory write address, checks the status flag of the page, and waits until it becomes possible if writing is impossible. If writing is possible, write data is written. The first write address conversion mechanism 22 </ b> A outputs a write notification to the state transition control unit 24 when writing to the internal memory core 21. Furthermore, the first write address conversion mechanism 22A outputs a write completion notification to the state transition control unit 24 when writing to the final address of the page. When the state transition control unit 24 receives the write completion notification, the state transition control unit 24 transitions the status flag of the page to “waiting for reading”. In FIG. 11, when the writing of the region 31A of the first page is completed, the corresponding status flag 61A transitions to “Read wait”.

  On the other hand, in parallel with the transfer operation of the first DMAC 13A, the second DMAC 13B reads the second page data stored in the second external memory 18B via the memory controller 16 and performs the second write in the internal memory 20B. Transfer to the address translation mechanism 22B. The second write address translation mechanism 22B performs the same operation as the first write address translation mechanism 22A, and writes the transferred second page data to another page area in the internal memory core 21. When the second write address translation mechanism 22B outputs a write completion notification to the state transition control unit 24, the state transition control unit 24 transitions the status flag of the page to “read (read) wait”.

  Thereafter, the first write address conversion mechanism 22A and the second write address conversion mechanism 22B calculate the write start addresses (page areas) of the third page and the fourth page from the values stored in the stride amount register 45. Then, the first write address conversion mechanism 22A and the second write address conversion mechanism 22B perform the same writing if the page area is “Waiting for writing”, and perform “Reading waiting” or “Reading”. If “Read” is in progress, it waits until “Waiting for Write” is reached.

  On the other hand, when the writing of the data of the first page to the internal memory 20A is completed, the ACC 14 starts the reading operation of the data of the first page from the internal memory 20A via the read address conversion mechanism 23. The read operation by the read address conversion mechanism 23 is the same as that of the first embodiment. When the reading of the first page data stored in the first page area 31A of the internal memory core 21 is completed, the second page area 31B Since the data for the second page is already stored, it is read.

  FIG. 12 is a time chart showing changes in write data and read data in the access operation of the internal memory 20B. This time chart is an operation time chart when the data transfer speed from the external memory 18 to the internal memory 20A by the two DMACs 13A and 13B and the read speed from the internal memory 20A by the ACC 14 are substantially equal. In other words, the ACC 14 can process data transferred by a single DMAC 13A or 13B at a predetermined time in about half the predetermined time.

  In FIG. 12, single-line rectangles in the first page area to the fourth page area indicate writing of transfer data to the internal memory 20B by the first DMAC 13A and the second DMAC 13B. Data reading from 20B is shown.

  As shown in FIG. 12, the data transfer of the first page by the first DMA 13A and the writing of the transferred data to the first page area 31A, the data transfer of the second page by the second DMA 13B and the transfer to the second page area 31B Data is written in parallel.

  When the data transfer of the first page and the second page is completed, the data transfer of the third page and the fourth page by the first DMAC 13A and the second DMAC 13B and the writing to the third page area 31C and the fourth page area 31D are performed.

  On the other hand, immediately after the data transfer and writing of the first page are completed, the data of the first page is read from the first page area 31A by the ACC. When the reading of the first page of data is completed, the reading of the second page of data from the second page region 31B by the ACC 14 is performed.

  When the data transfer and writing of the third page data to the third page area 31C by the first DMAC 13A are completed, the reading of the first page data from the first page area 31A by the ACC 14 is completed. Therefore, data can be written in the first page area 31A, and the first DMAC 13A can perform a new data transfer operation. Therefore, data transfer of the fifth page by the first DMAC 13A and data writing to the first page area 31A are started.

  When the transfer and writing of the fourth page data to the fourth page area 31D by the second DMAC 13B is completed, the reading of the second page data from the second page area 31B by the ACC 14 is not completed. At this time, the first page area 31A has been written with data for the fifth page, and the third and fourth page areas 31C, 31D have not been read with data for the third and fourth pages. Therefore, new data cannot be written. Accordingly, the second DMAC 13B is in an inactive state but cannot transfer data, and therefore waits until the reading of the second page of data from the second page area 31B by the ACC 14 is completed. Then, after the reading of the second page data from the second page area 31B is completed, transfer and writing of the sixth page data to the second page area 31B by the second DMAC 13B is started.

  Thereafter, the first DMAC 13A and the second DMAC 13B are alternately used to wait until reading of the written data is completed and one of the page areas is in a “write wait” state, and “wait for write”. When the state is reached, new data is transferred and written. By repeating such an operation, the ACC 14 can read data stored in the external memory 18 in a different form of access at high speed.

  FIG. 13 is a flowchart showing a process of writing transferred data to the internal memory 20B (page areas 31A to 31D of the internal memory core 21) in the second embodiment.

  In step S31, the first DMAC 13A or the second DMAC 13B issues a write process to the first write address conversion mechanism 22A or the second write address conversion mechanism 22B of the internal memory 20B.

  In step S32, the first write address conversion mechanism 22A or the second write address conversion mechanism 22B calculates an internal memory write address and a write page from the input write address based on the set register information.

  In step S33, the first write address conversion mechanism 22A or the second write address conversion mechanism 22B determines whether the state of the write page that is the data write destination is “Read waiting” (10) or “Reading” (11). Since writing cannot be performed when the writing page is waiting for reading or reading, the process waits until these states are completed, and proceeds to the next step when these states are completed.

  In step S34, the first write address conversion mechanism 22A or the second write address conversion mechanism 22B determines whether the state of the write page is Write wait (00). If it is Write wait (00), the process proceeds to step S35. If not Write wait (00), the process proceeds to step S36.

  In step S35, the state transition control unit 24 causes the state flag of the write page to transition to “being written” (01).

  In step S36, the first write address conversion mechanism 22A or the second write address conversion mechanism 22B writes the transferred data to the internal memory write address of the internal memory core 21.

  In step S37, the first write address conversion mechanism 22A or the second write address conversion mechanism 22B determines whether the internal memory write address is the final address of the write page based on the set register information. If so, the process proceeds to step S38, and if not the final address, the process ends. Thereafter, steps S31 to S37 are repeated for the same written page.

  In step S38, the state transition control unit 24 makes the state flag of the write page transition to Read wait (10), and ends.

  Since the process of reading data from the internal memory 20B (page areas 31A to 31D of the internal memory core 21) by the ACC 14 is the same as that in the first embodiment, the description thereof is omitted.

  FIG. 14 is a diagram illustrating a configuration of the internal memory 20C of the data processing device 10C according to the third embodiment.

  The data processing device 10B of the second embodiment is provided with two write address conversion mechanisms 22A and 22B corresponding to the two DMACs 13A and 13B in the internal memory 20B. However, if the data write speed to the internal memory core 21 by the write address conversion mechanism is sufficiently higher than the data transfer speed by one DMAC, for example, if it is twice or more, the two DMACs 13A and 13B Even if is used, the data transferred by one write address conversion mechanism 22 can be written to the internal memory core 21.

  Similarly to the data processing device 10B of the second embodiment shown in FIG. 9, the data processing device 10C of the third embodiment has two DMACs 13A and 13B, to which two external memories 13A and 13B are connected. The The internal memory 20 has the same configuration as the internal memory 20A of the first embodiment, but the operation speed is high, and the data transferred by the two DMACs 13A and 13B in a predetermined time is transmitted by one write address conversion mechanism 22. It is possible to write to the internal memory core 21 within a predetermined time. Other parts are the same as those in the first and second embodiments.

  As shown in FIG. 14, the internal memory 20C of the data processing apparatus 10C of the third embodiment has the same configuration as the internal memory 20A of the first embodiment, but the write address conversion mechanism 22 has the number of external memories (here 2) address range registers 46A and 46B. Although not shown, the internal memory capacity registers 42 and 52 and the page capacity registers 43 and 53 are provided in the write address conversion mechanism 22 and the read address conversion mechanism 23, respectively, as in the second embodiment. Further, the write address conversion mechanism 22 includes a base address register 44 and a stride amount register 45.

  Address range registers 46A and 46B store the address ranges of external memories 18A and 18B, respectively. The transfer source external memory can be determined from the information related to the write address of the data transferred by the two DMACs 13A and 13B.

  15 shows that in the internal memory 20C of the third embodiment, the first and second DMACs 13A and 13B write the data of the first and second external memories 18A and 18B to the internal memory 20B via the memory controller 16, and the ACC 14 It is a figure explaining the access operation which reads the data transferred to the internal memory 20B.

  As described above, it is assumed that the external memory 18A stores odd-numbered page data, and the external memory 18B stores even-numbered page data.

  The first DMAC 13A and the second DMAC 13B read the data of the first page and the second page stored in the first external memory 18A and the second external memory 18B in parallel through the memory controller 16 while performing bus arbitration. Transfer to the write address conversion mechanism 22 of the memory 20C. The write address conversion mechanism 22 compares the write address of the transferred data with the address range stored in the address range registers 46A and 46B, and specifies the external memory from which the data is transferred. In other words, the write address conversion mechanism 22 determines the page area of the transferred data. Then, the write address conversion mechanism 22 selects a page area to which data is written according to the determined page area. Then, based on the write address, the value of each register, and the status flag, address conversion is performed to convert the address into the internal memory write address, and writing or standby is performed according to the status flag of the write destination page.

  The ACC 14 sequentially reads data from the page area in which writing is completed and “waiting for writing”. Other operations are the same as those in the second embodiment. Therefore, the time chart showing the access operation of the internal memory 20B in the third embodiment is the same as the time chart of the second embodiment shown in FIG.

  FIG. 16 is a flowchart showing a process of writing transferred data to the internal memory 20C (page areas 31A to 31D of the internal memory core 21) in the third embodiment.

  In step S41, the first DMAC 13A and the second DMAC 13B issue a write process to the write address conversion mechanism 22 of the internal memory 20C.

  In step S42, it is determined whether the write address matches the address range information stored in the address range registers 46A and 46B. If they match, the process proceeds to step S44, and if they do not match, the process proceeds to step S43.

  In step S43, since the write address does not match the address range, the transfer-source external memory cannot be confirmed, so another register information is referred to. Since this process is not directly related to the process of the embodiment, the description is omitted.

  In step S44, the write address conversion mechanism 22 calculates an internal memory write address and a write page from the input write address based on the set register information.

  Steps S45 to S50 are the same processes as steps S33 to S38 in FIG.

  FIG. 17 is a diagram illustrating a configuration of the data processing device 10D according to the fourth embodiment and a data access path. The data processing device 10D of the fourth embodiment is an example in which the speed at which the DMAC 13 transfers data is faster than the processing speed at which the accelerator (ACC) 14 processes data. In such a case, the DMAC 13 always waits for data transfer until the ACC 14 processes data, and the transfer efficiency of the DMAC 13 decreases. Therefore, in the data processing device 10D of the fourth embodiment, a plurality of ACCs are used to increase the data processing speed by ACC.

  As shown in FIG. 17, the data processing device 10 </ b> D of the fourth embodiment is different from the first embodiment in having first and second ACCs 14 </ b> A and 14 </ b> B. The internal memory 20D of the data processing device 10D of the fourth embodiment is also different from the internal memory 20A of the data processing device 10A of the first embodiment, but the other parts are the same. In the second embodiment, two ACCs are provided, but three or more ACCs may be provided.

  FIG. 18 is a diagram showing a configuration of the internal memory 20D.

  As shown in FIG. 18, the internal memory 20D has a first read address translation mechanism 23A and a second read address translation mechanism 23B. Unlike the internal memory 20A of the first embodiment, the other parts are the first implementation. The form is the same. The first read address conversion mechanism 23A and the second read address conversion mechanism 23B can independently access the page areas 31A to 31D. The first read address translation mechanism 23A and the second read address translation mechanism 23B have a base address register 54 and a stride amount register 55. Although not shown, the first read address translation mechanism 23A and the second read address translation mechanism 23B have an internal memory capacity register 52 and a page capacity register 53, as in the first embodiment. Further, the write address conversion mechanism 22 has an internal memory capacity register 42 and a page capacity register 43.

  When reading data from the internal memory core 21, the base address register 54 stores an address value that specifies at which position in the internal memory core 21 to start reading. The stride amount register 55 stores the sum of page capacities of all write address translation mechanisms other than itself. From this sum value, it is possible to obtain the offset of the read start address of the next page.

  FIG. 19 shows an access operation in which the DMAC 13 writes data in the external memory 18 to the internal memory 20D via the memory controller 16 and the first ACC 14A and the second ACC 14B read data from the internal memory 20D in the internal memory 20D of the fourth embodiment. FIG.

  The external memory 18 includes data 1-a, 2-a, 3-a, 4-a, 5-a processed by the first ACC 14A and data 1-b, 2-b, 3-b, processed by the second ACC 14B. 4-b and 5-b are stored alternately.

  First, the DMAC 13 sequentially reads data 1-a, 1-b, 2-a, 2-b,... Stored in the external memory 18 via the memory controller 16, and converts the write address of the internal memory 20D. Transfer to mechanism 22. As in the first embodiment, the write address conversion mechanism 22 writes the transferred data in the page areas 31A to 31D in order. At this time, the status flag of each page is checked, and if it is not writable, it waits until it becomes possible, and if it is writable, write data is written.

  When the writing of the first page data 1-a to the internal memory 20D is completed, the first ACC 14A reads the first page data 1-a from the internal memory 20D via the first read address conversion mechanism 23A. To start. The first read address conversion mechanism 23A reads the internal memory based on the read address from the first ACC 14A, the values of the internal memory capacity register and the page capacity register, the value of the base address register 54, the value of the stride amount register 55, and the status flag. Perform address conversion to convert to address. Further, the first read address conversion mechanism 23A determines the corresponding page area in the internal memory core 21 from the internal memory read address, checks the status flag of the page, and waits until it becomes possible if the read is impossible. If data can be read, data is read. When reading data from the internal memory core 21, the first read address conversion mechanism 23 </ b> A outputs a Read notification to the state transition control unit 24. Further, the first read address conversion mechanism 23A outputs a read completion notification to the state transition control unit 24 when reading from the final address of the page. When the state transition control unit 24 receives the Read completion notification, the state transition control unit 24 transitions the status flag of the page to “Waiting for writing”.

  On the other hand, when the writing of the data 1-b of the second page to the internal memory 20D is completed, the second ACC 14B completes the writing of the data 1-b of the second page from the internal memory 20D via the second read address conversion mechanism 23B. Read operation is performed. This read operation is the same as the operation of the first read address conversion mechanism 23A.

  Thereafter, the DMAC 13 sequentially transfers the data of the external memory 18 to the internal memory 20D, and the first ACC 14A and the second ACC 14B read the data from the internal memory 20D in parallel. In FIG. 19, data 1-a is in the first data area 31A, data 1-b is in the second data area 31B, data 2-a is in the third data area 31C, and data 2-b is in the fourth data area 31D. Are stored respectively. The data 3-a, 4-a, 5-a are stored in the first data area 31A, the third data area 31C, and the first data area 31A, respectively, and the data 3-b, 4-b, 5-b are stored. Are stored in the second data area 31B, the fourth data area 31D, and the second data area 31B, respectively. The first ACC 14A alternately reads data from the first data area 31A and the third data area 31C, and acquires and processes data 1-a, 2-a, 3-a, 4-a, and 5-a. The second ACC 14B alternately reads data from the second data area 31B and the fourth data area 31D, and acquires and processes data 1-b, 2-b, 3-b, 4-b, 5-b.

  FIG. 20 is a time chart showing changes in write data and read data in the access operation of the internal memory 20D. This time chart is an operation time chart when the data transfer speed from the external memory 18 to the internal memory 20D by one DMAC 13 and the read speed from the internal memory 20D by the two ACCs 14A and ACC14B are substantially equal. In other words, one DMAC 13 transfers data to be processed by the ACC 14 at a predetermined time in about half the predetermined time.

  In FIG. 20, a single-line rectangle in the first page area to the fourth page area indicates writing of transfer data to the internal memory 20D by the DMAC 13, and a double-line square at both ends indicates the internal memory by the first ACC 14A and the second ACC 14B. Data reading from 20D is shown.

  As shown in FIG. 20, data transfer by the DMAC 13 is performed in page order, and data reading by the first ACC 14A and the second ACC 14B is partially performed in parallel.

  When the transfer and writing of the data 1-a on the first page is completed, the DMAC 13 starts transferring and writing the data 1-b on the second page. On the other hand, when the transfer and writing of the data 1-a for the first page are completed, the first ACC 14A immediately starts reading the data 1-a. At this time, transfer and writing of the data 1-b of the second page are performed in parallel. When the transfer and writing of the data 1-b on the second page are completed, the DMAC 13 starts transferring and writing the data 2-a on the third page, and the second ACC 14B starts reading the data 1-b. . At this time, the first ACC 14A is still reading the data 1-a. Thereafter, the data 2-a on and after the fourth page is written and read.

  When the transfer and writing of the data 2-b of the fourth page by the DMAC 13 are completed, the data 1-a written in the first page area 31A has already been read by the first ACC 14A and is “waiting for writing”. The DMAC 13 starts to transfer and write the data 3-a of the fifth page to the first page area 31A.

  Thereafter, the first ACC 14A and the second ACC 14B are alternately used to wait until data writing is completed and one of the page areas is in a “read (read)” state, and then in a “read” state. Then, new data is read out. By repeating such an operation, the first ACC 14A and the second ACC 14B can process at high speed data stored in different forms stored in the external memory 18.

  The process of writing the transferred data to the internal memory 20D (page areas 31A to 31D of the internal memory core 21) in the fourth embodiment is the same as in the first embodiment.

  FIG. 21 is a flowchart showing a process of reading data from the internal memory 20D (page areas 31A to 31D of the internal memory core 21) by the first ACC 14A and the second ACC 14B in the fourth embodiment.

  In step S51, the first ACC 14A or the second ACC 14B issues a read process to the first read address conversion mechanism 23A or the second read address conversion mechanism 23B of the internal memory 20D.

  In step S52, the first read address translation mechanism 23A or the second read address translation mechanism 23B is based on the values of the internal memory capacity register and the page capacity register, the value of the base address register 54, the value of the stride amount register 55, and the status flag. Thus, the internal memory read address and the read page are calculated as the read address.

  In step S53, the first read address translation mechanism 23A or the second read address translation mechanism 23B determines whether the status of the read page is Write wait (010) or Write in progress (01). Since reading cannot be performed when the read page is waiting for writing or writing, the process waits until these states are completed, and proceeds to the next step when these states are completed.

  In step S54, the first read address translation mechanism 23A or the second read address translation mechanism 23B determines whether the status of the read page is Wait for Read (10), and if it is Wait for Read (10), the process proceeds to Step S55. If it is not Read waiting (10), the process proceeds to step S56.

  In step S55, the state transition control unit 24 changes the state flag of the read page to “Reading” (11).

  In step S56, the first read address conversion mechanism 23A or the second read address conversion mechanism 23B reads data from the internal memory read address of the internal memory core 21.

  In step S57, the first read address conversion mechanism 23A or the second read address conversion mechanism 23B determines whether the internal memory read address is the final address of the read page based on the set register information. If so, the process proceeds to step S58, and if not the final address, the process ends. Thereafter, steps S51 to S57 are repeated for the same read page.

  In step S58, the state transition control unit 24 changes the status flag of the read page to write wait (00), and the process ends.

  FIG. 22 is a diagram illustrating a configuration of the internal memory 20E of the data processing device 10E according to the fifth embodiment.

  In the data processing device 10D of the fourth embodiment, two read address conversion mechanisms 23A and 23B are provided in the internal memory 20D corresponding to the two ACCs 14A and 14B. However, if the read speed of the data from the internal memory core 21 by the read address conversion mechanism is sufficiently higher than the data processing speed by one ACC, for example, if it is twice or more, the two ACCs 14A and 14B Even when using, data can be read from the internal memory core 21 by one read address conversion mechanism 23.

  Similarly to the data processing device 10B of the fourth embodiment shown in FIG. 17, the data processing device 10E of the fifth embodiment has two ACCs 14A and 14B. The internal memory 20E has a high operating speed and can read data processed by the two ACCs 14A and 14B in a predetermined time from the internal memory core 21 by the single read address conversion mechanism 23 within a predetermined time. Other parts are the same as those in the first and fourth embodiments.

  As shown in FIG. 22, the internal memory 20E of the data processing device 1EC of the fifth embodiment has the same configuration as the internal memory 20A of the first embodiment, but the read address conversion mechanism 23 has the number of ACCs (here, 2) address range registers 56A and 56B. Although not shown, the internal memory capacity registers 42 and 52 and the page capacity registers 43 and 53 are provided in the write address conversion mechanism 22 and the read address conversion mechanism 23, respectively, as in the fourth embodiment. Further, the read address conversion mechanism 23 includes a base address register 54 and a stride amount register 55.

  Address range registers 56A and 56B store the address ranges of first ACC 18A and second ACC 18B, respectively. The ACC of the data request source can be determined from the information regarding the read addresses from the two first ACCs 18A and the second ACCs 18B.

  In FIG. 23, in the internal memory 20E of the fifth embodiment, the DMAC 13 writes the data of the external memory 18 to the internal memory 20E via the memory controller 16, and the first ACC 14A and the second ACC 14B transfer the data transferred to the internal memory 20E. It is a figure explaining the access operation to read.

  As described above, the external memory 18 includes the data 1-a, 2-a, 3-a, 4-a, 5-a processed by the first ACC 14A and the data 1-b, 2-b processed by the second ACC 14B. , 3-b, 4-b, 5-b are stored alternately.

  First, the DMAC 13 sequentially reads data 1-a, 1-b, 2-a, 2-b,... Stored in the external memory 18 via the memory controller 16 and converts the write address of the internal memory 20E. Transfer to mechanism 22. As in the first embodiment, the write address conversion mechanism 22 writes the transferred data in the page areas 31A to 31D in order. At this time, the status flag of each page is checked, and if it is not writable, it waits until it becomes possible, and if it is writable, write data is written.

  The first ACC 14A or the second ACC 14B outputs a read address to the read address conversion mechanism 23. The read address conversion mechanism 23 compares the read address with the address ranges stored in the address range registers 56A and 56B, and identifies the ACC that requested the data. In other words, the read address translation mechanism 23 determines the page area of the requested data. Then, the read address conversion mechanism 23 selects a page area from which data is read according to the determined page area. Then, based on the read address, the value of each register, and the status flag, address conversion is performed for conversion to an internal memory read address, and reading or waiting is performed according to the status flag of the read page.

  The read data is output to the first ACC 14A or the second ACC 14B. Other operations are the same as those in the fourth embodiment. Therefore, the time chart showing the access operation of the internal memory 20E in the fifth embodiment is the same as the time chart of the fourth embodiment shown in FIG.

  FIG. 24 is a flowchart showing a process of reading data from the internal memory 20E (page areas 31A to 31D of the internal memory core 21) by the first ACC 14A and the second ACC 14B in the fifth embodiment.

  In step S61, the first ACC 14A or the second ACC 14B issues a read process to the first read address conversion mechanism 23A or the second read address conversion mechanism 23B of the internal memory 20D.

  In step S62, it is determined whether the read address matches the address range information stored in the address range registers 56A and 56B. If they match, the process proceeds to step S64, and if they do not match, the process proceeds to step S63.

  In step S63, since the read address and the address range do not match, the request source ACC cannot be confirmed, so another register information is referred to. Since this process is not directly related to the process of the embodiment, the description is omitted.

  In step S64, the read address conversion mechanism 23 calculates an internal memory read address and a read page from the input read address based on the set register information.

  Steps S65 to S51 are the same processes as steps S53 to S58 in FIG.

  In the first and fifth embodiments, the data in each page area is read to the end and output to the ACC. The state transition control unit 24 changes each page area from which data has been read to the end to “Waiting for Write (00)”. However, in the ACC process, there is a case where the process is completed with the data up to the middle of each page area and it is not necessary to read the data to the end. In such a case, there may be a deadlock that new data cannot be written to the internal memory. The occurrence of this deadlock will be described using the fourth embodiment as an example.

  FIG. 25 is a diagram illustrating the occurrence of deadlock in the fourth embodiment, and corresponds to the time chart of FIG.

  In FIG. 25, consider a case where the first ACC 14A reads the data 3-a stored in the first memory area 31A, but only requires halfway data. In this case, since the first ACC 14A does not read until the end of the data 3-a, the status flag of the first memory area 31A does not become “Waiting for writing (00)”, but is “Reading” (11 ) ”. After the transfer and writing of the data 4-b to the fourth memory area 31D by the DMAC 13 is completed, the DMAC 13 transfers and writes the data 5-a to the first memory area 31A. The first memory area 31A is “Reading (11)” and the DMAC 13 waits, but the first memory area 31A does not become “Write wait (00)”. Therefore, the standby state will continue. Therefore, the data 5-a and 5-b are not transferred and written to the internal memory 20D, and a deadlock occurs. In the data processing apparatus according to the sixth embodiment described below, the occurrence of deadlock is prevented.

  FIG. 26 is a diagram illustrating a configuration of the data processing device 10F according to the sixth embodiment and a data access path. The data processing device 10F of the sixth embodiment includes first and second DMACs 13A and 13B, and first and second ACCs 14A and 14B, and two first and second external memories 18A are connected.

  FIG. 27 is a diagram showing the configuration of the internal memory 20F.

  As shown in FIG. 27, the internal memory 20F of the data processing device 10F according to the sixth embodiment includes two write address conversion mechanisms 22A and 22B and two read address conversion mechanisms 23A and 23B. The two write address translation mechanisms 22A and 22B have address range registers 46A and 46B, and the two read address translation mechanisms 23A and 23B have address range registers 56A and 56B. In other words, the internal memory 20F of the data processing device 10F according to the sixth embodiment has a configuration in which the third embodiment and the fifth embodiment are combined.

  Furthermore, the data processing apparatus according to the sixth embodiment adds “ACC processing completion (100)” to the status flag for each page of the state transition control unit 24 of the internal memory 20F. Different from processing equipment.

  The first ACC 14A and the second ACC 14B notify the first read address conversion mechanism 23A and the second read address conversion mechanism 23B of “ACC processing completion” when the processing is completed, including the case where the data processing is completed in the middle of the page. To do. In response to this, the first read address translation mechanism 23A and the second read address translation mechanism 23B notify the state transition control unit 24 of “ACC processing completion”, and the state transition control unit 24 displays the status flag of the corresponding page. Change to “ACC processing complete”.

  FIG. 28 is a diagram illustrating changes in the status flags of each page in the sixth embodiment. In the four states shown in FIG. 6, writing (00), writing (01), reading (10) and reading (11), “ACC processing complete” (100) ”is added. “ACC processing complete (100)” can transition from any of the four states. In addition, there may be a transition from waiting for reading (10) to waiting for writing (00).

  FIG. 29 is a flowchart showing a process of writing transferred data to the internal memory 20F (page areas 31A to 31D of the internal memory core 21) in the sixth embodiment.

  In step S71, the DMAC 13 issues a write process to the write address conversion mechanism 22 of the internal memory 20F.

  In step S72, it is determined whether the write address matches the address range information stored in the address range registers 46A and 46B. If they match, the process proceeds to step S74, and if not, the process proceeds to step S73.

  In step S73, since the write address and the address range do not match, the transfer source external memory cannot be confirmed, so another register information is referred to.

  In step S74, the write address conversion mechanism 22 calculates an internal memory write address and a write page from the input write address based on the set register information.

  In step S75, it is determined whether or not the status flag is “ACC process complete (100)”. If “ACC process complete (100)”, the process proceeds to step S76. Proceed to S77.

  In step S76, data is transferred from the external memory, but the process ends without writing to the internal memory 20F.

  Steps S77 to S82 are the same processing as steps S33 to S38 in FIG.

  FIG. 30 is a flowchart showing a process of reading data from the internal memory 20F (page areas 31A to 31D of the internal memory core 21) by the first ACC 14A and the second ACC 14B in the sixth embodiment.

  In step S91, the first ACC 14A or the second ACC 14B issues a read process to the first read address translation mechanism 23A or the second read address translation mechanism 23B of the internal memory 20D.

  In step S92, it is determined whether the read address matches the address range information stored in the address range registers 56A and 56B. If they match, the process proceeds to step S94, and if they do not match, the process proceeds to step S93.

  In step S93, since the read address does not match the address range, the request source ACC cannot be confirmed, so another register information is referred to. Since this process is not directly related to the process of the embodiment, the description is omitted.

  In step S94, the read address conversion mechanism 23 calculates an internal memory read address and a read page from the input read address based on the set register information.

  In step S95, it is determined whether the calculated read page is different from the page read in the immediately preceding process. If they are different, the process proceeds to step S96, and if they are the same, the process proceeds to step S97.

  In step 96, the status flag from the page held in the internal memory 20F to the page immediately before the calculated read page is changed to “Waiting for write (00)”, and the process proceeds to step S97.

  Steps S97 to S102 are the same processing as steps S53 to S58 in FIG.

  In step S103, the internal memory read address and information related to the read page in the process performed by the read address conversion mechanism 23 are stored in the memory, and the process is terminated.

  FIG. 31 is a flowchart illustrating a process performed when the read process by the first ACC 14A and the second ACC 14B is completed in the sixth embodiment.

  In step S110, the first ACC 14A or the second ACC 14B notifies the completion of the process.

  In step S111, the read control unit 51 confirms which ACC has completed the process.

  In step S112, the page that has been processed is determined based on the register information of the ACC that has completed the process.

  In step S113, the status flag status of the determined page is changed to “ACC processing complete (100)”.

  In step S114, it is determined whether or not the state transition of all pages has been performed in consideration of the case where the completed ACC has performed processing for a plurality of pages. If pages remain, the process returns to step S112, and pages remain. If not, exit.

  In the ACC process, it is possible that the data of consecutive pages is not processed continuously and the data of intermediate pages is not used. In such a case, since data transfer and writing from the external memory to the internal memory by the DMAC are performed in continuous pages, the data is not read from the page in which the data is written, and page skipping occurs. . In the first to fifth embodiments, the page area of the internal memory core 21 is shifted to “Waiting for writing (00)” after data is read, but when page skipping occurs, Since no data is read out, “Read (waiting for read) (10)” is maintained. Therefore, a deadlock that new data cannot be written to the internal memory may occur. In the data processing apparatus according to the seventh embodiment, even when page skipping occurs, deadlock does not occur.

  FIG. 32 is a diagram showing a configuration of the internal memory 20G.

  As shown in FIG. 32, the internal memory 20G of the data processing device 10G of the seventh embodiment is different from the first embodiment in that the read address conversion mechanism 23 has a previous address register 57. The same as in the first embodiment.

  FIG. 33 is a diagram illustrating changes in the status flag of each page in the seventh embodiment. As in the case of the first embodiment shown in FIG. 6, writing (00), writing (01), reading (10) and reading (11) are in progress (11). There are four states. However, it is different from the first embodiment that a transition from “Read wait (10)” to “Write wait (00)” can occur. The transition from “Read wait (10)” to “Write wait (00)” occurs when a page is straddled without being read.

  FIG. 34 is a time chart showing changes in write data and read data in the access operation of the internal memory 20G in the seventh embodiment, and corresponds to FIG. Since the basic operation is the same as that of the first embodiment, the description is omitted.

  As shown in FIG. 34, the DMAC 13 performs data transfer for the third page and data writing to the first page area 31A, and further performs data transfer for the fourth page and data writing to the second page area 31B. Is called. Normally, the ACC 14 finishes reading the second page data written in the second page area 31B, and then writes the third page data written in the first page area 31A and the second page area 31B. Read data on page 4. However, in the example of FIG. 34, the data on the third page and the fourth page are skipped. Therefore, after the DMAC 13 performs the data transfer of the fourth page and the data writing to the second page area 31B, the data transfer of the fifth page and the sixth page and the first page area 31A and the second page area 31B. The data is written. However, the first page area 31A and the second page area 31B are “read waiting (10)” and data cannot be written. Therefore, if a process that spans pages to which a subsequent page is written without being read (read) is performed for each page area, the page area is changed from “Read wait (10)” to “Write wait”. (00) ". Thereby, the data transfer of the fifth page and the sixth page and the writing of the data to the first page area 31A and the second page area 31B are performed, and the same processing as in the first embodiment is performed thereafter.

  FIG. 35 is a flowchart showing a process of reading data from the internal memory 20G (page areas 31A to 31D of the internal memory core 21) by the ACC 14.

  In step S121, the ACC 14 issues a read process to the read address conversion mechanism 23 in the internal memory 20G.

  In step S122, the read address conversion mechanism 23 calculates an internal memory read address and a read page from the input read address based on the set register information.

  In step 123, the read address conversion mechanism 23 determines whether the calculated read page is different from the page corresponding to the previous internal memory read address stored in the previous address register 57. If they are different, the process proceeds to step S124. If so, the process proceeds to step S125.

  In step S124, among the data of the page written and held in the internal memory, the status flag up to the page immediately before the calculated read page is changed to “Waiting for write (00)”, and step S125. Proceed to

  Steps S125 to S130 are the same processing as steps S53 to S58 in FIG.

  In step S131, the information related to the internal memory read address and the read page in the processing performed by the read address conversion mechanism 23 is stored in the memory, and the process ends.

  The first to seventh embodiments have been described above, but various modifications are possible. For example, the configurations described in the first to seventh embodiments can be appropriately combined.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
CPU,
A master operating module;
An internal memory accessible directly from the master operating module;
A data transfer unit that accesses an external memory that is not directly accessible from the master operation module, and that transfers data stored in the external memory to the internal memory; and
The internal memory is
Two or more page storage areas logically divided in units of pages;
A write address conversion unit that converts the data transferred from the external memory by the data transfer unit into an address of the internal memory and writes the address to the two or more page storage areas;
A read address conversion unit that converts a read address of the master operation module into an address of the internal memory in accordance with a read operation of the master operation module, and reads data stored in the two or more page storage areas;
A state transition control unit having a state flag corresponding to each of the two or more page storage areas,
The read address conversion unit performs a read operation on the page storage area where writing by the write address conversion unit is performed, and the write address conversion unit performs read operation on the page storage area where the read operation by the read address conversion unit is completed. And a data processing apparatus that controls to perform a writing operation. (1) (Figs. 2-9)
(Appendix 2)
The internal memory is
An internal memory capacity register for storing a value defining the capacity of the internal memory;
A page capacity register for storing a value defining the size of the page storage area,
The data processing device according to appendix 1, wherein values of the internal memory capacity register and the page capacity register can be arbitrarily set.
(Appendix 3)
The data transfer unit includes a plurality of data transfer units that transfer data in parallel from the plurality of external memories,
The data processing apparatus according to appendix 1 or 2, wherein the write address conversion unit includes a plurality of write address conversion mechanisms corresponding to the plurality of data transfer units. (2) (FIGS. 9 and 10)
(Appendix 4)
Each write address translation mechanism
A base address register for storing start address information of data writing to the internal memory;
The data processing apparatus according to appendix 3, further comprising: a stride amount register that stores a change amount when a page storage area to which data is written changes.
(Appendix 5)
The data transfer unit includes a plurality of data transfer units that transfer data in parallel from the plurality of external memories,
The write address conversion unit includes a plurality of address range registers corresponding to the plurality of data transfer units,
Each address range register stores an address range of the external memory to which data is transferred by a corresponding data transfer unit,
The data processing device according to appendix 1 or 2, wherein the write address conversion unit specifies the external memory from the address range. (3) (FIGS. 14-16)
(Appendix 6)
The master operation module includes a plurality of master operation units that read data in parallel from the internal memory,
The data processing device according to any one of appendices 1 to 5, wherein the read address conversion unit includes a plurality of read address conversion mechanisms corresponding to the plurality of master operating units. (4) (FIGS. 17 to 21)
(Appendix 7)
Each read address translation mechanism
A base address register for storing start address information of data reading from the internal memory;
The data processing apparatus according to appendix 6, further comprising: a stride amount register that stores a change amount when a page storage area from which data is read is changed.
(Appendix 8)
The master operation module includes a plurality of master operation units that read data in parallel from the internal memory,
The read address conversion unit includes a plurality of address range registers corresponding to the plurality of master operating units,
Each address range register stores the address range of the corresponding master actuator,
The data processing device according to any one of appendices 1 to 5, wherein the read address conversion unit identifies the master operating unit from the address range.
(Appendix 9)
When the master operation module finishes reading the data from the internal memory, the master operation module notifies the read address conversion unit of the completion of reading,
When the master operation module detects that the master operation module has accessed a page after the page storage area notified of the read completion, the read address conversion unit waits for writing the page storage area notified of the read completion. 9. The data processing device according to any one of appendices 1 to 8, wherein the data processing device is changed to a state.
(Appendix 10)
The read address conversion unit includes a previous address register for storing address information accessed by the master operation module last time,
The address information accessed last time is compared with the read address by the master operation module, and the master operation module skips the page that accesses the next page without reading the data written in the internal memory. The data processing apparatus according to claim 1, wherein when the data is detected, the page skipped is shifted to a state of waiting for writing. (5) (FIGS. 32-35)

10 10A Data processing device (SoC)
11 Bus 12 CPU
13 DMAC
13 Power supply control unit (PMU)
14 Accelerator (ACC)
16 memory controller 17 control memory 18 external memory 20A internal memory 21 internal memory core 22 write address conversion mechanism 23 read address conversion mechanism 24 state transition control unit 31A-31D page area 41 write operation control unit 51 read operation control unit 61A-61D Status flag

Claims (5)

CPU,
A master operating module;
An internal memory accessible directly from the master operating module;
A data transfer unit that accesses an external memory that is not directly accessible from the master operation module, and that transfers data stored in the external memory to the internal memory; and
The internal memory is
Two or more page storage areas logically divided in units of pages;
A write address conversion unit that converts the data transferred from the external memory by the data transfer unit into an address of the internal memory and writes the address to the two or more page storage areas;
A read address conversion unit that converts a read address of the master operation module into an address of the internal memory in accordance with a read operation of the master operation module, and reads data stored in the two or more page storage areas;
A state transition control unit having a state flag corresponding to each of the two or more page storage areas,
The read address conversion unit performs a read operation on the page storage area where writing by the write address conversion unit is performed, and the write address conversion unit performs read operation on the page storage area where the read operation by the read address conversion unit is completed. And a data processing apparatus that controls to perform a writing operation. The data transfer unit includes a plurality of data transfer units that transfer data in parallel from the plurality of external memories,
The data processing apparatus according to claim 1, wherein the write address conversion unit includes a plurality of write address conversion mechanisms corresponding to the plurality of data transfer units. The data transfer unit includes a plurality of data transfer units that transfer data in parallel from the plurality of external memories,
The write address conversion unit includes a plurality of address range registers corresponding to the plurality of data transfer units,
Each address range register stores an address range of the external memory to which data is transferred by a corresponding data transfer unit,
The data processing apparatus according to claim 1, wherein the write address conversion unit specifies the external memory from the address range. The master operation module includes a plurality of master operation units that read data in parallel from the internal memory,
The data processing apparatus according to claim 1, wherein the read address conversion unit includes a plurality of read address conversion mechanisms corresponding to the plurality of master operating units. The read address conversion unit includes a previous address register for storing address information accessed by the master operation module last time,
The address information accessed last time is compared with the read address by the master operation module, and the master operation module skips the page that accesses the next page without reading the data written in the internal memory. 5. The data processing apparatus according to claim 1, wherein when the data is detected, the page skipped is shifted to a write wait state.

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