JP2011013739A - Constant-voltage power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant-voltage power supply circuit outputting a low voltage.SOLUTION: The constant-voltage power supply circuit includes an output transistor receiving a voltage from an external power source, and outputting a first voltage; a feedback circuit outputting the first voltage or a voltage, obtained by dividing the first voltage as a second voltage; a first reference voltage generation circuit generating a third voltage; and an error amplifier circuit. The error amplifier circuit includes a first differential amplifier circuit, including two transistors with a common terminal connected to the ground and performing amplification and generating constant currents and controls the output transistor, by amplifying the error of the second voltage with respect to the third voltage.

Description

  The present invention relates to a constant voltage power supply circuit.

In recent years, the demand for power supply circuits has been advanced with the advancement of functions of electronic devices. For example, mobile communication devices and the like are required to improve ripple removal characteristics and reduce noise characteristics. Therefore, a constant voltage power supply circuit having a multi-stage differential amplifier circuit is used.
Further, with higher integration and lower power consumption, the constant voltage power supply circuit is required to have a lower voltage (for example, see Patent Document 1).

JP 2007-219856 A

However, if a multi-stage differential amplifier circuit is operated at a low voltage, it becomes unstable or the current flowing through the amplifier circuit decreases, resulting in degraded response characteristics, offset voltage (difference voltage between the reference voltage and comparison voltage) Cause an increase in dispersion. The deterioration of the response characteristics makes the output voltage unstable with respect to the load fluctuation, and the increase in the offset voltage variation causes the problem that the accuracy of the output voltage is deteriorated.
The present invention provides a constant voltage power supply circuit capable of outputting a low voltage.

  According to one embodiment of the present invention, an output transistor that inputs a voltage from an external power supply and outputs a first voltage, and a first voltage or a voltage obtained by dividing the first voltage is a second voltage A first differential circuit that includes a feedback circuit that outputs a voltage, a first reference voltage generation circuit that generates a third voltage, and two transistors whose common terminals are connected to the ground, and that generates amplification and constant current There is provided an error amplification circuit that includes an amplification circuit and amplifies an error of the second voltage with respect to the third voltage to control the output transistor. .

  According to the present invention, a constant voltage power supply circuit capable of outputting a low voltage is provided.

1 is a circuit diagram illustrating a configuration of a constant voltage power supply circuit according to an embodiment of the invention. It is a circuit diagram of the differential amplifier circuit of a comparative example. It is a circuit diagram which illustrates the composition of the differential amplifier circuit of this example. FIG. 6 is a circuit diagram illustrating another configuration of the constant voltage power supply circuit according to the embodiment of the invention. FIG. 6 is a circuit diagram illustrating another configuration of the constant voltage power supply circuit according to the embodiment of the invention.

Embodiments of the present invention will be described below with reference to the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the specification of the present application, high potential and low potential (high voltage and low voltage) are high potential and low potential (high voltage and low voltage), which are absolute values of the potential (voltage), respectively.

FIG. 1 is a circuit diagram illustrating the configuration of a constant voltage power supply circuit according to an embodiment of the invention.
As shown in FIG. 1, the constant voltage power supply circuit 60 a of this embodiment includes a first reference voltage generation circuit 10, an error amplification circuit 30 a, an output transistor 40, and a feedback circuit 50.

  The output transistor 40 receives a voltage from the external power supply VDD and outputs a first voltage to the output terminal VOUT. In this embodiment, a configuration using an enhancement P-type MOSFET as the output transistor 40 is illustrated, but an N-type MOSFET or a bipolar transistor may be used.

  The feedback circuit 50 outputs the first voltage or a voltage obtained by dividing the first voltage as the second voltage. In this embodiment, the feedback circuit 50 includes resistors R51 and R52 connected between the output terminal VOUT and the ground GND. A second voltage obtained by dividing the first voltage is output by using the connection point between the resistors R51 and R52 as the output terminal VFB.

  The feedback circuit 50 further includes a capacitor C51 and a resistor R53, and performs phase compensation to stabilize negative feedback applied to the error amplifier circuit 30a and the output transistor 40. In this embodiment, the phase compensation circuit is provided in the feedback circuit 50. However, another type of phase compensation circuit may be provided in the error amplifier circuit 30a or the like to achieve stability. .

  The first reference voltage generation circuit 10 receives a voltage from the external power supply VDD and outputs a third voltage to the output terminal VB. In this embodiment, the first reference voltage generation circuit 10 includes a depletion N-type first transistor MD11 having a gate connected to the source, and an enhancement having a gate and a drain connected to the source of the first transistor MD11. And an N-type second transistor MN11.

  The drain of the first transistor MD11 is connected to the power supply VDD on the high potential side via the transistor MD12, and the source of the second transistor MN11 is connected to the ground GND on the low potential side. The third voltage is output using the source of the first transistor MD11 as the output terminal VB.

  The transistor MD12 is inserted to limit the currents of the first and second transistors MD11 and MN11. It may not be necessary depending on the voltage of the power supply VDD and the current flowing through the first and second transistors MD11 and MN11, and a plurality of transistors may be connected in series.

  The error amplifier circuit 30 a includes a first differential amplifier circuit 31. In the present embodiment, the first differential amplifier circuit 31 is a differential amplifier circuit having two enhancement N-type transistors MN31 and MN32, and a common terminal thereof is connected to the ground GND. That is, the sources of the transistors MN31 and MN32 are connected in common and connected to the ground GND. Thereby, as will be described later with reference to FIG. 3A, the first differential amplifier circuit 31 plays the role of amplification and constant current generation at the same time.

  Further, the error amplifier circuit 30a has a two-stage configuration including a first-stage amplifier circuit 36a and a second-stage amplifier circuit 38a. The first-stage amplifier circuit 36a includes the first differential amplifier circuit 31 as described above, and uses a current mirror formed of enhancement P-type transistors MP31 and MP32 as a load.

  The second-stage amplifier circuit 38a has a complementary configuration of an enhancement P-type transistor MP39 and an N-type transistor MN38. The signal input to the gate of the transistor MP39 is output to the output transistor 40 from the drains of the transistors MP39 and MN38 connected to each other.

  In this embodiment, the error amplifying circuit 30a has a two-stage configuration, and the output transistor 40 as a whole is a three-stage amplifying circuit. However, the present invention is not limited to this, and the error amplifying circuit 30a can be configured with one or more stages and an arbitrary number of stages. Further, the second stage amplifier circuit 38a may not be provided.

The gates of the transistors MN31 and MN32 serving as input terminals of the error amplifier circuit 30a are connected to the output terminals VB and VFB, respectively, and the third voltage and the second voltage are input thereto.
The error amplification circuit 30a amplifies the error of the second voltage with respect to the third voltage and outputs it to the output transistor 40 as described above. The output of the output transistor 40, that is, the first voltage is controlled to be constant.

In order to reduce (lower) the first voltage, it is necessary to decrease the resistance R51 of the feedback circuit 50 and increase the feedback rate (= (R52 / (R51 + R52)). By reducing the voltage of 3, the first voltage can be reduced.
As will be described later with reference to FIG. 3A, according to the constant voltage power supply circuit 60 a of the present embodiment, the third voltage is compared with the conventional example by using the first differential amplifier circuit 31. It can be set small, and low voltage output is possible.

Here, the operation of the first differential amplifier circuit 31 will be described in detail.
FIG. 2 is a circuit diagram of a differential amplifier circuit of a comparative example.
2A is a circuit diagram of a differential amplifier circuit used as an amplifier circuit, and FIG. 2B is a circuit diagram when the differential amplifier circuit is used as an error amplifier circuit of a constant voltage power source. Represents each.

  As shown in FIG. 2A, the differential amplifier circuit 136 has a differential pair composed of two transistors MN131 and MN132, and uses a current mirror composed of two transistors MP131 and MP132 as a load. The sources of the transistors MN131 and MN132, which are common terminals of the differential amplifier circuit 136, are connected to the ground GND on the low potential side via the transistor MN133.

  The gate of the transistor MN133 is connected to the output terminal VB of a reference voltage generation circuit (not shown), and the transistor MN133 operates as a constant current source. The transistors MN131 and MN132 are driven with a constant current by the transistor MN133. The gates of the transistors MN131 and MN132 are connected to the two signal sources VI1 and VI2, and signals are input to the respective gates.

  In the differential amplifier circuit 136 used as the amplifier circuit, it is necessary that the potential of the input signal be in a wide range from the high potential of the power supply VDD to the low potential of the ground GND. In order to increase the common-mode rejection ratio (CMRR) for this wide range of inputs, the sources of the common-terminal transistors MN131 and MN132 are driven with a constant current.

By the way, when the differential amplifier circuit 136 of the comparative example is used as an error amplifier circuit of a constant voltage power supply circuit, it can be expressed as a differential amplifier circuit 136a of FIG.
The gate of the transistor MN131, which is one input terminal, is connected to the output terminal VB of a reference voltage generation circuit (not shown). The gate of the transistor MN132, which is the other input terminal, is connected to the signal source VI2. In many cases, an output voltage or a comparison voltage that is a voltage obtained by dividing the output voltage is input to the gate of the transistor MN132.

That is, the reference voltage and the comparison voltage are input to the gates of the transistors MN131 and MN132, respectively.
In order to reduce the output voltage, it is necessary to increase the feedback rate of the feedback circuit 50 as described above. Further, it is necessary to reduce the reference voltage.

  However, in the configuration of the differential amplifier circuit 136a shown in FIG. 2B, when the reference voltage is reduced, the drain-source voltage of the transistor MN133 serving as the constant current source of the differential amplifier circuit 136a is reduced. It falls into the unsaturated region. For this reason, the currents of the transistors MN131 and MN132 constituting the differential amplifier circuit 136a are reduced, causing problems such as deterioration in response characteristics and increase in variations in offset voltage.

  This deterioration of the response characteristic causes an increase in output voltage fluctuation due to load fluctuation or the like, and degrades the stability of the output voltage. Further, an increase in offset voltage variation causes an increase in the difference (offset) voltage variation between the reference voltage and the comparison voltage, thereby increasing the output voltage variation and degrading the accuracy of the output voltage.

Here, the drain-source voltage of the boundary of the non-saturation region and a saturation region of the transistor MN133 that the role of the constant current source Vdssat _133, the drain-source voltage during operation of the transistor MN133 and _{VDS 133.}

In order for the transistor MN133 to operate in the saturation region, a condition of VDS ₁₃₃ ≧ VDsat ₁₃₃ is necessary. This condition is expressed as equation (2) using the drain-source voltage during operation of the transistor MN133 as VDS ₁₃₃ and the equation (1) which is the basic characteristic equation of the MOS transistor.

ただし、Ｉ_Ｄはドレイン電流、μ_ｎは多数キャリア移動度、Ｃ_ＯＸは酸化膜容量、Ｗはゲート幅、Ｌはゲート長、Ｖ_ＧＳはゲート・ソース間電圧、Ｖｔｈは閾値電圧である。また、（１）式においては、チャンネル長変調効果を無視している。

Where _ID is the drain current, μ _n is the majority carrier mobility, C _OX is the oxide film capacitance, W is the gate width, L is the gate length, V _GS is the gate-source voltage, and Vth is the threshold voltage. In the equation (1), the channel length modulation effect is ignored.

ただし、ＶＲＥＦは基準電圧であり、トランジスタＭＮ１３３、ＭＮ１３１のそれぞれのゲート電圧である。また、トランジスタＭＮ１３３、ＭＮ１３１の物理量にそれぞれ１３３、１３１の添え字を付けている。

However, VREF is a reference voltage and is the gate voltage of each of the transistors MN133 and MN131. Subscripts 133 and 131 are added to the physical quantities of the transistors MN133 and MN131, respectively.

From the equation (2), if the reference voltage VREF does not satisfy the condition of the following equation (3), the transistor MN133 falls into a non-saturated region and the current decreases.

Thus, there is a limit in reducing the reference voltage VREF and reducing the output voltage.
On the other hand, there is a limit to reducing the output voltage by reducing the resistance R51 as follows. That is, when the resistance R51 is reduced, the effect of phase compensation using the frequency difference between zero and pole generated by the capacitor C51 and the resistances R53, R52, and R51 is reduced. Further, since the feedback rate (= R52 / (R51 + R52)) increases, the stability is deteriorated and oscillation is likely to occur.

  By the way, when the differential amplifier circuit 136a shown in FIG. 2B is used as the error amplifier circuit, the reference voltage is input to the gate of the transistor MN131 and the comparison voltage is input to the gate of the transistor MN132 as described above. Will be. Since the comparison voltage is controlled to be equal to the reference voltage, the comparison voltage is almost equal.

Therefore, when the differential amplifier circuit 136a is used as the error amplifier circuit of the constant voltage power supply circuit, a substantially constant voltage is input to the gates of the two transistors MN131 and MN132.
In the error amplifier circuit, it is not necessary to allow the potential of the input signal over a wide range. The transistors MN131 and MN133 both generate a constant current.

FIG. 3 is a circuit diagram illustrating the configuration of the differential amplifier circuit of this embodiment.
FIG. 3A is a circuit diagram of a differential amplifier circuit 36 a having the first differential amplifier circuit 31. FIG. 3B is a circuit diagram of a differential amplifier circuit 36b having a configuration in which a grounded gate amplifier circuit 32 is overlapped on the high potential side of the first differential amplifier circuit 31 and cascode-connected.

First, the differential amplifier circuit 36a having the first differential amplifier circuit 31 shown in FIG.
The first differential amplifier circuit 31 is a differential amplifier circuit having two enhancement N-type transistors MN31 and MN32, and a source which is a common terminal thereof is connected to the ground GND.

The gate of the transistor MN31 is connected to the output terminal VB of the first reference voltage generation circuit (not shown), and the gate of the transistor MN32 is connected to the output terminal VFB of the feedback circuit (not shown).
That is, the third voltage and the second voltage are input to the gates of the transistors MN31 and MN32, respectively.

In the first differential amplifier circuit 31 of this embodiment, unlike the differential amplifier circuit 136a of the comparative example, there is no transistor MN133 serving as a constant current source between the source and the ground GND. Can be reduced.
Further, since the third voltage can be set small, it is not necessary to reduce the resistance R51 of the feedback circuit 50 and increase the feedback rate even at the time of low voltage output. Therefore, there is no problem that the stability is deteriorated and oscillation occurs.

Furthermore, problems such as deterioration of response characteristics and increase in offset voltage variations due to a decrease in the currents of the transistors MN31 and MN32 during low voltage output do not occur.
As described above, according to the constant voltage power supply circuit 60a of the present embodiment, by using the first differential amplifier circuit 31 as the error amplifier circuit 30a, a low voltage output is possible as compared with the conventional example.

  Further, as shown in FIG. 3B, cascode connection is established by overlapping the grounded gate type amplifier circuit 32 on the high potential side of the first differential amplifier circuit 31, and the output impedance of the grounded gate type amplifier circuit 32. Can be increased. The constant current characteristic is improved with respect to voltage fluctuation of the power supply VDD, and the stability of the output voltage, that is, the second voltage is improved.

  As shown in FIG. 3B, the gates of the transistors MN33 and MN34 constituting the common-gate amplification circuit 32 are connected to the output terminal VB of the first reference voltage generation circuit 10 (not shown). Yes. That is, the third voltage is input to the gates of the transistors MN33 and MN34.

The gates of the transistors MN31 and MN32 constituting the first differential amplifier circuit 31 are the output terminal VA of the second reference voltage generation circuit 20 (not shown) and the output of the feedback circuit 50 (not shown), respectively. Connected to the end VFB.
That is, the fourth voltage and the second voltage are input to the gates of the transistors MN31 and MN32, respectively.

Here, the fourth voltage is set to be lower than the third voltage.
The transistors MN31 and MN32 constituting the first differential amplifier circuit 31 also serve as differential amplification and constant current generation. The gate voltages of the transistors MN33 and 34 constituting the common-gate amplifier circuit 32 are the third voltage, which is higher than the fourth voltage that is the gate voltage of the transistor MN31 constituting the first differential amplifier circuit 31. It is a voltage.

Therefore, the drain-source voltages of the transistors MN31 and MN32 constituting the first differential amplifier circuit 31 can be set to a large value, and the transistors MN31 and MN32 are operated in the saturation region. Can do.
The condition for operating the transistors MN31 and MN32 in the state of the saturation region is expressed by the equation (4) similarly to the equation (3).

ただし、ＶＢは第３の電圧である。また、（３）式と同様に、トランジスタＭＮ３１、ＭＮ３３の物理量にはそれぞれ３１、３３の添え字を付けている。
第３の電圧を（４）式で与えられる基準電圧ＶＢに設定することにより、第４の電圧を小さくしてもトランジスタＭＮ３１、ＭＮ３２を飽和領域で動作させることができる。

However, VB is the third voltage. Similarly to the equation (3), subscripts 31 and 33 are attached to the physical quantities of the transistors MN31 and MN33, respectively.
By setting the third voltage to the reference voltage VB given by the equation (4), the transistors MN31 and MN32 can be operated in the saturation region even if the fourth voltage is reduced.

Next, an embodiment of a constant voltage power supply circuit using the differential amplifier circuit 36b will be described.
FIG. 4 is a circuit diagram illustrating another configuration of the constant voltage power supply circuit according to the embodiment of the invention.
As shown in FIG. 4, the constant voltage power supply circuit 60b of the present embodiment is different from the constant voltage power supply circuit 60a in that the second reference voltage generation circuit 20 and the error amplification circuit 30b are provided.
The error amplifier circuit 30b includes the differential amplifier circuit 36b. First, the second reference voltage generation circuit 20 will be described.

  The second reference voltage generation circuit 20 includes transistors MN20, MN21, MN22, MP21, MP22, MP23, resistors R21, R22, and a capacitor C21, and constitutes a constant voltage power supply circuit.

  The transistors MN21 and MN22 are differential amplifier circuits, and constitute an error amplifier circuit with the transistor MN23 as a constant current source and the transistors MP21 and MP22 as loads. Further, the transistor MP23 inputs the voltage of the power supply VDD and outputs a stabilized voltage. The output is fed back to the error amplification circuit of the transistors MN21 and MN22.

The error amplification circuit receives the third voltage as the reference voltage and the output voltage of the transistor MP23 as the comparison voltage. The error of the comparison voltage with respect to the reference voltage is amplified and controls the transistor MP23.
The output of the transistor MP23 is divided by resistors R21 and R22. A fourth voltage is output using the connection point of the resistors R21 and R22 as the output terminal VA.

In this embodiment, a configuration using a constant voltage power supply circuit having transistors MN21, MN22, MN23, MP21, MP22, and MP23 as the second reference voltage generation circuit 20 is illustrated. However, the present invention is not limited to this, and other configurations, for example, the first differential amplifier circuit 31 can be used. Alternatively, a resistor may be connected to the output terminal VB of the first reference voltage generation circuit 10 to divide the third voltage to obtain the fourth voltage.
The capacitor C21 is inserted for phase compensation.

The error amplifier circuit 30b includes a first stage amplifier circuit 36b and a second stage amplifier circuit 38b. The first stage amplifier circuit 36b is the same as the amplifier circuit 36b shown in FIG.
The second-stage amplifier circuit 38b has a configuration in which a transistor MN39 is added to the second-stage amplifier circuit 38a in the constant voltage power supply circuit 60a shown in FIG.

As shown in FIG. 4, the fourth voltage and the third voltage are input to the gates of the transistors MN38 and MN39, respectively.
As a result, the drain-source voltage of the transistor MN38 can be set to a large value, and the transistor MN38 can be operated in the saturation region.

Thus, according to the constant voltage power supply circuit 60b of the present embodiment, the fourth voltage can be reduced by setting the third voltage to a large value, and a low voltage output is possible. Yes.
In this embodiment, the error amplifying circuit 30b has a two-stage configuration, and the output transistor 40 as a whole is a three-stage amplifying circuit. However, the present invention is not limited to this, and the error amplifying circuit 30b can be composed of one or more stages and an arbitrary number of stages. Further, the second stage amplifier circuit 38b may not be provided.

FIG. 5 is a circuit diagram illustrating another configuration of the constant voltage power supply circuit according to the embodiment of the invention.
As shown in FIG. 5, the constant voltage power supply circuit 60c of this embodiment is different from the constant voltage power supply circuit 60b in that a band gap reference circuit 10a is used as the first reference voltage generation circuit 10a.

  The band gap reference circuit 10a includes a first bipolar transistor Q11, a second bipolar transistor Q12, a third bipolar transistor Q13, a current mirror CM, a first resistor R11, and a second resistor R12.

  In this embodiment, the current mirror CM includes transistors MN12, MN13, and MP11 to MP13, and is configured in two stages. The current mirror CM includes a reference-side transistor MN12, a transistor MN13 that is a first current generation circuit, and a transistor MP13 that is a second current generation circuit.

  The first bipolar transistor Q11 has its base and collector connected to the ground GND, and its emitter connected to the reference transistor MN12 of the current mirror CM.

  The second bipolar transistor Q12 has its base and collector connected to the ground GND. The emitter is connected to the transistor MN13 which is the first current generating circuit of the current mirror CM via the first resistor R11.

  Furthermore, the third bipolar transistor Q13 has its base and collector connected to the ground GND. The emitter is connected to the transistor MP13, which is the second current generation circuit of the current mirror CM, via the second resistor R12.

Here, the emitter areas of the first to third bipolar transistors Q11 to Q13 are set to 1: n: n. However, n> 1.
Due to the current mirror CM, a current I proportional to the absolute temperature flows through the first bipolar transistor Q11, the second bipolar transistor Q12, and the third bipolar transistor Q13.

  That is, the currents I flowing through the first resistor R11 and the second resistor R12 are equal, and the connection point between the second resistor R12 and the transistor MP13 which is the second current generation circuit is the output terminal VB, and the third voltage is Is output. This third voltage can be temperature compensated by setting the resistance values of the first resistor R11 and the second resistor R12. That is, the resistance value can be set so that the differentiation of the third voltage by the absolute temperature becomes zero.

In this embodiment, since the bandgap reference circuit 10a is used as the first reference voltage generation circuit 10a, a temperature-compensated reference voltage can be supplied, and the temperature-compensated stable first voltage is supplied. Can be output.
According to the constant voltage power supply circuit 60c of the present embodiment, a more stable low voltage output is possible.

In the present embodiment, the third voltage is output from the connection point between the transistor MP13, which is the second current generation circuit, and the second resistor R12, but the transistor MN13, which is the first current generation circuit. May be output from a connection point between the first resistor R11 and the first resistor R11.
In the present embodiment, the current mirror CM is illustrated as a two-stage configuration using transistors MN12, MN13, and MP11 to MP13. However, the current mirror CM may be configured with an arbitrary number of stages.
In the constant voltage power supply circuits 60a to 60c, a configuration for outputting a positive voltage is illustrated. However, a constant voltage power supply circuit for outputting a negative voltage can also be configured.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with regard to the specific configuration of each element constituting the constant voltage power supply circuit, the present invention is similarly implemented by appropriately selecting from a well-known range by those skilled in the art, as long as the same effect can be obtained. It is included in the scope of the invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all constant voltage power supply circuits that can be implemented by those skilled in the art based on the constant voltage power supply circuit described above as an embodiment of the present invention are also included in the scope of the present invention as long as they include the gist of the present invention. Belongs to a range.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

DESCRIPTION OF SYMBOLS 10 1st reference voltage generation circuit 10a 1st reference voltage generation circuit (band gap reference circuit)
20 Second reference voltage generation circuit 30a, 30b Error amplification circuit 31 First differential amplification circuit 32 Common gate amplification circuit 32 Differential amplification circuit 36a, 36b First stage amplification circuit (differential amplification circuit)
38a, 38b Second stage amplifier circuit 40 Output transistor 50 Feedback circuit 60a, 60b, 60c Constant voltage power supply circuit 136, 136a Differential amplifier circuit C21, C51 Capacitor GND Ground MD11 First transistor MD12 Depletion N type MOS transistor MN11 First 2 transistors MN12 enhancement N-type MOS transistor (reference side of current mirror)
MN13 enhancement N-type MOS transistor (first current generation circuit)
MN21-MN23, MN31-MN34, MN38, MN39, MN131-MN133 Enhancement N-type MOS transistors MP11-MP12, MP21-MP23, MP31, MP32, MP39, MP131, MP132 Enhancement P-type MOS transistor MP13 Enhancement P-type MOS transistor 2 current generation circuit)
Q11 First bipolar transistor Q12 Second bipolar transistor Q13 Third bipolar transistor R11 First resistor R12 Second resistor R21, R22, R51, R52, R53 Resistor VDD power supply VOUT output terminal

Claims (5)

An output transistor for inputting a voltage from an external power source and outputting a first voltage;
A feedback circuit for outputting the first voltage or a voltage obtained by dividing the first voltage as a second voltage;
A first reference voltage generating circuit for generating a third voltage;
A first differential amplifier circuit that includes two transistors having a common terminal connected to the ground and that amplifies and generates a constant current; amplifies an error of the second voltage with respect to the third voltage; and An error amplification circuit for controlling the output transistor;
A constant voltage power supply circuit comprising: A second reference voltage generating circuit for generating a fourth voltage lower than the third voltage;
The error amplifier circuit further includes a grounded-gate amplifier circuit that is cascode-connected to the high potential side of the first differential amplifier circuit and to which the third voltage is input;
2. The constant voltage power supply circuit according to claim 1, wherein an error between the fourth voltage and the second voltage input to the first differential amplifier circuit is amplified to control the output transistor. . The first reference voltage generation circuit includes:
A first transistor having a drain connected to the power source and a source and a gate connected to each other;
A second transistor having a gate and a drain connected to a source and a gate of the first transistor, respectively, and a source connected to the ground;
Have
3. The constant voltage power supply circuit according to claim 1, wherein the third voltage is output to a source of the first transistor. The first reference voltage generation circuit includes:
A current mirror having first and second current generation circuits;
A first bipolar transistor having a base and a collector each connected to ground and an emitter connected to the reference side of the current mirror;
A first resistor having one end connected to the first current generating circuit;
A second resistor having one end connected to the second current generating circuit;
A second bipolar transistor having a base and a collector each connected to ground and an emitter connected to the other end of the first resistor;
A third bipolar transistor having a base and a collector each connected to ground and an emitter connected to the other end of the second resistor;
Have
3. The constant voltage power supply circuit according to claim 1, wherein the constant voltage power supply circuit is a band gap reference circuit that outputs the third voltage to a connection point between the second resistor and the second current generation circuit.   5. The constant voltage power supply circuit according to claim 4, wherein a resistance value of the second resistor is set so that differentiation of the third voltage with respect to temperature becomes zero.

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