JP2011009553A - Inspection system and inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection system capable of highly accurately determining correlation between the distribution pattern of defects in a semiconductor wafer found in a defect inspection, and the distribution pattern in a defective semiconductor chip found in an electric test, in a short time.SOLUTION: The electric test is performed to a plurality of semiconductor chips of the semiconductor wafer. Presence/absence of a correlation is determined by checking first coordinate data of the defective semiconductor chip found in the electric test, and third coordinate data of the semiconductor chip obtained by statistically processing circuit characteristic values measured by changing a condition about the semiconductor chip. Presence/absence of a correlation is determined by checking the first coordinate data determined that there is no correlation with the third coordinate data, and second coordinate data of the defective semiconductor chip found in the defect inspection of the semiconductor chip.

Description

  The present invention relates to a semiconductor wafer inspection system and inspection method.

  In recent years, in the manufacturing process of a semiconductor device such as an LSI, the number of manufacturing steps has increased and the processing technology has become more complicated. As a result, leakage current increases around the connection holes (contact holes, via holes) of the transistor elements, the connection holes of the interlayer insulating film are not opened, and the wirings are poorly connected. Problems in the manufacturing process are diversifying, such as electrical short circuits between them.

  As one method for solving such diversified problems, there is a method of performing in-line defect inspection on the surface of a semiconductor wafer during the manufacture of a semiconductor device. The in-line defect inspection is to detect a pattern shape abnormality or foreign matter generation at the time of manufacturing a semiconductor device as a defect. And if a defect is detected by this in-line defect inspection, it is regarded as a process defect, and the cause of the defect is estimated from the number of defects, distribution in the wafer surface, images such as photographs with a metal microscope or an electron microscope, Provide feedback for quality improvement.

  In addition, in the manufacturing process of a semiconductor device, an electrical test at the wafer level is performed on individual semiconductor chips formed on a semiconductor wafer after completing a series of steps in order to check whether the circuit operates normally. Is done. There is also a method for solving problems that occur during the process by combining the electrical test and the in-line defect inspection described above.

  However, in the manufacturing process complicated by the increase in the number of processes, there are various defect factors such as insufficient processing accuracy in addition to the defects found by in-line defect inspection, and the electrical test includes all these defects. It will be a comprehensive test. For this reason, a semiconductor chip having a defect found by in-line defect inspection does not always become a defective semiconductor chip in an electrical test. On the contrary, a semiconductor chip having no defect may become defective in an electrical test.

  Therefore, when combining in-line defect inspection and electrical test, compare the distribution patterns of defects and defective semiconductor chips, and find out the cause of defects due to defects by how to find the correlation between them accurately. It will be an important technology for.

  However, the coordinate system of chip coordinates used differs between in-line defect inspection and electrical test. Conventionally, since there is no method or system for automatically analyzing the correlation between the distribution patterns of defects and defective semiconductor chips output in different coordinate systems in this way, humans visually compare each distribution. , Was determining the correlation. Judgment that relies on human vision takes a long time and is ambiguous, so a technique for improving accuracy and reducing man-hours is desired.

JP 2007-300003 A JP 2004-55837 A

In order to solve the above problems, techniques such as Patent Documents 1 and 2 have been devised. In particular, in Patent Document 1, defect data determined as local distribution and test result data are matched as chip coordinates with high accuracy by standardizing chip coordinates and physical coordinates, and then the shape of the defect data is determined. In addition, a technique for performing weighting other than coordinate matching based on incidental information such as length is proposed.
According to this technique, it is said that the correlation between the defect data and the local distribution of the test result can be automated to ensure the accuracy. However, it cannot be said that the correlation between the defect distribution pattern of the semiconductor wafer discovered by the defect inspection and the distribution pattern of the defective semiconductor chip discovered by the electrical test can be obtained with extremely high accuracy. Further improvement is desired.

  The present invention has been made in view of the above problems, and a correlation between a defect distribution pattern of a semiconductor wafer discovered by defect inspection and a distribution pattern of defective semiconductor chips discovered by an electrical test. It is an object of the present invention to provide an inspection system and an inspection method capable of performing a high-accuracy and in a short time with extremely high accuracy.

  One aspect of the inspection system includes a first database that stores first coordinate data of defective semiconductor chips of a semiconductor wafer, a second database that stores second coordinate data of defective semiconductor chips of the semiconductor wafer, and the semiconductor A third database that stores third coordinate data of semiconductor chips obtained by statistically processing circuit characteristic values measured under different conditions of the wafer, and the first coordinate data and the third coordinate data are collated, A first calculation unit that determines the presence or absence of a correlation between the two, the first coordinate data determined by the first calculation unit to have no correlation with the third coordinate data, and the second coordinate data; And a second calculation unit that determines whether or not there is a correlation between the two.

  One aspect of the inspection method is the step of performing an electrical test on a plurality of semiconductor chips on a semiconductor wafer, obtaining first coordinate data of the defective semiconductor chip found in the electrical test, and a defect in the semiconductor chip. Performing inspection, obtaining second coordinate data of the semiconductor chip of the defect found in the defect inspection, measuring circuit characteristics of the semiconductor chip under different conditions, and statistically processing the circuit characteristic value Obtaining the third coordinate data of the semiconductor chip, comparing the first coordinate data and the third coordinate data to determine whether or not there is a correlation between them, and correlating with the third coordinate data Collating the first coordinate data determined to be absent and the second coordinate data to determine whether or not there is a correlation between them.

  According to each aspect described above, the correlation between the distribution pattern of the defect of the semiconductor wafer discovered by the defect inspection and the distribution pattern of the defective semiconductor chip discovered by the electrical test is more highly accurate, It is possible to carry out with high accuracy in a short time, and a highly reliable semiconductor device is realized.

1 is a configuration diagram of a semiconductor wafer inspection system according to an embodiment. FIG. It is a flowchart which shows the inspection method of the semiconductor wafer by this embodiment. It is a figure for demonstrating the function of the summary part and statistical processing part of FIG. It is a figure which represents typically the inspection data output from an inspection apparatus. It is a top view showing chip coordinates (i, j) and physical coordinates (X, Y). It is a figure which represents typically the test data output from a test device. It is a top view for demonstrating the chip | tip coordinate used by test data. It is a flowchart for explaining the reference method for each data D _i1, D _t1, D _c1 in step S6. It is a figure which represents typically conversion to a chip coordinate. It is a schematic diagram for demonstrating step S22. It is a top view which shows an example of the distribution pattern of a defect. It is a flowchart for demonstrating the method of classifying the distribution pattern of a defect. It is a figure which represents classified inspection data typically. It is a figure for demonstrating an example of a physical coordinate. It is a flowchart for demonstrating the method of classifying the distribution pattern of a defective semiconductor chip. It is a figure which represents classified test data typically. It is a flowchart for demonstrating the method of classifying the distribution pattern of a circuit characteristic value. It is a figure which represents the classified circuit measurement data typically. It is a flowchart for demonstrating the method of collating the test result data classified and the circuit measurement data classified, and making the presence or absence of correlation of both. It is a figure which shows step S61 typically. It is a flowchart for demonstrating the method of collating the test | inspection data already classified and uncorrelated data. It is a figure for demonstrating an example of a physical coordinate. It is a figure which represents typically the synthetic | combination data after complete | finishing step S73. It is a figure which shows step S71 typically. It is a flowchart for demonstrating the method of calculating a whole correlation rate. It is a figure which shows chip | tip information typically.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a semiconductor wafer inspection system according to the present embodiment.
As illustrated, the inspection system 1 is connected to an inspection device 2, a test device 3, a circuit measurement device 4, and a user terminal client 5.

The inspection apparatus 2 performs defect inspection on a semiconductor wafer that is being manufactured. For example, the inspection apparatus 2 detects defects in the shape of wiring and connection holes (contact holes and via holes) by scanning the wafer surface with a laser beam. It is. The data of the semiconductor chip evaluated as having a defect is input to the inspection system 1 as inspection data.
The test apparatus 3 performs a final electrical test on the semiconductor wafer after the semiconductor chips are integratedly formed, and determines whether or not the semiconductor chip operates normally normally (good / bad semiconductor chip). Device. The data of the semiconductor chip evaluated as defective is input to the inspection system 1 as test data.
The circuit measurement device 4 electrically measures each semiconductor chip formed on the semiconductor wafer while changing the measurement conditions (power supply voltage and operating frequency), acquires a plurality of circuit characteristic values with different measurement conditions, and defines them in advance. This is a device for determining the presence or absence of a failure depending on the tolerance (circuit margin). Data of the semiconductor chip evaluated as a failure depending on the circuit margin is input to the inspection system 1 as circuit characteristic data.
In addition, although the case where the test apparatus 3 and the circuit measurement apparatus 4 are provided separately is illustrated here, one apparatus having the functions of the test apparatus 3 and the circuit measurement apparatus 4 may be provided.

The inspection system 1 determines whether or not there is a correlation between a distribution pattern of defects found by the inspection apparatus 2 in the wafer surface and a distribution pattern of defective semiconductor chips found by the test apparatus 3 in the semiconductor wafer surface. The determination is made in consideration of the circuit characteristic value acquired by the measuring device 4.
The inspection system 1 includes a data management server 11, a first application analysis server 12, and a second application analysis server 13. The data management server 11 and the second application analysis server 13 are connected via a LAN (Local Area Network) 14, and the second application analysis server 13 and the user terminal client 5 are connected via a LAN 15. The correlation of the distribution pattern acquired in the inspection system 1 is displayed on the user terminal client 5 via the LAN 15.

  The data management server 11 includes a standardization unit 21, a defect database 22, a test result database 23, and a circuit measurement database 24.

The standardization unit 21 performs standardization in which the inspection data received from the inspection device 2, the test data received from the test device 1, and the circuit measurement data received from the circuit measurement device 4 are all set to the same coordinate system. is there.
Specifically, the standardization unit 21 uses the semiconductor wafer layout reference information to test the inspection data coordinate system based on the test data chip coordinate coordinate system (circuit measurement data chip coordinate coordinate system). Standardization is performed to match the data coordinate system (the circuit measurement data coordinate system).

The defect database 22 is a database for storing inspection data standardized by the standardization unit 21.
The test result database 23 is a database for storing standardized test data.
The circuit measurement database 24 is a database for storing standardized circuit measurement data.

  The first application analysis server 12 processes circuit measurement data received from the circuit measurement device 4, and includes a summarization unit 31, a first management knowledge 32, a statistic calculation unit 33, and a second management knowledge 34. Configured.

The summarizing unit 31 summarizes the shmoo data waveform of the circuit measurement data for each semiconductor wafer into arbitrary representative values (representative shmoo point values), and sets the measurement conditions corresponding to the representative values to categories. As XML (eXtensible Markup Language). The shum data is data indicating the result of verifying the operation of the target semiconductor device with two correlated parameters such as the power supply voltage and the operating frequency as two axes.
The first management knowledge 32 stores and manages the representative value acquired by the summarizing unit 31 and the measurement condition converted into XML.
The statistical processing unit 33 statistically processes and summarizes the representative values read from the first management knowledge 32, and converts the statistically processed chip coordinates into XML.
The second management knowledge 34 stores and manages XML-ized chip coordinates acquired by the statistical processing unit 33.

  The second application analysis server 13 includes a first classification unit 41 that processes inspection data, a second classification unit 42 that processes test result data, a third classification unit 43 that processes circuit measurement data, a first calculation unit 44, 1 knowledge database 45, the 2nd calculating part 46, and the 2nd knowledge database 47 are comprised.

The first classifying unit 41 extracts and classifies a specific distribution of defects (for example, a line-shaped (linear) or cluster-shaped (lumped) defect distribution) based on inspection data.
The second classification unit 42 extracts and classifies a specific distribution of defective semiconductor chips based on the test result data.
The third classification unit 43 extracts and classifies a singular distribution of circuit characteristic values based on circuit measurement data.

The first calculation unit 44 collates the test result data classified by the second classification unit 42 with the circuit measurement data classified by the third classification unit 43, and determines whether or not there is a correlation between the two. . The first calculation unit 44 assigns a new classification category to the coordinate data of the defective semiconductor chip determined to have the correlation.
The first knowledge database 45 is a database for storing chip coordinates for which the presence or absence of correlation (for example, a matching rate described later) is determined by the first calculation unit 44. In the first knowledge database 45, the chip coordinates of the defective semiconductor chip that is determined to have the correlation and is given a new classification category are managed. In addition, a defective semiconductor chip related to the correlation (coincidence rate) in the past and an actual defect that has occurred in the semiconductor chip is stored with a predetermined weight assigned to the chip coordinate so that it can be identified.

The second calculation unit 46 collates the classified test result data determined to have no correlation with the circuit measurement data classified by the first calculation unit 44 and the inspection data classified by the first classification unit 41. Thus, it is determined whether or not there is a correlation between the two. In the second arithmetic unit 46, the overall degree of correlation between the classified test result data determined to have no correlation with the classified circuit measurement data and the inspection data classified by the first classification unit 41 (described later) (Total correlation rate) is calculated.
The second knowledge database 47 is a database for storing test result data and inspection data for which the presence or absence of correlation (for example, a matching rate described later) is determined by the second calculation unit 46. In the second knowledge database 47, a predetermined weight is assigned to the chip coordinates so that a defective semiconductor chip related to the correlation (match rate) in the past and an actual defect that has occurred in the semiconductor chip can be identified. Stored.

  In the present embodiment, the first calculation unit 44 and the second calculation unit 46 are provided separately, but one calculation unit having the functions of the calculation units 44 and 46 may be provided.

Next, a semiconductor wafer inspection method using the inspection system 1 will be described.
FIG. 2 is a flowchart showing the semiconductor wafer inspection method according to the present embodiment.

Using the inspection apparatus 2 in FIG. 1, a semiconductor wafer being manufactured is inspected for defects (step S1).
Using the test apparatus 3 of FIG. 1, a final electrical test is performed on the semiconductor wafer after the semiconductor chips are integrated and formed (step S2).
Using the circuit measurement device 4 of FIG. 1, electrical measurement is performed on each semiconductor chip formed on a semiconductor wafer while changing measurement conditions (power supply voltage and operating frequency), and a plurality of circuit characteristic values with different measurement conditions are obtained. Obtain (step S3). Here, the semiconductor chip depending on the tolerance (circuit margin) is determined as a failure.

Subsequent to step S3, the summarizing unit 31 in FIG. 1 summarizes the sum data waveform of the circuit measurement data for each semiconductor wafer into an arbitrary representative value, and performs XML using the measurement condition corresponding to the representative value as a category (step S4). . An example of a Schum plot is shown in FIG. In FIG. 3A, the horizontal axis k is, for example, the operating frequency, and the vertical axis is the circuit characteristic value. By shaking the value of k, a plurality of Schum plots for each k value corresponding to FIG.
The representative value acquired by the summarizing unit 31 and the measurement condition converted into XML are stored in the first management knowledge 32.
Subsequently, as shown in FIG. 3B, the statistical processing unit 33 in FIG. 1 superimposes the semiconductor wafers W so that the semiconductor chips C coincide with each other, and the representative value read from the first management knowledge 32 in FIG. Are statistically processed and summarized, and the statistically processed chip coordinates are converted into XML (step S5).

  Subsequent to step S1, the standardization unit 21 in FIG. 1 uses the semiconductor wafer layout reference information as a reference for the coordinate system of the chip coordinate of the test data and sets the coordinate system of the inspection data of the test data (circuit measurement data). Normalization is performed according to the coordinate system (step S6).

Step S6 will be described in detail below.
FIG. 4 is a diagram schematically showing the inspection data D _i1 output from the inspection apparatus 2.
The inspection data D _i1 includes chip coordinates (i, j) where a defect is found and physical coordinates (X, Y) in the chip.

FIG. 5 is a plan view showing these chip coordinates (i, j) and physical coordinates (X, Y). As shown in FIG. 5, the semiconductor chip C ₀ including the center P of the semiconductor wafer is the origin (0, 0) of the chip coordinates. When the notch N of the semiconductor wafer W is raised, the X coordinate of the chip coordinate increases by 1 as it goes to the right from the semiconductor chip C _0, and the Y coordinate increases by 1 as it goes upward.
Further, physical coordinates (X, Y) are assigned to each semiconductor chip, and the origin is the lower left point of each chip.

On the other hand, FIG. 6 is a diagram schematically showing test data D _t1 output from the test apparatus 3. The test data D _t1 is composed of chip coordinates (i, j) of a defective semiconductor chip discovered by an electrical test. Similarly, the circuit measurement data D _c1 is composed of chip coordinates (i, j) of a semiconductor chip evaluated as a failure depending on the circuit margin.

FIG. 7 is a plan view for explaining chip coordinates used in the test data D _t1 .
As shown in FIG. 7, the origin (0, 0) of the chip coordinates is the upper left semiconductor chip when the notch N of the semiconductor wafer W is down (in the case of notch down). The X coordinate of the chip coordinate increases by 1 as it goes to the right from the upper left semiconductor chip, and the Y coordinate increases by 2 as it goes down.

As described above, in the inspection apparatus 2 for the semiconductor wafer in which the semiconductor chip is being manufactured and the test apparatus 3 for the semiconductor wafer in which the semiconductor chip has been completed, the origin (0, 0) of the chip coordinates. And the direction in which the chip coordinates increase is also different. For this reason, the data D _i1, D _t1, D _c1 cannot be compared with each other.

Therefore, in the present embodiment, each data D _i1 , D _t1, D _c1 is standardized as follows.
FIG. 8 is a flowchart for explaining the standardization method for each data D _i1 , D _t1, D _c1 in step S6.
First, the chip coordinates (i, j) of the inspection data D _i1 obtained on the basis of the state in which the notch of the semiconductor wafer is above are converted into the chip coordinates of the state in which the notch is below (notch down) (step S21).

FIG. 9 is a diagram schematically showing this conversion.
As shown in FIG. 9, this conversion corresponds to rotating the semiconductor wafer W by 180 degrees. For example, the semiconductor chip A located at the lower right (1, −1) before the conversion moves to the upper left after the conversion. Further, in this conversion, since the origin O of the physical coordinates (X, Y) of the defect in each semiconductor chip is at the upper right of the chip due to the rotation of the semiconductor wafer W by 180 degrees, the defect in the first quadrant is the first. Move to 3 quadrants. Therefore, the defect F whose physical coordinates before conversion are (x, y) has physical coordinates (-x, -y) whose signs are reversed after conversion.

Next, the distance between the origin of the chip coordinates of the inspection data D _i1 (the semiconductor chip including the center P of the semiconductor wafer W) and the origin of the chip coordinates of the defect data D _t1 (the upper left semiconductor chip) in the chip coordinates. An offset (N _x , N _y ) indicating whether or not is present is acquired (step S22).

FIG. 10 is a schematic diagram for explaining step S22.
As shown in FIG. 10, the offset (N _x , N _y ) is obtained from the following equations (1) and (2).
N _x = {A _x + (s _x −a _x )} / s _x (1)
N _y = {A _y + (s _y −a _y )} / s _y (2)
In these equations, A _x (A _y ) represents a signed vector distance in the X direction (Y direction) between the lower left point Q of the upper left semiconductor chip C and the center P of the semiconductor wafer. Further, s _x (s _y ) is the length of one semiconductor chip in the X direction (Y direction). A _x (a _y ) is the absolute value of the distance in the X direction (Y direction) between the center P of the semiconductor wafer and the upper right point R of the semiconductor chip C _p including the center P.

In the example of FIG. 10, (N _x , N _y ) = (− 1, +1). Therefore, the origin of the chip coordinates of the inspection data D _i1 (chip C _p including the center P of the semiconductor wafer W) and the origin of the chip coordinates of the defect data D _t1 (semiconductor chip C in the upper left) are the X direction and Y That is one chip away in either direction.

Next, by performing coordinate conversion, the origin of the chip coordinates of the inspection data D _i1 set for the semiconductor chip including the center P is reset to the upper left of the semiconductor wafer W (step S23). This coordinate conversion is performed as follows using the above-described offset (N _x , N _y ).

(I, j) = (N _x + i ′, N _y + j ′) (3)
In equation (3), (i ′, j ′) represents the chip coordinates before conversion, and (i, j) represents the chip coordinates after conversion.

For example, in the semiconductor chip A (see FIG. 9) in which the chip coordinates (i ′, j ′) before conversion is (1, −1), the chip coordinates (i, j) after conversion are (0, 0). It turns out that it moves to the origin in the coordinate system of test data. After the chip coordinates are converted, the physical coordinates of the defect data are managed with a minus sign (−x, −y) as described above.
This completes the standardization of the chip coordinates of the inspection data D _i1 .

The standardized inspection data D _i1 is stored in the defect database 22 as standardized inspection data D _i2 . The standardized inspection data D _i2 has the same format as the inspection data D _i1 and circuit measurement data D _c1, and the chip coordinates and the physical coordinates of the defect ( -X, -y).

  In the present embodiment, the standardization of matching the coordinate system of the inspection data with the coordinate system of the test data (circuit measurement data) is exemplified with reference to the coordinate system of the chip coordinate of the test data (circuit measurement data). There is a case where each of the data, the test data, and the circuit measurement data is normalized to a predefined coordinate system.

FIG. 3C shows an example of a semiconductor wafer W including a semiconductor chip to which circuit measurement data D _c1 normalized to a notch down state is attached.
In FIG. 3C, the defective semiconductor chip C is shown with a mesh pattern.

Following step S6 in FIG. 2, the first classification unit 41 in FIG. 1 extracts and classifies the specific distribution of defects based on the standardized inspection data (step S7).
Step S7 in FIG. 2 will be described in detail below.

Defects discovered by the inspection apparatus 2 are often distributed in a specific pattern, for example, a line shape (line shape) or a cluster shape (lumb shape) in the wafer surface.
FIG. 11 is a plan view showing an example of a defect distribution pattern. In the example of FIG. 11, the defect F _C is distributed to the cluster shape on the semiconductor the wafer W, a defect F _L are distributed in a line.

Therefore, a method for analyzing whether the defect distribution pattern is classified into a line shape or a cluster shape will be described next.
FIG. 12 is a flowchart for explaining a method of classifying defect distribution patterns.
First, the standardized inspection data D _i2 is fetched from the defect database 22 to the first classification unit 41 (step S31).

Next, using a so-called Defect-SSA (Spatial Signature Analysis), the defect distribution pattern is classified based on the standardized inspection data _Di2 (step S32). Defect-SSA is a tool that analyzes whether the defect distribution pattern is classified into line or cluster based on the physical position coordinates X and Y of each defect. It can be implemented using packaged software. In step S32, the size of the distribution pattern is also determined.

  When the distribution pattern is a line, the size is determined by setting a threshold value in advance. If the length of the distribution pattern is equal to or greater than the threshold value, the distribution pattern is determined to be “long” and less than the threshold value. In this case, the determination is made as “short”.

Next, the distribution pattern classified in step S32 and its size are _added to the standardized inspection data D _i2 to obtain classified inspection data D _i3 as shown in FIG.

The example of FIG. 14 shows that defects having physical coordinates (70000 μm, 70000 μm) and (70001 μm, 70001 μm) have a common line distribution. Further, this example shows that the line-shaped distribution is determined to be “long”.
As described above, the defect distribution patterns found in the inspection apparatus 2 are classified by shape and size.

Following step S2 in FIG. 2, the second classification unit 42 in FIG. 1 extracts and classifies the specific distribution of defective semiconductor chips based on the test result data (step S8).
Step S8 in FIG. 2 will be described in detail below.
In FIG. 12, the classification of defect distribution patterns has been described. Similar to defects, even a defective semiconductor chip discovered by the test apparatus 3 may show a distribution pattern such as a line shape or a cluster shape.

FIG. 14 is a plan view showing an example of a distribution pattern of defective semiconductor chips. In FIG. 14, the defective semiconductor chip is shown with a mesh pattern. And, in this example, along with defective semiconductor chip C _C is distributed in a cluster shape, defective semiconductor chip C _L is distributed in a line.
Hereinafter, a method for analyzing whether the distribution pattern of defective semiconductor chips discovered by the test apparatus 3 is classified into a line shape or a cluster shape will be described.

FIG. 15 is a flowchart for explaining a method of classifying a distribution pattern of defective semiconductor chips.
First, the test data D _t1 is taken from the test result database 23 into the second classification unit 42 (step S41).
Next, using the above-described Defect-SSA, the distribution pattern of the defective semiconductor chip is classified based on the test data D _t1 and the size of the distribution pattern is also determined (step S42).
The determination of the pattern size is performed in the same manner as in step S32 described with reference to FIG. That is, when the distribution pattern is a line, a size threshold is set in advance, and when the length of the distribution pattern is equal to or greater than the threshold, the distribution pattern is determined to be “long”, and when the distribution pattern is less than the threshold Judge as “short”.

Then the size of the classified distribution pattern imparted to the scaled test data D _t1 in step S42, to obtain the test data D _t2 classification already shown in FIG. 16 (step S43).
As described above, the distribution patterns of defective semiconductor chips discovered by the test apparatus 3 are classified by shape and size.

Following step S7 in FIG. 2, the third classification unit 43 in FIG. 1 extracts and classifies the singular distribution of circuit characteristic values based on the circuit measurement data (step S9).
Step S9 in FIG. 2 will be described in detail below.
Similar to the defect, the circuit characteristic value of the semiconductor chip measured by the circuit measuring device 4 is a pattern of a singular distribution such as a line shape or a cluster shape due to a mismatch between the processing accuracy of the manufacturing process and the allowable value of the circuit design. May show.
Hereinafter, a method for analyzing whether or not the distribution pattern of the circuit characteristic values measured by the circuit measuring device 4 is classified into a line shape or a cluster shape will be described.

FIG. 17 is a flowchart for explaining a method of classifying circuit characteristic value distribution patterns.
First, circuit measurement data D _c1 is fetched from the circuit characteristic database 24 to the third classification unit 43 (step S51).
Next, using the BIN-SSA technique, the distribution patterns of circuit characteristic values are classified based on the standardized circuit measurement data D _c1 and the size of the distribution pattern is also determined (step S52).
The determination of the pattern size is performed in the same manner as in step S32 described with reference to FIG. For example, a threshold value of the cluster size is set in advance, and when the distribution pattern size is equal to or larger than the threshold value, the distribution pattern is determined to be “large (in a cluster shape)”. Judged as “small (not clustered)”.

Next, by applying its size and classified distribution pattern in step S52 to the scaled circuit measurement data D _c2, obtaining circuit measurement data D _c2 classification already shown in FIG. 18 (step S53) .
The classified circuit measurement data D _c2 is fed back and stored in the circuit characteristic database 24, and is managed for each type (technology unit) of the semiconductor device (step S54).

Following the steps S8 and S9 in FIG. 2, the first calculation unit 44 in FIG. 1 collates the test result data classified by the second classification unit 42 with the circuit measurement data classified by the third classification unit 43. Whether or not there is a correlation between the two is determined (step S10).
Step S10 in FIG. 2 will be described in detail below.
FIG. 19 is a flowchart for explaining a method of collating the classified test result data with the classified circuit measurement data to determine whether or not there is a correlation between the two.

First, the respective chip coordinates of the classified test data D _t2 and the classified circuit measurement data D _c2 are collated, and among these data D _t2 and D _c2 , those having the same chip coordinates are “correlated”, Of the classified test data data D _t2 , the classified circuit measurement data D _c2 and the chip coordinates that do not match are classified as “no correlation” (step S61). The former is correlated data, and the latter is uncorrelated data _Dt3 .

FIG. 20 schematically shows step S61. The semiconductor chip C ₂ (right shoulder) evaluated as a failure depending on the chip coordinates of the defective semiconductor chip C ₁₁ (indicated by the hatching pattern with the lower right shoulder) of the test result semiconductor wafer W and the circuit margin of the circuit measurement result. The chip coordinates (indicated by the rising hatch pattern) are collated. Then, correlated data which is a chip coordinate (the former chip coordinate) common to both of them indicated by a broken line in FIG. 20 is removed from the chip coordinate of the defective semiconductor chip C ₁₁ of the semiconductor wafer W as a test result. In the semiconductor wafer W of the test results, uncorrelated data D _t3 is created, (indicated by hatched) semiconductor chip C ₁ 2 of the defective semiconductor chips only remain.

The following steps S62 to S64 are executed for the correlated data.
The uncorrelated data D _t3 is sent to the second calculation unit 46 in FIG. 1, and step S12 described later is executed.

In step S62, composite data D _s1 is created for the correlated data.
In the synthesized data D _s1 , classified test data D _t2 having the same chip coordinates and classified circuit measurement data D _c2 are arranged in the same row, and items of “chip coordinates” and “matching rate” beside them. Is granted. Among these, the “chip coordinates” item is given the chip coordinates of each row.
Note that the item “match rate” is further subdivided into items “classification (shape)” and “classification (size)”, which will be described later.

Next, for each row of the composite data D _s1 described above, the shapes of the distribution patterns of the circuit characteristic values depending on the defective semiconductor chip and the circuit margin are collated to determine whether or not the shapes are the same. (Step S63). If it is determined that the shapes are the same, for example, 1 is written in the “classification (shape)” item of “match rate”, and 0 is written if they are not the same.

Next, for each row of the composite data D _s1 , the sizes of the distribution patterns of the circuit characteristic values depending on the defective semiconductor chip and the circuit margin are collated to determine whether or not the sizes are the same. (Step S64). If it is determined by this determination that the sizes are the same, for example, 1 is written in the “classification (size)” item of “match rate”, and 0 is written if they are not the same.

Subsequently, following step S10 in FIG. 2, the first calculation unit 44 in FIG. 1 assigns a new classification category to the coordinate data of the correlated defective semiconductor chip in the combined data D _s1 (step S11).

Subsequently, following steps S7 and S10 in FIG. 2, the second calculation unit 46 in FIG. 1 includes the inspection data D _i3 already classified by the first classification unit 41 and the uncorrelated data D _t3 created in step S61. Are compared to determine whether or not there is a correlation between them, and an overall correlation rate is calculated (step S12).
Step S12 in FIG. 2 will be described in detail below.

First, the defects found by the inspection apparatus 2, how to match each chip coordinates with uncorrelated data D _t3 created in step S61 will be described.
FIG. 21 is a flowchart for explaining a method of collating classified inspection data with uncorrelated data.

First, the respective chip coordinates of the classified inspection data D _i3 and the uncorrelated data D _t3 classified in step S61 are collated, and the data D _i3 and D _t3 having the same chip coordinates are compared with each other. As a pair, synthesized data D _s2 as shown in FIG. 22 is obtained (step S71).
In the combined data D _s2 , classified inspection data D _i3 and uncorrelated data D _t3 having the same chip coordinates are arranged in the same line, and items of “chip coordinates” and “match rate” are given beside them. The Among these, the “chip coordinates” item is given the chip coordinates of each row.

  For example, in the example of FIG. 22, a defect having a physical coordinate (70000 μm, 70000 μm) has a chip coordinate of (1, 1). Therefore, (1, 1) is arranged in the “chip coordinates” next to the defect data. Note that the item “match rate” is further subdivided into items “classification (shape)” and “classification (size)”, which will be described later.

Next, with respect to each row of the composite data D _s2 described above, the shapes of the distribution patterns of the defect and the defective semiconductor chip are collated, and it is determined whether or not the shapes are the same (step S72). If it is determined that the shapes are the same, 1 is written in the “classification (shape)” item of “match rate”, and 0 is written if they are not the same.

Next, for each row of the composite data D _s2 , the sizes of the distribution patterns of the defect and the defective semiconductor chip are collated, and it is determined whether or not the sizes are the same (step S73). If it is determined that the sizes are the same, 1 is written in the “classification (size)” item of “match rate”, and 0 is written if they are not the same.

FIG. 23 is a diagram schematically illustrating the combined data D _s2 after step S73 is completed.
In the example of FIG. 23, a defect having physical coordinates (70000 μm, 70000 μm) and a defective semiconductor chip having chip coordinates (1, 1) have distribution patterns having the same shape (line) and the same size (long), respectively. 1 belongs to “Category (shape)” and “Category (size)” in the first row.

  On the other hand, the distribution pattern of defects to which defects with physical coordinates (140000 μm, 140000 μm) belong and the distribution pattern of defective semiconductor chips to which a defective semiconductor chip with chip coordinates (2, 1) belongs have the same shape (line). It has different sizes, such as “long” and “short”. Therefore, 1 is written in the “classification (shape)” of the last line, and 0 is written in the “classification (size)”.

FIG. 24 schematically shows step S71. The chip coordinates of defective semiconductor chips (indicating cluster-like and line-like defects) of the inspected semiconductor wafer W and the semiconductor chip C ₁₂ (shown in a mesh pattern) corresponding to uncorrelated data among the defective semiconductor chips. The chip coordinates are collated and composite data D _s2 is created.

Subsequently, the overall correlation rate between the distribution pattern of defects found in the inspection apparatus 2 in the wafer surface and the distribution pattern in the wafer surface of the corresponding semiconductor chip of the uncorrelated data D _t3 created in step S61. A method for calculating the value will be described.
FIG. 25 is a flowchart for explaining this method.

First, the chip coordinates (i, j) are set to (1, 1) (step S81).
Next, the process proceeds to step S32, and it is determined whether or not the composite data D _s2 has a chip coordinate equal to (i, j) (step S82). If it is determined that it exists (YES), the process proceeds to step S73, and the chip coordinates (i, j) are extracted. The extracted chips coordinates are additionally written to the chip information D _c shown in FIG. 26. The chip information _Dc is stored in the second knowledge database 42 of FIG.

Next, the process proceeds to step S84. If it is determined in step S82 that there is no chip data having a chip coordinate equal to (i, j) in the composite data D _s2 (NO), the process proceeds to step S84. In step S84, it is determined whether or not the determination in step S82 has been performed for all chip coordinates in the j-th column.
If it is determined that the process has not been performed (NO), the process proceeds to step S35, i is incremented by 1, and step S82 is performed again. On the other hand, if it is determined that the determination has been made (YES), the process proceeds to step S86, and it is determined whether or not the determination in step S82 has been performed for all chip coordinates.

Here, if it is determined that it has not been performed (NO), the process proceeds to step S87, j is incremented by 1, and step S82 is performed again. On the other hand, if it is determined that the determination has been made (YES), the process proceeds to step S88.
In step S88, counting the number X ₁ chip coordinates included in the chip information D _c extracted in step S83.

The chip coordinates included in the chip information D _c are equal to the total number of different chip coordinates included in the composite data D _s2 (in addition, the composite data D _s2 is classified inspection data D having the same chip coordinates. _i3 because is obtained by a pair of uncorrelated data D _t3, the number X ₁ above, among the defective semiconductor chip influences the circuit margin has been removed in the circuit characteristics, the same chip coordinates defective Equal to the number of things you have.
Furthermore, this step S88, the total number of chips coordinates included in uncorrelated data D _t3, that is, calculates the number Y ₁ All defective semiconductor chip influences the circuit margin has been removed in the circuit characteristics.

Next, compute the number X ₁ and Y ₁ of the whole is the ratio correlation index P ₁ = X ₁ / Y ₁ (step S89).
Next, it is determined whether or not there is a correlation between the distribution patterns of the defect and the defective semiconductor chip using the ratio P ₁ (step S90). This, for example, that the entire correlation factor P ₁ is determined to correlate is in the case where the reference value (e.g., 0.9) or more, it is determined that there is no correlation when the overall correlation factor P ₁ is less than the reference value Done in
In step S90, the accuracy of determination may be increased by increasing the reference value, and the accuracy of determination may be decreased by decreasing the reference value.

  As described above, according to the present embodiment, the correlation between the defect distribution pattern of the semiconductor wafer discovered by the defect inspection and the distribution pattern of the defective semiconductor chip discovered by the electrical test is expressed by the latter. By removing the influence of the circuit margin on the circuit characteristics from the distribution pattern, it is possible to perform with high accuracy and in a short time with higher accuracy, and to realize a highly reliable semiconductor device.

Each component of the inspection system according to the present embodiment described above (the standardization unit 21, the summarization unit 31, the statistic calculation unit 33, the first to third classification units 41 to 43, and the first and second calculation units 44 of FIG. , 46, etc.) is realized by executing a program read from a storage medium such as a ROM or a hard disk by a CPU of the computer.
Similarly, each step of the graphic verification method (steps S1 to S12 in FIG. 2, steps S21 to S23 in FIG. 8, S31 to S33 in FIG. 12, S41 to S43 in FIG. 15, S51 to S53 in FIG. 17, and S51 in FIG. S61 to S64, S71 to S73 in FIG. 21, S81 to S90 in FIG. 25, etc.) can be realized by operating a program read from a storage medium such as a ROM or a hard disk. This program and a computer-readable storage medium storing the program are included in this embodiment.

  Specifically, the program is recorded on a recording medium such as a CD-ROM or provided to a computer via various transmission media. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used. On the other hand, as the program transmission medium, a communication medium in a computer network system for propagating and supplying program information as a carrier wave can be used. Here, the computer network is a WAN such as a LAN or the Internet, a wireless communication network, or the like, and the communication medium is a wired line such as an optical fiber or a wireless line.

  Further, the program included in the present embodiment is not limited to the one in which the functions of the above-described embodiments are realized by the computer executing the supplied program. For example, when the function of the above-described embodiment is realized in cooperation with an OS (operating system) running on a computer or other application software, the program is included in this embodiment. Further, when all or part of the processing of the supplied program is performed by the function expansion board or function expansion unit of the computer and the functions of the above-described embodiment are realized, such a program is included in this embodiment. .

  Hereinafter, various aspects will be collectively described as additional notes.

(Supplementary note 1) a first database for storing first coordinate data of defective semiconductor chips of a semiconductor wafer;
A second database for storing second coordinate data of semiconductor chips having defects in the semiconductor wafer;
A third database for storing third coordinate data of semiconductor chips obtained by statistically processing circuit characteristic values measured under different conditions of the semiconductor wafer;
A first computing unit that collates the first coordinate data with the third coordinate data to determine whether or not there is a correlation between the two,
A second computing unit that collates the first coordinate data determined to have no correlation with the third coordinate data by the first computing unit and the second coordinate data, and judges whether or not there is a correlation between them; Inspection system characterized by including.

  (Supplementary note 2) The inspection system according to supplementary note 1, further comprising a first standardization unit that performs an operation to match the coordinate system of the second coordinate data with the coordinate system of the first coordinate data.

  (Supplementary note 3) The inspection system according to Supplementary note 1 or 2, further comprising a first classification unit that extracts and classifies a specific distribution of the defective semiconductor chip based on the first coordinate data.

  (Supplementary note 4) The inspection system according to any one of supplementary notes 1 to 3, further comprising a second classification unit that extracts and classifies the singular distribution of the defect based on the second coordinate data.

  (Supplementary note 5) The inspection according to any one of supplementary notes 1 to 4, further comprising a third classification unit that extracts and classifies a singular distribution of the circuit characteristic values based on the third coordinate data. system.

(Additional remark 6) The said 1st calculating part provides a classification category to the said 1st coordinate data determined to have a correlation with the said 3rd coordinate data,
The inspection system according to any one of appendices 1 to 5, further including a fourth database that stores the first coordinate data to which the classification category is assigned.

(Appendix 7) Conducting an electrical test on a plurality of semiconductor chips on a semiconductor wafer to obtain first coordinate data of the defective semiconductor chip found in the electrical test;
Performing a defect inspection on the semiconductor chip, obtaining second coordinate data of the semiconductor chip of the defect found in the defect inspection;
For the semiconductor chip, measuring circuit characteristics under different conditions, statistically processing the circuit characteristic value to obtain third coordinate data of the semiconductor chip;
Collating the first coordinate data with the third coordinate data to determine the presence or absence of a correlation between the two,
And a step of collating the first coordinate data determined to have no correlation with the third coordinate data and the second coordinate data to determine whether or not there is a correlation between the first coordinate data and the second coordinate data.

  (Supplementary note 8) The inspection method according to supplementary note 7, further comprising a step of matching the coordinate system of the second coordinate data with the coordinate system of the first coordinate data.

  (Supplementary note 9) The inspection method according to supplementary note 7 or 8, further comprising a step of assigning a classification category to the first coordinate data determined to have a correlation with the third coordinate data.

  According to the present case, the correlation between the defect distribution pattern of the semiconductor wafer discovered by the defect inspection and the distribution pattern of the defective semiconductor chip discovered by the electrical test can be obtained with a very high accuracy and with higher accuracy. This can be performed in a short time, and a highly reliable semiconductor device is realized.

DESCRIPTION OF SYMBOLS 1 Inspection system 2 Inspection apparatus 3 Test apparatus 4 Circuit measurement apparatus 11 Data management server 12 1st application analysis server 13 2nd application analysis server 14,15 LAN
21 Standardization unit 22 Defect database 23 Test result database 24 Circuit measurement database 31 Summary unit 32 First management knowledge 33 Statistics calculation unit 34 Second management knowledge 41 First classification unit 42 Second classification unit 43 Third classification unit 44 1 computing unit 45 1st knowledge database 46 2nd computing unit 47 2nd knowledge database

Claims (5)

A first database storing first coordinate data of defective semiconductor chips of the semiconductor wafer;
A second database for storing second coordinate data of semiconductor chips having defects in the semiconductor wafer;
A third database for storing third coordinate data of semiconductor chips obtained by statistically processing circuit characteristic values measured under different conditions of the semiconductor wafer;
A first computing unit that collates the first coordinate data with the third coordinate data to determine whether or not there is a correlation between the two,
A second computing unit that collates the first coordinate data determined to have no correlation with the third coordinate data by the first computing unit and the second coordinate data, and judges whether or not there is a correlation between them; Inspection system characterized by including.   2. The inspection system according to claim 1, further comprising a first standardization unit that performs an operation of matching a coordinate system of the second coordinate data with a coordinate system of the first coordinate data. The first calculation unit assigns a classification category to the first coordinate data determined to have a correlation with the third coordinate data,
The inspection system according to claim 1, further comprising a fourth database that stores the first coordinate data to which the classification category is assigned. Performing an electrical test on a plurality of semiconductor chips of a semiconductor wafer to obtain first coordinate data of the defective semiconductor chip found in the electrical test;
Performing a defect inspection on the semiconductor chip, obtaining second coordinate data of the semiconductor chip of the defect found in the defect inspection;
For the semiconductor chip, measuring circuit characteristics under different conditions, statistically processing the circuit characteristic value to obtain third coordinate data of the semiconductor chip;
Collating the first coordinate data with the third coordinate data to determine the presence or absence of a correlation between the two,
And a step of collating the first coordinate data determined to have no correlation with the third coordinate data and the second coordinate data to determine whether or not there is a correlation between the first coordinate data and the second coordinate data.   5. The inspection method according to claim 4, further comprising a step of assigning a classification category to the first coordinate data determined to have a correlation with the third coordinate data.

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