JP2004096121A - Method of semiconductor defect analysis and method for specifying causes of semiconductor defects - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To utilize electrical test results of a wafer effectively, and identify the causes of defects adequately and promptly. <P>SOLUTION: A wafer map 10 comprising non-defective and defective categories for each die is used, which is a result of electrical tests of a wafer; and the defective category are classified into a process-margin origin region 11 and a foreign-substance origin region 11 from proximity nature of the category; and then, for example, measurement points of a size examination of the wafer 21 are sorted into measurement points 32 belonging to the process-margin origin region 11 and measurement points 31 belonging to the foreign-substance origin region 11. Then, a histogram 13 on the measurements of the size at the measurement points 32 belonging to the process-margin origin region 11 and a histogram 14 on the measurements of the size at the measurement points 31 belonging to the foreign-substance origin region 11 are prepared; and the histograms 13, 14 are compared with each other; thereby causes of the process-margin origin defects or the foreign-substance origin defects are identified. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to production control, quality control, and failure analysis in a wafer manufacturing line for semiconductors and the like. In particular, the results of electrical inspection for each die of a wafer are effectively utilized for production control, quality control, and failure analysis, and The present invention relates to a method for narrowing down a cause of a semiconductor defect which can narrow down the cause of the defect.

Conventionally, when utilizing the results of electrical inspection on a semiconductor or other production line for production control, quality control, and failure analysis, it is common to directly use the yield value. Correlation analysis with in-line inspection results is a great clue. However, the yield value contains various components, and in recent semiconductors that manufacture minute circuits using complex processes, the yield value alone can be used as a production management index or a clue for failure analysis. It has become insufficient.

Therefore, for the purpose of the above, a method of separating components of yield has been proposed (for example, see Non-Patent Document 1).

The method is mathematically (yield) = (yield due to process margin) * (yield due to foreign matter)
This is a method of approximating a curve. However, since this curve is approximated by only a few points, the calculation error is extremely large and cannot be said to be practical. In addition, the yields due to the process margin and the yields due to the foreign particles obtained here are not graphed in time series or graphed in the order of the wafer numbers to be used as an index for production control or quality control. Moreover, according to the component separation method described in the above-mentioned document, since the area within the wafer surface is not two-dimensionally separated, the result cannot be used for two-dimensional analysis within the wafer surface.

(4) It has been proposed that it is effective to analyze the yield separately for each two-dimensional location in the wafer plane (for example, see Non-Patent Document 2).

However, since this method only determines the location artificially, it is only a yield analysis for each location such as near the center or periphery of the wafer surface, and it can not be said that the components of the electrical inspection result are separated. Was.
Allan Y. Wong, “Statistical Micro Yield Modeling” Semiconductor International pp.139-148 (1996) Nick Atchison and Ron Ross, “Wafer Zone Based Yield Analysis,” pp. E51-E54 International Symposium on Semiconductor Manufacturing, Proceedings (1997)

The most important thing about production control, quality control, and failure analysis in semiconductor and other wafer production lines is to quickly find the cause of low yield of product devices, take countermeasures to achieve high yield, and high yield. Is always maintained.

For this purpose, it is necessary to be able to easily understand the yield of wafers on the production line and to use it as a guideline for production control and quality control. When the yield due to the process margin is low, the management of the manufacturing site is performed with the priority given to increasing the yield due to the process margin. When the yield due to the foreign matter is low, the analysis of the foreign matter data should be focused on in order to take measures against the foreign matter. If the shot dependency at the time of exposure is found, the yield can be improved by analyzing the parameters of the exposure apparatus. In addition, by dividing the wafer map into a process margin area and a foreign matter area, and analyzing various data for each area, it is possible to specify what caused the process margin defect and where it occurred. Can be.

However, conventionally, there has been no one that can accurately and quickly find the cause of a semiconductor defect.

The present invention has been made in view of the above points, and its purpose is to use a result of an electric test as a final test of a wafer in a wafer manufacturing process or a result of an in-line inspection and a result of the electric test. It is an object of the present invention to provide a method of narrowing down the cause of a semiconductor defect which makes it possible to narrow down the cause of a semiconductor defect accurately and quickly by using the method.

Another object of the present invention is to provide a method of narrowing down the cause of a semiconductor defect, which is adapted to narrow down the cause of the semiconductor defect accurately and promptly based on the result of the electric test.

In order to achieve the above object, the present invention provides a method of manufacturing a plurality of different regions based on the distribution of map components from a wafer map of a non-defective product or a defective product as a result of an electrical inspection in a wafer manufacturing process of a semiconductor or the like. Divide the area to be set, sort the results of inline inspection such as parametric inspection, dimensional inspection, foreign substance inspection, appearance inspection, film thickness inspection, alignment inspection into each area, and compare the data distribution of the sorting result for each area To narrow down the cause of semiconductor failure.

Further, in the present invention, in a wafer manufacturing process of a semiconductor or the like, a plurality of different regions are set based on the distribution state of the map components from wafer maps of non-defective products and defective products which are the results of electrical inspection. The yield of each map component is quantitatively calculated and totalized from the result of the area division, and the totalized result is output to narrow down the cause of the semiconductor defect. At this time, the results of quantitatively separating the components from the results of the electrical inspection are tabulated for each certain period, such as weekly, and the tabulated results are output. And the results of quantitative component separation of the yield from the results of the electrical inspection are tabulated for each wafer number in the lot, and the results are output. Identify and quantitatively separate the yields from the results of electrical inspections, aggregate the results for each unit of manufacturing equipment, and analyze the aggregated results by dispersion analysis to detect differences between equipment units. The cause of the failure is narrowed down.

Further, in the present invention, in a semiconductor wafer manufacturing process, a non-defective / defective product category is superimposed for each die in a mask at the time of exposure from a wafer map of a non-defective / defective product as a result of an electrical inspection, and a histogram is calculated. By omitting the data of wafers that have differences in the calculated values between the dies in the mask from the results of the electrical inspection, the above method is performed to increase the reliability of component separation due to foreign matter and process margins, and to narrow down the causes of failure. It is intended to improve accuracy.

In order to achieve the above and other objects, the present invention seeks continuity of the same defective category in a wafer map of a non-defective product or a defective product, which is a result of an electrical inspection, in a wafer manufacturing process of a semiconductor or the like. By detecting the area where the defective die is adjacent to the area and calculating the logical sum of the areas detected for each defective category as the process margin area and the other area as the foreign matter area, the non-defective and defective products as the result of the electrical inspection are obtained. Is divided into regions. The result of such area division is used for failure analysis, and further, the yield due to foreign matter and the yield due to process margin are calculated from these areas, thereby narrowing down the cause of failure.

Further, in the present invention, in a wafer manufacturing process of a semiconductor or the like, a histogram is obtained by superimposing non-defective / defective product categories for each die in a mask at the time of exposure from wafer map data of non-defective / defective products obtained as a result of electrical inspection. By calculating the wafer, the total number of wafers having a difference in the calculated values among the dies in the mask can be identified for each exposure apparatus, thereby making it possible to identify the exposure apparatus in which a mask abnormality has occurred, and to summarize the totaled result as a graph. By outputting, the cause of the failure is narrowed down.

電 気 In semiconductor manufacturing, electrical inspection is the final inspection in the wafer manufacturing process, and several hundreds of tests are sequentially performed on all the dies on the wafer just before cutting the wafer into chips. In this electrical inspection, the defective dies are classified into dozens of defect categories based on the content of the defect, and a wafer map of the defect category can be obtained.

Then, based on the distribution of the map components (categories) of the wafer map, a plurality of regions within the wafer surface, that is, a process margin region and a foreign matter region are divided into regions based on their adjacencies. The component is separated into the yield resulting from the process margin and the yield resulting from the foreign matter. By graphing and outputting these yields with the components separated, it is possible to understand in what condition the wafer product is being manufactured at the manufacturing site, and therefore, what measures should be taken now to improve the product It is possible to obtain an index indicating whether the retention can be improved.

Utilizing the results of such area division, the results of in-line inspection such as parametric inspection, dimension inspection, film thickness inspection, alignment inspection, appearance inspection, and foreign substance inspection using TEG are sorted for each of these areas. By comparing with, the cause of the failure can be ascertained. For example, by sorting the dimension inspection results at a plurality of measurement points into the process margin-caused region and the foreign matter-caused region, and comparing the sorting results for each of these regions, it is possible to find clues to identify the cause of the process margin failure. .

Further, by comparing the shot dependency at the time of exposure for each unit of the exposure apparatus and comparing them, it is possible to find out the difference between the units, and to classify each category of non-defective and defective products, which is the result of the electrical inspection, into each shot at the time of exposure. The difference between the dies is obtained by superimposing the total for each die and totaling for each die in the shot. If the difference is large, it is known that there is a shot-dependent defect. The fact that the shot dependency is large indicates that measures must be taken for the exposure apparatus. In addition, the accuracy of the yield component separation can be improved by removing the shot-dependent wafer when performing the yield component separation. Can be improved.

Furthermore, by utilizing it in computer systems such as production management systems and quality management systems, it is possible to provide useful information to engineers responsible for failure analysis and engineers responsible for production management, and to speed up failure analysis. Can be performed.

According to the present invention, in production control and quality control of semiconductors, a wafer map of a failure category, which is a result of an electrical inspection, is two-dimensionally separated into a process margin area and a foreign matter area, thereby efficiently narrowing down defects. Can do it.

Further, according to the present invention, the process margin-based yield and the foreign-matter-based yield are calculated from the results obtained by dividing the area into the process margin-based area and the foreign-matter-based area, and the calculated yield is calculated for each term, for each facility, and for each wafer number. By outputting the result of the aggregation, it is possible to identify items that need to be dealt with, and to quickly identify the cause of the defect.

Furthermore, according to the present invention, it is possible to specify a shot-dependent defect at the time of exposure, and it is possible to improve the accuracy of the yield component separation result by removing the shot-dependent wafer from the data. .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking a wafer manufacturing process of a semiconductor or the like as an example.

The first embodiment of the method of narrowing down the cause of a semiconductor defect according to the present invention is to perform a final inspection of a wafer, which is a final inspection of the wafer, for each die (a product unit before cutting into a chip unit), and to perform the inspection on a wafer production line. The cause of the defect is narrowed down by reflecting the result of a series of in-line inspections performed. FIG. 2 shows a system configuration and a data flow for executing this embodiment.

In the drawing, at least one of an in-line inspection such as a visual inspection 52, a dimensional inspection 53, a film thickness inspection 54, a mask alignment inspection 55, and a foreign matter inspection is performed in each step of the manufacturing line. In the final stage, the parametric inspection by the TEG is performed. The inspection results of these inline inspections are stored in the database 63 by being divided for each wafer number and each lot number, and the inspection results of the parametric inspection by the TEG are also stored in the database 62. Is stored in

In the final stage of the production line, an electrical test (tester) 51 is performed for each die of the wafer, and the test results are stored in the database 61, sorted for each wafer number and for each lot number. In this case, the defective die are classified according to the type (category) of the defect, and the category and the non-defective product are stored in the database 61 as a divided map (this is called a wafer map).

Using the wafer map, the defect map area dividing unit 64 performs a process of dividing the die existing area of the wafer into a process margin area and a foreign matter area, and uses the processing result to narrow down the cause of the defect. is there.

Therefore, first, a specific example of a method of dividing a region into a process margin caused region and a foreign matter caused region using a wafer map stored in the database 61 will be described.

FIG. 3 shows a specific example of a wafer map of a certain wafer stored in the database 61, in which the total number of dies is 218 and the category of each die is shown. Here, “Category A” indicates a die whose drive system is defective, “Category B” indicates a die whose DC system is defective, “Category C” indicates a die whose AC system is defective, and “Category D” indicates that the timing system is defective. Each of the defective dies is indicated, and “category /” indicates a good die.

FIG. 4 is a flowchart showing a method of electrical inspection for setting such a category.

The electrical inspection is the final inspection of the wafer manufacturing process.Several hundred items of tests are sequentially performed on all the dies on the wafer just before cutting the wafer into chips. Are classified into the above five categories.

In FIG. 4, first, an electrical test is performed on each die of a wafer that has passed through a manufacturing line, and a test is performed to determine whether a die to be tested has a category A defect (see FIG. 4). Step 301). This test is performed to determine whether the most critical drive circuit as a chip is not operated due to a short circuit or disconnection. If the defect cannot be repaired (step 302), the category of the die to be tested is determined. Is set to “A” (step 303). If such a defect does not exist, or if it can be repaired, the process proceeds to the next category B test (step 304). This is a test for determining whether a fatal DC system defect exists next to the category A. If the defect exists and cannot be repaired (step 305), the die to be tested is checked. The category is set to "B" (step 306). In the same manner, tests of category C (presence of AC system failure) and category D (presence of timing system failure) are sequentially performed (steps 307 and 310). 308, 311), data with a category of "C" or data with a category of "D" (steps 309, 312). If any defect does not exist, or if there is any defect, it can be repaired (step 309, 312). 311), the category of the die to be inspected is set as a non-defective product “/” (step 313). When the test for all the dies of the wafer to be inspected is completed (step 314), a wafer map of a category as shown in FIG. 3 is obtained, which is assigned to this wafer to be tested in the database 61 (FIG. 2). Is stored at the specified address.

From the wafer map obtained as described above, a region is divided into a process margin origin region and a foreign matter origin region on the wafer (process 71 in FIG. 2). This shows the definition of the foreign matter originating region.

In the figure, a defective area continuously occurring at a certain position on a wafer due to a process margin due to a process design error such as a variation in dimensions or film thickness is referred to as a process margin area. 11 is defined. On the other hand, there is a defect that does not occur continuously at such a certain position but randomly occurs on the wafer. Usually, such randomly generated defects are caused by the occurrence of foreign substances such as film peeling due to equipment troubles or process defects (this is referred to as foreign matter-induced defects). An area where a serious defect occurs is defined as a foreign matter-caused area 12. The foreign matter originating region 12 also includes a good die of the good product category “/”. Therefore, the foreign matter originating region 12 is the entire remaining region other than the process margin originating region 11. Needless to say, foreign matter is also generated in the process margin-caused region, so that the process margin-caused region also includes a defect due to the foreign material (a foreign matter-caused defect).

FIG. 6 is a diagram showing a specific example of a method of dividing the process margin-caused region and the foreign matter-caused region, using the wafer map shown in FIG. 3 as an example.

When the failure categories of the adjacent dies are equal for each of the failure categories A to D, it is determined that these dies are not two-dimensionally randomly generated failures, and all of them are included in the process margin area. If the category of the adjacent die is different from the defective category of the die surrounded by these four dies, the enclosed die is determined to be a randomly generated defect, and is included in the foreign matter-caused region.

FIG. 6 (a) is for obtaining the process margin originating area from the category A, and the shaded one of the category A is included in the process margin originating area. Similarly, FIG. 6B shows the category B included in the process margin originating area by shading, FIG. 6C shows the category C included in the process margin originating area, and FIG. The categories D included in the margin-caused region are shaded. 6 (a) to 6 (d) are combined (logical sum) to form the entire area of the process margin originating area, which is shown as a shaded area in FIG. 6 (e). ing. The area not shaded is a foreign matter-caused area.

FIG. 7 is a diagram showing a specific example of a method for determining the continuity of each defective category.

In FIG. 9A, the category A is targeted in the wafer map 601 in which the dies are arranged in a grid pattern, and the die of the defective category A exists adjacent to the category A as shown by hatching. Shall be. The wafer map 601 is scanned from left to right on each row from above to search for a category A die. When the first die 602a of the category A is found, it is determined whether or not the die adjacent to the die 602a is the same category A.

In this case, there are four dies adjacent to one die, up, down, left and right, but the determination order is right, lower, left, and upper as shown in FIG. 7B.

Therefore, in FIG. 7A, for the die 602a found first, the category of the die 602b on the right side is determined first. In this case, since the die 602b is also a category A, it is determined to be the same category A as the die 602a. Next, the category on the right side of the second die 602b is determined. Since this die is not the category A, the category of the lower die 602c is determined. Since the die 602c is of category A, it is determined that the die is of the same category A as the die 602a. In the same manner, the category of the adjacent die is sequentially determined according to the rule shown in FIG. 7B, and the die of the same category A as the die 602a is searched.

When there is only an adjacent die of the same category A, such as the die 602d, there is only a die that has already been determined. In this case, the process returns to the die 602e) so that the determination order proceeds in another direction.

In this way, it is possible to search for a group of dies in the same category A that are adjacent to each other. Then, the area occupied by the group of dies of category A is set in advance and compared with a threshold value. When the area is equal to or larger than the threshold value, the group of dies is assumed to belong to the process margin-caused region. Here, the threshold value is a value of the area of the two dies, but is not limited thereto. However, if the threshold is set to a value equal to the area of two dies, if two or more dies of the same category are adjacent to each other, these dies belong to the process margin-caused region.

When the search for the above-mentioned one set of dies in category A is completed, the search scan for dies in category A is restarted from the die that has not been searched yet and becomes the leading die in the above-described scanning order. When the search for the die of the category A is completed, the search is similarly performed for the other categories, so that the die area of the wafer as a whole, as shown in FIG. That is, it is divided into regions.

The process margin-caused yield and the foreign matter-caused yield are defined for the process margin-caused region and the foreign matter-caused region divided as shown in FIG. 5, respectively, as follows.

The yield in the foreign matter-derived area 12, that is, the foreign matter-derived yield is defined by the following equation (1):
Foreign matter-induced yield = (number of good dies in foreign matter-induced area 12) / (total number of dies in foreign matter-induced area 12) ... (1)
The yield due to the process margin is given by the following equation (2).
Yield due to process margin = (total yield) / (yield due to foreign matter) ... (2)
Is defined by However,
Overall yield = (the number of good dies in the entire wafer 21) / (the total number of dies in the entire wafer 21) (3)
It is. In the specific example shown in FIG. 3, the yield due to the process margin is 42.5%, and the yield due to the foreign matter is 45.1%.

In this embodiment, the cause of the wafer failure is narrowed down by using the results of the electrical inspection performed as described above. First, the result of the electrical inspection is compared with the result of the in-line inspection to determine the failure of the wafer. A first embodiment of the method of narrowing down the cause of a semiconductor defect according to the present invention, which narrows down the cause, will be described in detail.

FIG. 1 shows a first embodiment in which a measurement value of a dimensional inspection, which is one of the in-line inspections, is analyzed to narrow down the cause of the defect. Processing of the filtering unit 75 and the comparison unit 76 in FIG. 2 performed using the area division result of the wafer map obtained by the processing of the division unit 71 and the result of the dimensional inspection 53 of this wafer stored in the database 63 It is.

In FIG. 1, the wafer map 10 of the wafer to be analyzed is divided into the process margin area 11 and the foreign matter area 12 by the processing (FIG. 2) of the defect map area dividing unit 71 as described above. The dimensional inspection 53 (FIG. 2) measures whether or not the wafer is processed to a designed size after exposure through each mask or after each etching in a wafer manufacturing process at a predetermined measurement point on the wafer 21. The position data of each measurement point and the measurement value (dimension value) at that measurement point are stored in the database 63 (FIG. 2) in association with each other. Here, the determined measurement points may be set for each die, may be set for each shot, or may be other than those. However, the measurement points may be uniformly distributed on the surface of the wafer 21. Set.

The filtering unit 75 (FIG. 2) sequentially reads out the position data of the measurement points from the database 63 and classifies them into the measurement points 32 belonging to the process margin area 11 and the measurement points 31 belonging to the foreign matter area 12. Next, the comparison unit 76 (FIG. 2) reads out the measurement values of the measurement points 32 belonging to the process margin originating region 11 from the database 63 and calculates the histogram 13 thereof. The measured values are read from the database 63, the histogram 14 is calculated, and the histograms 13 and 14 are compared. If there is a difference between the histograms 13 and 14, it can be found from this that the cause of the process margin defect is the dimension formation in the target process, and the exposure immediately before the dimension inspection used at that time is performed. Alternatively, it can be seen that measures against etching and the like are effective for improving the yield.

Here, as a result of comparing the illustrated histograms 13 and 14, it can be seen that the distribution of the dimension measurement values in the process margin-caused region 11 is larger than the distribution in the foreign matter-caused region 12. Can be determined to be due to large dimensions. Also, as shown in the graphs of histograms 13 and 14 in FIG. 1, the measured value distribution in the foreign matter-caused region 12 and the measured value distribution in the process margin-caused region 11 are displayed on the computer system (results in FIG. 2). The output unit 77) is extremely effective.

FIG. 8 is a view showing a second embodiment of the method of narrowing down the cause of a semiconductor defect according to the present invention. In this embodiment, a measurement value of a visual inspection which is another one of the inline inspections is analyzed to determine the cause of the defect. This is also done by narrowing down, but this is also the result of the area division result of the wafer map obtained by the processing of the defect map area division unit 71 in FIG. 2 and the result of the visual inspection 52 of this wafer stored in the database 63. This is a process performed by the filtering unit 75 and the comparing unit 76 in FIG. Here, the data of the defect detection position by the appearance inspection and the type of the defect (foreign matter, disconnection, non-opening, etc.) are stored in the database 63 in association with each other.

In FIG. 8, as in the case of the dimension inspection 53, the filtering unit 75 reads the detection position data of the defect 22 from the database 63, and determines the defect 34 belonging to the process margin due area 11 and the defect 33 belonging to the foreign matter due area 12. Classify. Then, the comparison unit 76 calculates a histogram 15 corresponding to the type of the defect 33 belonging to the foreign matter-caused region 12 and a histogram 16 corresponding to the type of the defect 34 belonging to the process margin-caused region 11. Compare. Then, based on the difference between the histograms 15 and 16, the cause of the defect is narrowed down.

In the case of the histograms 15 and 16 shown in FIG. 8, the non-opening defect is small in the distribution of defects in the foreign matter-caused region 12, but the non-opening defect is frequent in the distribution of defects in the process margin-caused region 11. . Therefore, it can be seen that the cause of the process margin defect is the non-opening, and the cause of the non-opening can be determined to prevent the process margin defect.

Here, the results of the visual inspection 52 are classified for each type of defect to create a histogram, and the histograms are compared. However, the histogram is not the type but data representing the defect characteristics such as the size of the defect. It is also effective to compare the distribution differences between the process margin area 11 and the foreign matter area 12 to find out the cause of the defect. In this case, the cause of the defect can be determined in detail by observing the defect corresponding to the difference in data with an SEM or an elemental analyzer. Also, as shown in the histograms 15 and 16 shown in the figure, it is extremely difficult to display the distribution of the defects in the foreign matter-caused region 12 and the defects in the process margin-caused region 11 on the computer system (result output unit 77 in FIG. 2). It is valid.

FIG. 9 is a view showing a third embodiment of the method of narrowing down the cause of a semiconductor defect according to the present invention. In this embodiment, the result of the dimension inspection 53 is analyzed to narrow down the cause of the defect. Different from the first embodiment shown, the present embodiment uses the results of dimensional inspection of a plurality of wafers.

In the figure, the dimensional inspection 53 is generally performed at a plurality of measurement points determined on a wafer, and focuses on one specific measurement point designated (hereinafter, designated measurement point). In the filtering unit 75, first, the position data of the designated measurement point is read from the database 63 for each wafer, and it is determined whether each designated measurement point belongs to the process margin area 11 or the foreign matter area 12. The designated measurement point is divided into a wafer group 41 belonging to the process margin origin area 11 and a wafer group 42 belonging to the foreign substance origin area.

Then, a histogram of the dimension measurement value at the designated measurement point of the wafer group 41 and a histogram of the dimension measurement value at the designated measurement point of the wafer group 42 are created, and the comparison unit 76 compares the respective distributions. If there is a difference between these distributions, it is known that the cause of the process margin defect is a defect depending on the size, and it can be determined that the cause is a focus or offset of the exposure apparatus.

1 and 9 relate to dimensional inspection, but similarly, parametric inspection using TEG (the inspection result is stored in the database 62 of FIG. 2) and film thickness inspection 54 As in the case of the dimension inspection 53, the in-line inspection using the measured value of a fixed measurement point on the wafer as the inspection result is performed by performing the analysis in the same manner as described above, so that the process margin or the foreign matter is generated. The cause of the defect can be narrowed down.

Next, a description will be given of an embodiment in which the cause of failure is roughly classified using only the results of the electrical inspection and used as an index for quality control and failure analysis.

FIG. 10 is a flowchart showing a fourth embodiment of the method of narrowing down the cause of a semiconductor defect according to the present invention. This embodiment narrows down the cause of the defect based on the temporal transition of the yield between the process margin area and the foreign matter area. Things.

Referring to FIG. 7, the defect map area dividing section 71 (FIG. 2) divides an area into a process margin area and a foreign matter area as described above (step 400). The calculation unit 72 (FIG. 2) obtains the particle-based yield and the process margin-based yield for each wafer by the above equations (1) and (2) (step 401), and the data totaling unit 73 (FIG. 2) Then, the average of these yields for each fixed period (for example, daily or weekly) is totaled, and the totaling result is plotted to create a transition diagram of the yield (step 402). The data of the yield transition diagram is displayed on the computer system (result output unit 77 (FIG. 2)). From the displayed contents, the relative tendency of the yield indicates that the cause of the wafer failure is caused by the process margin. It is determined whether the defect is caused by a foreign matter (step 403). In the former case, a countermeasure against a process-induced defect is performed (step 404) to improve the process margin-induced yield. A defect countermeasure is implemented (step 405) so that the yield due to foreign matter can be improved.

From the yield transition diagram shown, around January, the yield due to the process margin is extremely low, and the measures against the yield due to the process margin contribute to higher yields of the entire product than the measures against the yield due to foreign matter. What can be done can be read from this graph. In addition, since April, the yield due to the process margin is high and the yield due to the foreign matter is low, so that measures against the foreign matter-based yield can contribute to increasing the yield of the entire product. In this way, since it is possible to know below what measures should be taken to improve the yield, it is effective to utilize this for budgeting and human resource administration for improving the yield.

FIG. 11 is a flowchart showing a fifth embodiment of the method of narrowing down the causes of semiconductor defects according to the present invention. This embodiment is based on the difference in distribution between the process margin yield and the foreign matter yield for each manufacturing facility. It narrows down the cause.

In this embodiment, similarly to the previous embodiment, the wafer surface is divided into a process margin area and a foreign matter area, and the calculation unit 72 shown in FIG. The wafer is sorted for each of the first unit, the second unit of the equipment, the third unit of the equipment,...), And the yield due to the process margin and the yield due to the foreign matter of the wafer belonging to each manufacturing equipment are calculated, and the data of FIG. The results are totaled by the unit 73 (step 500), and the distribution of the resulting yield is graphed for each manufacturing facility (step 501). The data of such distribution is displayed on the result output unit 77, and it is possible to determine a manufacturing facility causing a defect from the displayed contents (step 502).

In the example shown in the figure, although there is no difference in the yield due to the process margin between the manufacturing facilities, it can be seen that the yield due to the foreign matter is lower in the first facility than in the other manufacturing facilities. This difference can be detected by calculating an analysis of variance such as the F test. From this, by investigating the cause of foreign matter generation of the first equipment, it is possible to take measures against a decrease in yield, and thereby to increase the yield.

FIG. 12 is a flowchart showing a sixth embodiment of the method of narrowing down the causes of semiconductor defects according to the present invention. In this embodiment, the process margin-based yield and the foreign matter-based yield calculated for each wafer number in a lot are calculated. The cause of the defect is narrowed down based on the tendency.

In the figure, a process in which the calculation margin 72 calculates the yield due to the process margin and the yield due to the foreign matter of the wafer manufactured in a certain period as described above, and the data summation unit 73 calculates the same wafer number of each lot for the same wafer number Average values of the margin-based yield and the foreign-material-based yield are totaled, plotted and graphed for each of the wafer numbers 1, 2, 3,... (Step 600). In this case, the average value of the entire yield of the wafer is similarly obtained and displayed for each wafer number. This totaling result is displayed on the result output unit 77 (step 601), and the cause of the defect can be narrowed down from the tendency of the graph (step 602).

In the case of the graph shown in the figure, the number of wafers in one lot is 25, indicating that the larger the wafer number, the lower the overall yield tends to be. If the overall yield is separately shown as a process margin-based yield and a foreign matter-based yield, the foreign matter-based yield completely matches the overall yield, and the larger the wafer number, the larger the overall yield. It can be seen at a glance that the cause of the decrease in retention is due to foreign matter. By analyzing foreign matter data based on the results of this graph, the cause of the defect can be determined without performing another analysis.

FIG. 13 is a diagram showing a specific example of a result of analyzing foreign substance data stored in the database 63 of FIG. 2 based on the result of FIG.

In the figure, first, for each of the steps P1, P2, and P3 in which the foreign substance inspection is being performed, the average of the number of foreign substances generated immediately before the inspection is calculated for each same wafer number in each lot. As a result, if it can be confirmed that the number of foreign substances increases as the wafer number increases in the processes P1 and P3, it is understood that the number of foreign substances in these processes P1 and P3 depends on the wafer number. On the other hand, it is understood that the process P2 has no relation to the wafer number.

(4) Therefore, a correlation analysis between the number of foreign particles in the processes P1 and P3 and the yield due to the foreign particles is performed. As a result, as shown in the figure, if it is found that there is a strong correlation between the number of foreign substances and the yield due to the foreign substances in the process P1, if the foreign substances which are a factor that lowers the yield before the foreign substance inspection in the process P1, are found. The attachment can be specified, and the yield can be improved by taking measures against the attachment of the foreign matter.

FIG. 14 is a view showing a seventh embodiment of the method for narrowing down the cause of a semiconductor defect according to the present invention. It narrows down using the results of the electrical inspection.

(4) In the exposure of a semiconductor wafer, a circuit pattern is printed by projecting light onto the wafer through a filter having a pattern called a mask or a reticle. A mask is prepared so that a plurality of dies can be formed by one irradiation of the exposure apparatus. In the example shown in FIG. 14, the mask 45 includes four die portions, and four dies are formed by one irradiation through the mask 45.

Here, the shot dependency means that when light is irradiated on a wafer through a mask, four dies are not correctly and uniformly formed depending on the irradiation state. If the individual dies are not uniformly formed, it is considered that the cause is a defect of a mask used in this exposure, distortion of a lens of an exposure apparatus, misalignment at the time of exposure, and the like.

In the seventh embodiment, first, in FIG. 14, a die formed on a wafer is divided into a die formed by a shot of a first portion of the mask 45 (this is referred to as a die d1) and a die The die formed by the shot of the portion 2 (this is referred to as die d2), the die formed by the shot of the third portion of the mask 45 (this is referred to as the die d3), and the die formed by the shot of the fourth portion of the mask 45. Dies formed by shots (this is called die d4). All of the dies are set to the categories shown in FIG. 3 by the electrical inspection, but the categories A, B, C, and D shown in FIG. 3 are set for each of the dies d1, d2, d3, and d4. The occurrence rates of D and / are determined, and as shown in FIG. 14, the occurrence rates of the dies d1, d2, d3, and d4 are tabulated for each category and output to the result output unit 77.

In this case, according to the tabulation result shown in the figure, it is understood that the number of non-defective products is small in the die d3, and the number of defective categories B is increased only in the die d3. Therefore, it is understood that the yield can be improved by investigating the cause of the occurrence of the category B in the die 3.

On the other hand, the shot dependency at the time of exposure obtained in this way is shown in FIG. 15, and when the yield of each die is obtained and shown in a table, the wafer having the shot dependency can be known. A wafer having a shot dependency can be extracted from a difference in yield for each die. Outputting the table shown in FIG. 15 by the computer system is also highly effective.

By removing the extracted wafer from the data on the process margin-based yield and the foreign matter-based yield shown in FIGS. 10, 11, and 112, the shot dependency is removed from the process margin-based yield and the foreign matter-based yield. Therefore, the yield caused by the process margin and the yield caused by the foreign matter can be more effectively utilized. Also, in the case of performing the defect narrowing of the embodiment shown in FIGS. 1, 8, and 9, the accuracy of the analysis can be improved by removing and analyzing the wafer on which the shot dependency exists.

1 is a diagram showing a first embodiment of a method for narrowing down a cause of a semiconductor defect according to the present invention. FIG. 1 is a block diagram showing a specific example of a system configuration and a data flow for executing a semiconductor failure cause narrowing down method according to the present invention. It is a figure showing a specific example of a wafer map of a failure category of an electric inspection result in a wafer manufacturing process. 4 is a flowchart illustrating a specific example of testing for determining a failure category for obtaining the wafer map illustrated in FIG. 3. FIG. 4 is a diagram showing a specific example of defining a process margin originating region and a foreign matter originating region. FIG. 4 is a diagram showing a specific example of a method for dividing a process margin-caused region and a foreign matter-caused region based on the wafer map shown in FIG. 3. FIG. 7 is a diagram showing a specific example of a method for searching for the adjacentity of the same category for area division shown in FIG. 6. FIG. 6 is a diagram showing a second embodiment of the method for narrowing down the causes of semiconductor defects according to the present invention. FIG. 9 is a diagram showing a third embodiment of the method for narrowing down the cause of a semiconductor defect according to the present invention. 9 is a flowchart showing a fourth embodiment of the method for narrowing down the causes of semiconductor defects according to the present invention. 9 is a flowchart illustrating a fifth embodiment of a method for narrowing down a cause of a semiconductor defect according to the present invention. 13 is a flowchart showing a sixth embodiment of the method for narrowing down the cause of a semiconductor defect according to the present invention. FIG. 13 is a diagram showing a specific example of a method for analyzing foreign matter data from the results of the sixth embodiment shown in FIG. 13 is a flowchart showing a seventh embodiment of a method for narrowing down a cause of a semiconductor defect according to the present invention. FIG. 15 is a diagram illustrating a specific example of a method of detecting a shot-dependent wafer for exposure from the result of the seventh embodiment illustrated in FIG. 14.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 10 Wafer map 11 Process margin origin area 12 Foreign origin origin area 13-16 Histogram 21 Dimension inspection measurement point map 22 Visual inspection result map 31 Dimension inspection measurement point in foreign origin origin area 32 Dimension inspection measurement point in process margin origin area 33 Defects in foreign matter-caused area 34 Defects in process margin-caused area 41 Wafer group whose designated dimension inspection measurement point is a custody-induced area 42 Wafer group whose designated dimension inspection measurement point is a foreign matter-caused area 51 Tester group 52 Appearance Inspection Equipment 53 Dimension Inspection Equipment 54 Film Thickness Inspection Equipment 55 Alignment Inspection Equipment 61 Database for Utilizing Wafer Map of Defective Category 62 Database for Utilizing Parametric Inspection Results by TEG 63 To Utilize Inline Inspection Results Database 71 failure map area classification unit 72 step distillation calculator 73 data tabulation unit 74 correlation analysis unit 75 filtering unit 76 comparison unit 77 result output unit

Claims (9)

In the semiconductor wafer manufacturing process,
From the wafer map of the non-defective and defective products, which is the result of the electrical inspection of the semiconductor wafer in the manufacturing process, the wafer is divided into a plurality of regions based on the map components,
The results of in-line inspection of the wafer, such as parametric inspection, dimensional inspection, foreign material inspection, appearance inspection, film thickness inspection, alignment inspection, etc., are sorted for each of the regions divided based on the defect-causing component,
A method of narrowing down the cause of a semiconductor defect, comprising comparing data distributions of the results of the inline inspection for each of the sorted areas to narrow down the cause of a defect such as a semiconductor. In the semiconductor wafer manufacturing process,
From the wafer map of the non-defective and defective products, which is the result of the electrical inspection of the semiconductor wafer in the manufacturing process, the wafer is divided into a plurality of regions based on the map components,
Quantitatively calculate the yield for each area from the results of the area division,
A method of narrowing down the cause of a semiconductor defect, wherein the results of the calculation are totalized and output to narrow down the cause of the semiconductor defect. In claim 2,
It is characterized in that a result of quantitatively separating the components from the results of the electrical inspection is tabulated for each predetermined fixed period, and a fault countermeasure is prioritized from components to be countermeasured by outputting the tabulated result. To narrow down the cause of semiconductor failure. In claim 2,
The result of quantitatively component separation of the yield from the results of the electrical inspection is tabulated for each wafer number in the lot, and by narrowing down the cause of the yield drop depending on the wafer number by outputting the tabulated result, To narrow down the cause of semiconductor failure. In claim 2,
A semiconductor, wherein the result of quantitatively separating the components from the results of the electrical inspection is tabulated for each unit of the manufacturing facility, and the difference of the unit of the manufacturing facility is detected by performing a distributed analysis of the tabulated result. How to narrow down the cause of failure. In claim 2,
A histogram is calculated by superimposing categories of non-defective and defective products for each die in the mask at the time of exposure from a wafer map of non-defective products and defective products obtained as a result of the electric inspection,
A semiconductor, wherein the reliability of component separation caused by the foreign matter and the process margin is increased by removing data of a wafer having a difference in a value calculated between dies in the mask from the result of the electrical inspection. How to narrow down the cause of failure. In the semiconductor wafer manufacturing process,
The continuity of the same defect category in the wafer map data of the non-defective and defective wafers, which is the result of the electrical inspection of the semiconductor wafer in the manufacturing process, is searched, and an area where defective dies of the same category are adjacent to each other is detected. A method of narrowing down the cause of a semiconductor defect, wherein a logical sum of regions detected for each category is used as a process margin-caused region and other regions are used as a foreign matter-caused region for failure analysis. In claim 7,
A method of narrowing down a cause of a semiconductor defect, comprising calculating a yield caused by a foreign matter and a yield caused by a process margin, respectively, from the divided process margin caused area and the foreign matter caused area. In the semiconductor wafer manufacturing process,
A histogram is calculated by superimposing each category of non-defective and defective products for each die in the mask at the time of exposure from wafer map data of non-defective and non-defective products as a result of electrical inspection of a semiconductor wafer in a manufacturing process, and calculating a histogram in the mask. By summing up the wafers having different values between the dies for each exposure apparatus, it is possible to identify the exposure apparatus in which the mask abnormality has occurred, and to output the totaled result as a graph. To narrow down the cause of semiconductor failure.

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