JP2011008664A - Method and system for determining emc - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine EMC quality of a printed board and to narrow down parts for which countermeasures should be taken, of signal lines and wiring patterns.SOLUTION: A determination system of EMC includes a return loop area calculation part 104, a power supply-GND pattern end area calculation part 105, a stub length calculation part 106, a power supply-GND pattern area calculation part 107, and an EMC determination part 108. EMC conformity levels of signal lines on the printed board are digitized and displayed to narrow down parts for which countermeasures should be taken, of signal lines and wiring patterns, whereby required and sufficient countermeasures can be taken.

Description

  The present invention relates to an EMC (Electro Magnetic Compatibility) determination method and determination system when designing a wiring pattern of a printed circuit board.

  As a conventional EMC determination method and determination system, there is one that checks conformity to an EMC rule. FIG. 19 is a diagram illustrating a conventional EMC determination method described in Patent Document 1. In FIG.

  In FIG. 19, the wiring processing unit 14 includes a clock wiring pattern extraction unit 21 that extracts a clock wiring, a wiring layer detection unit 22 that detects the presence / absence of a power supply / GND layer in an adjacent layer of the wiring layer, and a power / An earth guard pattern detection unit 23 that detects a GND pattern when there is no GND layer, and a wiring error display unit 24 that displays an error in a wiring that violates the EMC rule that there is no GND pattern in the vicinity. When wiring is edited by the arithmetic processing unit 15 through the input / output device 13 for the data storage device 11 in which the wiring data is stored, an EMC error check is performed by the wiring processing unit 14 and an error is displayed on the display unit 12. The That is, this is a system for checking the presence or absence of a peripheral GND pattern, which is one of the EMC rules.

Japanese Patent No. 3119242

  However, in the conventional configuration, only whether or not the EMC rule is met is a problem, and how much the EMC rule is violated, for example, does not consider the degree of badness of the substrate end wiring. I cannot judge how much EMC is worsened by the violation. For this reason, there is a problem that the countermeasure points of the signal cannot be narrowed down and it takes too much time for the countermeasures or the countermeasures become excessive.

  The present invention solves the above-mentioned conventional problems, and by digitizing EMC factors for each signal line of a printed circuit board and displaying the EMC conformity level using this, a signal having a high priority is specified, Provided is an EMC determination method capable of efficiently taking measures against EMC, such as displaying a factor that deteriorates EMC.

In order to achieve the above object, an EMC determination method of the present invention is a processing method for designing a wiring pattern of a position of an electronic component mounted on a printed circuit board and a wiring pattern of a signal line between the electronic components using a CAD system.
Selecting an arbitrary signal line from printed circuit board data designed in the CAD system;
(A) calculating a return loop area for the selected signal line;
(B) calculating a power source / GND pattern edge area;
(C) calculating a stub length;
(D) calculating a power source / GND pattern area;
The method includes the steps of executing at least one of the steps (a) to (d) and displaying the executed calculation result corresponding to the signal line, and performing EMC determination of the printed circuit board.

  With this configuration, it is possible to quantify the factors that deteriorate EMC in the printed circuit board design stage and evaluation stage.

  As described above, according to the EMC determination method of the present invention, it is possible to specify a signal having a high priority by digitizing the EMC factor for each signal line of the printed circuit board and displaying the EMC conformity level using this. Thus, it is possible to efficiently take countermeasures against EMC, such as displaying a factor that deteriorates EMC.

The block diagram of the EMC determination system in Embodiment 1 of this invention Flow chart of EMC determination method in the first embodiment Explanatory drawing of the return loop area in the first embodiment (in the case of the same layer return) Explanatory diagram of return loop area in the first embodiment (in the case of discontinuous return) Explanatory diagram of the return loop area in the first embodiment (when there are other signal lines) Explanatory drawing of the return loop area in the first embodiment (when there is no same-layer return) Explanatory drawing of the return loop area in the first embodiment (when the wiring straddles layers) (A) Top view for explaining the end area of the power supply / GND pattern in the first embodiment, (b) A sectional view of FIG. 8 (a) Explanatory drawing of the stub length in the first embodiment (in the case of two branches) Explanatory drawing of the stub length in the first embodiment (in the case of 3 branches) Explanatory drawing of the power supply / GND pattern area in the first embodiment The figure explaining the display state of the EMC calculation result in the first embodiment The figure explaining the threshold value of EMC in the first embodiment The figure explaining the display state which distinguished the EMC calculation result in Embodiment 1 Block diagram of the EMC determination system in the second embodiment Flow chart of EMC determination method in the second embodiment Flow chart of EMC determination method in the third embodiment The figure explaining the display state of the EMC calculation result in Embodiment 3 Block diagram of a conventional EMC determination system described in Patent Document 1

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of an EMC determination system according to Embodiment 1 of the present invention. Printed circuit board data 102 is stored in the storage unit 101. The printed circuit board data 102 is designed using a wiring design CAD system, and is composed of data such as positions of electronic components mounted on the printed circuit board and wiring patterns for signal lines between the electronic components. The processing unit 103 includes a return loop area calculation unit 104, a power source / GND pattern end area calculation unit 105, a stub length calculation unit 106, a power source / GND pattern area calculation unit 107, and calculates EMC from these four calculation results. It is comprised from the EMC determination part 108 which determines a result. The display unit 109 includes means for displaying the result of the EMC determination unit 108 on the screen. The processing unit 103 is a system for executing each step of an EMC determination method described later.

  FIG. 2 is a flowchart of the EMC determination method according to Embodiment 1 of the present invention. In step S <b> 201, a signal line is selected from the printed circuit board data 102. Subsequently, for the selected signal line, a return loop area calculation (step S202), a power source / GND pattern end area calculation (step S203), a stub length calculation (step S204), and a power source / GND pattern are calculated. Area calculation (step S205) is executed. Next, in step S206, since calculation is performed for all signal lines on the printed circuit board, the process returns to step S201 to select another signal line and repeat the same calculation (steps S202 to S205). Finally, step S207 displays the signal line and EMC calculation results in numerical order from each calculation result. As a result, the priority order of signal lines that require EMC countermeasures and the factors that deteriorate EMC are clarified.

  In addition, although the case where all steps S202 to S205 are calculated has been described, at least one of steps S202 to S205 may be calculated. This is a process applied to the multilayer substrate in steps S203 and S205, and step S204 is a process in the case where there is a branch of the signal line. Therefore, it is not always necessary to execute the four steps. The four calculation orders may be rearranged and executed.

  Next, the calculation method in step S202 of FIG. 2 will be described with reference to FIGS.

  3 to 7 are diagrams showing a return loop area according to an embodiment of the present invention. It is a figure explaining calculation of the return loop area which is an area surrounded by a signal line and a GND pattern when a signal line is connected from the driver IC 302 toward the receiver IC 303.

  FIG. 3 is a view of the printed circuit board 300 as viewed from above, and shows an example in which the driver IC 302, the receiver IC 303, the signal line 301, and the GND pattern 304 are arranged in the first layer of the printed circuit board 300. The current flowing through the signal line 301 forms a return current in the GND pattern 304 that is closest to the wiring pattern of the signal line 301. That is, a return loop is formed between the signal line 301 and the GND pattern 306 of the GND pin 307 of the driver IC 302 from the GND pin 306 of the receiver IC 303. The area is calculated as a return loop area 305. The GND pattern is an example of a solid pattern, but may be a wiring pattern similar to a signal line.

  FIG. 4 is a view of the printed circuit board 300 as viewed from above, as in FIG. The difference from FIG. 3 is that the GND pattern closest to the point Pb on the signal line 401 is changed from the point Pd to the point Pe on the opposite side. That is, the GND pattern 404 on the point Pd side (the lower side in the figure) is the closest in the section from the point Pa to the Pb on the signal line 401, and the GND pattern 404 on the point Pe side (the upper side in the figure) is the closest in the section from the point Pb to the point Pc. Get closer. In such a case, the area 405 including the lower surface of the receiver IC 303 is calculated as the return loop area.

  FIG. 5 is a view of the printed circuit board 300 as viewed from above, as in FIG. The difference from FIG. 4 is that the GND pattern is divided into two parts 504a and 504b by the signal line 508 being arranged. These two GND patterns are connected via a via (through hole) by a GND line 504c provided in the inner layer of the printed circuit board. In this case, even if the GND is a wiring pattern, processing is performed in the same manner as the GND pattern, and the return loop area 505 for the signal line 501 is calculated as the illustrated region.

  FIG. 6 is a cross-sectional view of the printed circuit board 300. In this example, the driver IC 302, the receiver IC 303, and the signal line 601 are arranged in the first layer of the printed circuit board 300, and the GND pattern 604 is arranged in the second layer. Since the second-layer GND pattern 604 exists immediately below the wiring pattern of the first-layer signal line 601, the return loop area 605 with respect to the signal line 601 is directed to the thickness of the first and second layers of the printed circuit board 300. Calculate as the area represented by.

  FIG. 7 is a cross-sectional view of the printed circuit board 300. The driver IC 302 is arranged in the first layer, the receiver IC 303 is arranged in the fourth layer, and the GND patterns (704a, 704b) are arranged in the second layer and the third layer. Yes. In this example, the signal line 701a is connected to the signal line 701b in the fourth layer from the first layer through the via 709. The return loop area is calculated as an area obtained by adding the signal line 701a and the region 705a surrounded by the GND pattern 704a closest to the signal line, and the signal line 701b and the region 705b surrounded by the GND pattern 704b closest to the signal line. To do.

  An example of a method for calculating each area described with reference to FIGS. 3 to 7 will be described. The physical position data such as the position of the electronic component mounted on the printed circuit board 102 stored in the printed circuit board data 102 of FIG. 1 and the wiring pattern for the signal line between the electronic components is the minimum design unit (grid) of the wiring design CAD system. In general, it is designed in units of 0.1 mm. By using this grid, the area can be calculated by counting the number of squares of the minimum unit of 0.1 mm × 0.1 mm in the return loop region.

  Next, the calculation method in step S203 in FIG. 2 will be described with reference to FIG.

  FIG. 8 is a diagram showing a power source / GND pattern end area according to an embodiment of the present invention. FIG. 8A is a view of the printed circuit board 300 as viewed from above, and FIG. 8B is a cross-sectional view taken at points Pf and Pj in FIG. 8A and 8B, a driver IC 302, a receiver IC 303, and a signal line 801 are arranged on the first layer of the printed circuit board 300. FIG. The GND pattern 804 is arranged on the second layer of the printed circuit board 300. A region 804a indicated by a dotted line indicates the outline of the GND pattern 804 of the second layer. The power supply / GND pattern end area is calculated when the signal line 801 overlaps the power supply pattern or the GND pattern in a layer different from the layer where the signal line 801 is arranged. In FIG. 8A, since the contour of the GND pattern 804 closest to the section Pg to the point Pg of the signal line 801 corresponds to 804b, the power source / GND pattern end area in this section is 805a. Similarly, the power source / GND pattern end area from the point Pg to the point Ph is 805b, and the power source / GND pattern end area from the point Pi to the point Pj is 805c. Therefore, 805a, 805b, and 805c are added to the power supply / GND pattern edge area of the entire signal line 801. Although FIG. 8 shows the GND pattern as an example, the same calculation is performed for the power supply pattern. However, when the signal line protrudes from the outline of the power supply pattern or the GND pattern, the area of the section is set to zero.

  Next, the calculation method in step S204 in FIG. 2 will be described with reference to FIGS.

9 and 10 are diagrams showing stub lengths according to an embodiment of the present invention. The signal lines (901, 1001) are connected from the driver IC 302 to the plurality of receiver ICs 303. The stub length is calculated as a squared value of how far the signal line wiring pattern is centered on the average wiring distance from the first branch point to each receiver IC. When the wiring distance of x _i from the branch point to the receiver IC, the stub length is calculated by the following equation.

FIG. 9 shows an example in which the signal line 901 is branched into two. When the distance from the branch point P1 to P2 of the signal line 901 is L1, and the distance from the branch point P1 to P3 is L2, the stub length can be obtained by substituting the following values into Equations 1 and 2.
x ₁ = L1
x ₂ = L2
n = 2

FIG. 10 shows an example in which the signal line 1001 has three branches. The distance from the branch point P4 to P6 of the signal line 1001 is L3, the distance from the branch point P4 to the branch point P5 is L4, the distance from the branch point P5 to P7 is L5, and the distance from the branch point P5 to P8 is L6. Then, the stub length can be obtained by substituting the following values into Equation 1 and Equation 2.
x ₁ = L3
x ₂ = L4 + L5
x ₂ = L4 + L6
n = 3

  9 and 10 show the signal lines as straight lines for simplification, the actual wiring pattern is designed to be bent at 45 degrees or 90 degrees, and the distance between the actual wiring patterns is calculated. To calculate the stub length. In addition, the wiring is routed from the first layer of the printed circuit board to another layer through vias. In such a case, the actual physical wiring pattern distance is calculated and calculated.

  Next, the calculation method in step S205 in FIG. 2 will be described with reference to FIG.

  FIG. 11 is a diagram showing a power supply / GND pattern area according to an embodiment of the present invention. The printed circuit board 300 is viewed from above, and the driver IC 302, the receiver IC 303, and the signal line 1101 are arranged on the first layer, and the GND pattern 1104 and the power supply pattern 1109 are arranged on another layer of the printed circuit board 300. This is an example. A region 1110 in which the power supply pattern 1109 and the GND pattern 1104 which are driving power sources of the driver IC 302 and the receiver IC 303 overlap with each other in the upper and lower layer directions is a power supply / GND pattern area for the signal line 1101. The area of the power supply / GND pattern is not affected by the wiring pattern of the signal lines, the position of the IC, and the like, and is an area where the power supply pattern and the GND pattern overlap. Even when the power supply pattern or the GND pattern is a wiring, the area of the overlapping portion is calculated based on the wiring width and the wiring length.

  Next, EMC determination and display will be described with reference to FIGS.

  FIG. 12 is a diagram for explaining a display state of the EMC calculation result according to the embodiment of the present invention. This is an example in which the result calculated for each signal line is displayed on the display unit 109 based on step S201 to step S206 in FIG. The EMC determination unit 108 includes the result A of the return loop area calculation (step S202), the result B of the power source / GND pattern end area calculation (step S203), the result C of the stub length calculation (step S204), and the power source / GND. Any one or more of the results D of the pattern area calculation (step S205) are displayed for each signal line. Further, by rearranging and displaying the respective calculation results in numerical order, it is possible to identify signal lines that should be taken by EMC and items (A to D) that deteriorate the EMC level.

FIG. 13 is a diagram for explaining a table in which threshold values of items (A to D) according to an embodiment of the present invention are set. As a result of EMC calculation, when the return loop area of the signal line is small, the wiring pattern of the signal line is in the center with respect to the power supply pattern and the GND pattern, the stub length of the signal line is short, and the power supply / GND pattern is the minimum necessary EMC improves. This value empirically becomes (Equation 3) when the standard wiring length is 20 mm.
A = 20 mm × 0.1 mm (Formula 3)
B = 20mm × 10mm
C = 0
D = 20mm × 20mm

If a margin is added based on this standard value, the threshold value of each item (A, B, C, D) can be obtained by (Equation 4). Moreover, this calculation result is shown in FIG.
A ≧ 20 mm × 0.1 mm × 2 (Formula 4)
B ≦ 20mm × 10mm × 0.5
C ≧ 10
D ≧ 20mm × 20mm × 2

  FIG. 14 is a view for explaining display based on the threshold value of the EMC calculation result according to one embodiment of the present invention. The EMC determination unit 108 compares each item A to D with the threshold value shown in FIG. 13 and displays a colored display so that an item that violates the value is distinguished from other normal items. In addition, for each item, the signal lines may be rearranged and displayed in numerical order.

  According to this configuration, by calculating the return loop area, the power source / GND pattern end area, the stub length, and the power source / GND pattern area, the degree of violation of the four items of EMC is quantified and displayed for each signal line. In addition, in order to improve EMC quality at the printed circuit board design stage, it is possible to narrow down the countermeasures for signal lines and wiring patterns.

  In this embodiment, printed circuit board data is used as a calculation target. However, in consideration of the entire product, the cable is treated as a wiring by using the three-dimensional mechanism data including the cable and the casing structure, and the metal You may calculate each EMC factor by making a housing | casing into a GND pattern.

(Embodiment 2)
FIG. 15 is a block diagram of the EMC determination system according to Embodiment 2 of the present invention, and FIG. 16 is a flowchart of the EMC determination method. The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

  One method of EMC measurement is to place an electrical product in an actual usage state and measure the radiation electric field with an antenna located at a position of 3 m or 10 m. The measurement results are expressed as a list of frequencies and radiated electric field strengths, and the radiated electric field strengths are compared with standard values. When the radiated electric field intensity exceeds the standard value or when the margin with the standard value is small, it is necessary to identify the frequency and take EMC countermeasures.

  An EMC problem frequency table 1501 and a clock frequency table 1502 are added to the storage unit 101 of FIG. The EMC problem frequency table 1501 is stored as a list of frequencies and radiated electric field strengths as a result of measuring the radiated electric field strength. The clock frequency table 1502 stores the basic frequency during actual operation for each signal line.

  Next, the EMC determination method will be described with reference to FIG.

  In step S1601a, a frequency at which the radiation field intensity exceeds the standard value or a frequency with a small margin is selected from the EMC problem frequency table 1501 that is a measurement result of the radiation field intensity. Then, the calculation is repeated for all frequencies corresponding to the frequency exceeding the standard value or the frequency having a small margin in the determination processing in step S1606a.

Next, step S1601b selects a signal line corresponding to the selected frequency. Then, the calculation is repeated for all corresponding signal lines in the determination process of step S206. The corresponding signal line corresponds to a signal line having a lock frequency (Equation 5) obtained by dividing the EMC problem frequency by a natural number.
Clock frequency = EMC problem frequency / N (Formula 5)
(N is a natural number, 1, 2, 3, ...)

  According to such a configuration, a corresponding signal line is selected from frequencies that do not satisfy the EMC standard and need countermeasures, and a return loop area, a power supply / GND pattern end area, a stub length, and a power supply / GND pattern area are calculated. Thus, it is possible to extract only the signal related to the problem frequency of the measurement result of the radiated electric field intensity, and to display the four items of EMC numerically.

  In addition, although the case where all steps S202 to S205 are calculated has been described, at least one of steps S202 to S205 may be calculated.

  In this embodiment, the clock frequency table 1502 is used. However, the clock frequency of the signal line may be set in advance in the printed circuit board data 102 and used.

(Embodiment 3)
FIG. 17 is a flowchart showing an EMC conformance level determination method according to Embodiment 3 of the present invention, and FIG. 18 is a diagram showing a calculation result of the EMC conformance level. The same components as those in FIGS. 15 and 16 are denoted by the same reference numerals, and description thereof is omitted.

  Step S1707 in FIG. 17 calculates the EMC conformity level. The EMC conformity level is determined from the results of the return loop area A (step S202), the power source / GND pattern edge area B (step S203), the stub length C (step S204), and the power source / GND pattern area D (step S205). It calculates with (Formula 6). A value obtained by adding the four items is calculated as the sum of the EMC conformity levels.

The EMC conformity level is calculated by (Equation 6), the signals are arranged in ascending order, that is, in order of worse EMC conformance level, and signals below the predetermined criterion are displayed.
EMC conformity level of return loop area = -αA (Formula 6)
EMC compliance level of power supply / GND pattern edge area = -β / B
EMC conformity level of stub length = -γC
EMC compliance level of power supply / GND pattern area = -δD
Sum of EMC conformity level = −αA−β / B−γC−δD
However, α = 0.5, β = 200, γ = 0.2, δ = 0.0025

  FIG. 18 is an example in which the calculation result of FIG. 17 is displayed on the display unit 109. Return loop area A for each signal line (step S202), power source / GND pattern end area B (step S203), stub length C (step S204), power source / GND pattern area D (step S205), The calculation result of the EMC conformity level corresponding to each is displayed. Also, the sum of the EMC conformance levels is displayed, or the EMC conformance levels are rearranged in the descending order of the level (in order of worse EMC conformance level).

EMC is improved when the return loop area of the signal line is small, the wiring pattern of the signal line is in the center with respect to the power supply pattern and the GND pattern, the stub length of the signal line is short, and the power supply / GND pattern is the minimum necessary. This value empirically becomes (Equation 7) when the EMC conformity level is calculated using (Equation 3) described in the second embodiment with a standard wiring length of 20 mm.
EMC conformity level of return loop area = -1 (Formula 7)
EMC compliance level of power supply / GND pattern edge area = -1
EMC conformance level of stub length = 0
EMC compliance level of power supply / GND pattern area = -1
Sum of EMC conformity levels = -3

  The EMC conformance level judgment criterion is a value in which each item of the EMC conformance level -αA, -β / B, and -γC is -2, and the sum of the EMC conformance levels is defined by -8. Further, in order to identify the cause for each signal line having a poor EMC conformance level, the smallest item, that is, the EMC, is deteriorated most at the EMC conformance levels −αA, −β / B, −γC, and −δD of each calculation. Differentiated factors are displayed. Further, all items exceeding the standard value of the EMC conformity level may be distinguished and displayed.

  According to such a configuration, the return signal area, the power supply / GND pattern end area, the stub length, the power supply / GND pattern area are limited by limiting the relevant signal lines for frequencies that do not satisfy the EMC standard and need countermeasures. By calculating, the EMC maximum factor and the degree of violation thereof can be digitized and displayed, and the EMC quality can be improved at the evaluation stage of the electric product, so that the countermeasure points for each signal line can be narrowed down.

  In addition, although the case where all steps S202 to S205 are calculated has been described, at least one of steps S202 to S205 may be calculated.

  In the present embodiment, the signal lines may be highlighted or colored on the printed circuit board design CAD according to the EMC compatibility level. Further, the coefficients α, β, γ, δ, and determination criteria of the calculation formula for the EMC conformity level may be switched according to the product.

  The present invention relates to an EMC determination method and a determination system for digitizing EMC deterioration factors of a printed circuit board and displaying an EMC conformity level in a printed circuit board wiring design CAD system or the like.

DESCRIPTION OF SYMBOLS 101 Memory | storage part 102 Printed circuit board data 103 Processing part 104 Return loop area calculation part 105 Power supply / GND pattern edge area calculation part 106 Stub length calculation part 107 Power supply / GND pattern area calculation part 108 EMC judgment part 109 Display part

Claims (8)

In a processing method for designing a wiring pattern of a position of an electronic component mounted on a printed circuit board and a wiring pattern of a signal line between the electronic components using a CAD system,
Selecting an arbitrary signal line from printed circuit board data designed in the CAD system;
(A) calculating a return loop area for the selected signal line;
(B) calculating a power source / GND pattern edge area;
(C) calculating a stub length;
(D) calculating a power source / GND pattern area;
An EMC determination method comprising the steps of executing at least one of steps (a) to (d) and displaying the executed calculation result corresponding to the signal line. The step of selecting an arbitrary signal line from the printed circuit board data includes a step of selecting a frequency based on a result of measuring the radiation field strength in advance, and a step of selecting a signal line corresponding to the selected frequency. The EMC determination method according to claim 1. In a processing method for designing a wiring pattern of a position of an electronic component mounted on a printed circuit board and a wiring pattern of a signal line between the electronic components using a CAD system,
Selecting an arbitrary signal line from printed circuit board data designed in the CAD system;
(A) calculating a return loop area for the selected signal line;
(B) calculating a power source / GND pattern edge area;
(C) calculating a stub length;
(D) calculating a power source / GND pattern area;
From the step of executing at least one of the steps (a) to (d), calculating the EMC conformity level based on the weighting and sum of the performed calculation results for each signal line, and displaying the EMC conformance level in numerical order. An EMC determination method characterized by comprising: 2. The EMC determination according to claim 1, wherein the step of calculating the return loop area calculates an area of a return loop formed between the wiring pattern of the signal line and the GND pattern closest to the wiring pattern. Method. The step of calculating the power source / GND pattern end area is characterized by calculating an area formed between the wiring pattern of the signal line and the contour of either the power supply pattern or the GND pattern closest to the wiring pattern. The EMC determination method according to claim 1. The step of calculating the stub length is to calculate the distance from the first branch point around the average value of each wiring distance in the wiring pattern of the signal line including the branch as a square value of the distance. The EMC determination method according to claim 1, characterized in that: 2. The step of calculating a power supply / GND pattern area calculates an area of an overlapping portion when a power supply pattern and a GND pattern corresponding to a signal line are arranged on upper and lower layers of a printed circuit board. EMC judgment method. In a CAD system for designing the position of electronic components mounted on a printed circuit board and the wiring pattern of signal lines between the electronic components,
A storage unit for storing printed circuit board data designed in the CAD system;
(A) a return loop area calculation unit;
(B) a power source / GND pattern edge area calculation unit;
(C) a stub length calculation unit;
(D) a power source / GND pattern area calculation unit;
Comprising at least one of (a) to (d),
A determination system comprising: an EMC determination unit that determines an EMC calculation result corresponding to a signal line and an EMC deterioration factor based on the calculation result.

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