JP2011003734A - Method for leveling interlayer insulating film - Google Patents

Method for leveling interlayer insulating film Download PDF

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JP2011003734A
JP2011003734A JP2009145605A JP2009145605A JP2011003734A JP 2011003734 A JP2011003734 A JP 2011003734A JP 2009145605 A JP2009145605 A JP 2009145605A JP 2009145605 A JP2009145605 A JP 2009145605A JP 2011003734 A JP2011003734 A JP 2011003734A
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oxide film
silicon oxide
interlayer insulating
film
teos
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Yoshiko Harada
佳子 原田
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Yamaha Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a method for leveling an interlayer insulating film which facilitates leveling by excluding an effect of unevenness of the interlayer insulating film caused by a wiring layer.SOLUTION: In the method for leveling the interlayer insulating film, first, wiring layers 12a and 12b are formed, the wiring layers 12a and 12b are coated by a high density plasma CVD to form a first HDP oxide film 13, a PL-TEOS oxide film 14 is formed on the first HDP oxide film 13 by the plasma CVD using tetraethoxy silane gas, and a second HDP oxide film 15 is formed on the PL-TEOS oxide film 14 by the high density plasma CVD. Secondly, the second HDP oxide film 15 is polished by a CMP until the PL-TEOS oxide film 14 is exposed. Until the PL-TEOS oxide film 14 is removed, the second HDP oxide film 15 and the PL-TEOS oxide film 14 are simultaneously leveled by the CMP. By so doing, it is possible to attain a leveled interlayer insulating film 10.

Description

本発明は、配線層を覆う層間絶縁膜の表面をＣＭＰ（Chemical Mechanical Polishing）により平坦化する技術に関するものである。   The present invention relates to a technique for planarizing the surface of an interlayer insulating film covering a wiring layer by CMP (Chemical Mechanical Polishing).

配線層を覆う層間絶縁膜上に、更に微細な配線層を形成するときには、層間絶縁膜を平坦化することが重要である。この平坦化はＣＭＰにより行われる。
例えば、高密度プラズマＣＶＤ（Chemical Vapor Deposition）により配線層を覆うシリコン酸化膜を層間絶縁膜として形成した後に、ＣＭＰにより層間絶縁膜を平坦化する。 When forming a finer wiring layer on the interlayer insulating film covering the wiring layer, it is important to flatten the interlayer insulating film. This planarization is performed by CMP.
For example, after a silicon oxide film covering the wiring layer is formed as an interlayer insulating film by high-density plasma CVD (Chemical Vapor Deposition), the interlayer insulating film is planarized by CMP.

しかし、ギャプフィル特性を満足させるため高密度プラズマＣＶＤにより層間絶縁膜としてシリコン酸化膜（以下、高密度プラズマＣＶＤにより形成したシリコン酸化膜を、ＨＤＰ（High Density Plasma）酸化膜と称す。）を、４５°の斜め方向からスパッタを行いながら形成すると、削り取られたシリコン酸化膜が、成膜中のシリコン酸化膜に混入することで、パーティクルが増加する。シリコン酸化膜中のパーティクルが増加することで、シリコン酸化膜をＣＭＰしたときに、膜中のパーティクルが脱落して、層間絶縁膜の表面に凹凸が発生したり、表面がえぐられたりすることがある。   However, in order to satisfy the gap fill characteristics, a silicon oxide film (hereinafter, a silicon oxide film formed by high-density plasma CVD is referred to as HDP (High Density Plasma) oxide film) as an interlayer insulating film by high-density plasma CVD is 45. If the silicon oxide film is formed while being sputtered from an oblique direction, particles are increased by mixing the scraped silicon oxide film into the silicon oxide film being formed. As the number of particles in the silicon oxide film increases, when the silicon oxide film is CMPed, the particles in the film may fall off, resulting in irregularities on the surface of the interlayer insulating film or the surface being swept away. is there.

このような問題に対し、例えば、特許文献１には、高密度プラズマＣＶＤにより、多結晶シリコンゲート（配線層）間の隙間の深い部分が埋め込まれるように、シリコン酸化膜（ＨＤＰ酸化膜）を多結晶シリコンゲート上に形成し、ＴＥＯＳ（テトラエトキシシラン）ガスを用いたプラズマＣＶＤによりシリコン酸化膜（以下、ＴＥＯＳガスを用いたプラズマＣＶＤにより形成したシリコン酸化膜を、ＰＬ−ＴＥＯＳ酸化膜と称す。）をＨＤＰ酸化膜上に形成し、ＣＭＰを用いて、ＰＬ−ＴＥＯＳ酸化膜の表面を平坦化する薄膜形成方法が記載されている。   To deal with such a problem, for example, in Patent Document 1, a silicon oxide film (HDP oxide film) is formed by high-density plasma CVD so that a deep portion of a gap between polycrystalline silicon gates (wiring layers) is buried. A silicon oxide film formed by plasma CVD using TEOS (tetraethoxysilane) gas and formed by plasma CVD using TEOS gas (hereinafter referred to as a PL-TEOS oxide film) is formed on the polycrystalline silicon gate. .) Is formed on the HDP oxide film, and a thin film forming method is described in which the surface of the PL-TEOS oxide film is planarized using CMP.

この特許文献１に記載の方法によれば、ＴＥＯＳガスを用いたプラズマＣＶＤによりＰＬ−ＴＥＯＳ酸化膜を形成することで、高密度プラズマＣＶＤを用いてＨＤＰ酸化膜を形成した場合と比べて、パーティクル量を減らすことができるので、平坦化を向上させることができる。   According to the method described in Patent Document 1, by forming a PL-TEOS oxide film by plasma CVD using TEOS gas, particles are compared with a case where an HDP oxide film is formed by using high-density plasma CVD. Since the amount can be reduced, planarization can be improved.

特開２００４−７９８０７号公報JP 2004-79807 A

しかし、ＰＬ−ＴＥＯＳ酸化膜は、膜質がＨＤＰ酸化膜より軟質であるため、配線層によるＨＤＰ酸化膜の凹凸が、ＰＬ−ＴＥＯＳ酸化膜の成膜時に転写されてしまい、ＣＭＰ後もこの膜厚分布傾向が残ってしまう。また、ＰＬ−ＴＥＯＳ酸化膜は、ウエハエッジ部分で薄くなるが、ＣＭＰにより更に薄くなる傾向にある。   However, since the PL-TEOS oxide film is softer than the HDP oxide film, the irregularities of the HDP oxide film due to the wiring layer are transferred when the PL-TEOS oxide film is formed, and this film thickness is also present after the CMP. Distribution tendency remains. Further, the PL-TEOS oxide film is thinned at the wafer edge portion, but tends to be further thinned by CMP.

そこで本発明は、配線層による層間絶縁膜の凹凸の影響を排除することで、平坦化を容易とすることができる層間絶縁膜の平坦化方法を提供することを目的とする。   Therefore, an object of the present invention is to provide a method for planarizing an interlayer insulating film that can facilitate the planarization by eliminating the influence of the unevenness of the interlayer insulating film due to the wiring layer.

本発明の層間絶縁膜の平坦化方法は、配線層を形成する工程と、前記配線層を覆って第１シリコン酸化膜を、高密度プラズマＣＶＤにより形成する工程と、前記第１シリコン酸化膜上に、第２シリコン酸化膜を、テトラエトキシシランガスを用いたプラズマＣＶＤにより形成する工程と、前記第２シリコン酸化膜上に、第３シリコン酸化膜を形成する工程と、前記第２シリコン酸化膜が露出するまでＣＭＰにより研磨する工程と、前記第３シリコン酸化膜が除去されるまで、前記第２シリコン酸化膜と第３シリコン酸化膜を同時にＣＭＰにより平坦化する工程とを含むことを特徴とする。   The method for planarizing an interlayer insulating film of the present invention includes a step of forming a wiring layer, a step of forming a first silicon oxide film by high-density plasma CVD so as to cover the wiring layer, and a step on the first silicon oxide film. A step of forming a second silicon oxide film by plasma CVD using a tetraethoxysilane gas, a step of forming a third silicon oxide film on the second silicon oxide film, and the second silicon oxide film A step of polishing by CMP until it is exposed, and a step of simultaneously planarizing the second silicon oxide film and the third silicon oxide film by CMP until the third silicon oxide film is removed. .

本発明の層間絶縁膜の平坦化方法によれば、第２シリコン酸化膜上に、第３シリコン酸化膜を形成することで、第２シリコン酸化膜を薄く形成することができるので、第２シリコン酸化膜は、配線層の凹凸が転写された第１シリコン酸化膜の凹凸面の影響が小さい。また、第３シリコン酸化膜は、高密度プラズマＣＶＤにより形成されていることで、テトラエトキシシランガスを用いたプラズマＣＶＤにより形成した第２シリコン酸化膜より硬質であるため、第２シリコン酸化膜より均一性が良好である。
第２シリコン酸化膜が露出するまでＣＭＰにより第３シリコン酸化膜を研磨すると、露出させた第２シリコン酸化膜と、配線層の凹凸が転写され、第１シリコン酸化膜の影響を受けた第２シリコン酸化膜の凹部に残った第３シリコン酸化膜とによる研磨面を形成することができる。
そして、第２シリコン酸化膜と第３シリコン酸化膜を同時にＣＭＰすると、第２シリコン酸化膜と第３シリコン酸化膜とによる研磨面により、均等な研磨速度が得られるので、第３シリコン酸化膜が除去されるまでＣＭＰすることで、第２シリコン酸化膜を平坦化することができる。 According to the planarization method of the interlayer insulating film of the present invention, the second silicon oxide film can be formed thin by forming the third silicon oxide film on the second silicon oxide film. The oxide film is less affected by the uneven surface of the first silicon oxide film to which the unevenness of the wiring layer is transferred. Further, since the third silicon oxide film is formed by high density plasma CVD and is harder than the second silicon oxide film formed by plasma CVD using tetraethoxysilane gas, it is more uniform than the second silicon oxide film. Good properties.
When the third silicon oxide film is polished by CMP until the second silicon oxide film is exposed, the exposed second silicon oxide film and the unevenness of the wiring layer are transferred, and the second silicon oxide film affected by the first silicon oxide film is transferred. A polished surface with the third silicon oxide film remaining in the recess of the silicon oxide film can be formed.
When the second silicon oxide film and the third silicon oxide film are simultaneously CMPed, the uniform polishing rate is obtained by the polishing surface formed by the second silicon oxide film and the third silicon oxide film. By performing CMP until it is removed, the second silicon oxide film can be planarized.

本発明の層間絶縁膜の平坦化方法によれば、第２シリコン酸化膜が露出するまでＣＭＰにより第３シリコン酸化膜を研磨して平坦面を形成した後に、第２シリコン酸化膜と第３シリコン酸化膜とを同時にＣＭＰすることで、均等な研磨速度が得られるので、配線層による層間絶縁膜の凹凸の影響を排除することができる。よって、層間絶縁膜の平坦化を容易とすることができる。   According to the planarization method for an interlayer insulating film of the present invention, the second silicon oxide film and the third silicon are formed after the third silicon oxide film is polished by CMP until the second silicon oxide film is exposed to form a flat surface. By performing CMP simultaneously with the oxide film, a uniform polishing rate can be obtained, so that the influence of the unevenness of the interlayer insulating film due to the wiring layer can be eliminated. Therefore, planarization of the interlayer insulating film can be facilitated.

本発明の実施の形態に係る層間絶縁膜の平坦化方法の各工程を示す図であり、（Ａ）は配線工程を示す図、（Ｂ）は第１ＨＤＰ成膜工程を示す図、（Ｃ）はＰＬ−ＴＥＯＳ成膜工程を示す図である。It is a figure which shows each process of the planarization method of the interlayer insulation film concerning embodiment of this invention, (A) is a figure which shows a wiring process, (B) is a figure which shows the 1st HDP film-forming process, (C) These are figures which show a PL-TEOS film-forming process. 図１の工程に続く層間絶縁膜の平坦化方法の各工程を示す図であり、（Ａ）は第２ＨＤＰ成膜工程を示す図、（Ｂ）は第１ＣＭＰ工程を示す図、（Ｃ）は第２ＣＭＰ工程を示す図である。It is a figure which shows each process of the planarization method of the interlayer insulation film following the process of FIG. 1, (A) is a figure which shows a 2nd HDP film-forming process, (B) is a figure which shows a 1st CMP process, (C) is a figure. It is a figure which shows a 2nd CMP process.

本発明の実施の形態に係る層間絶縁膜の平坦化方法について、図面に基づいて説明する。
まず、図１（Ａ）に示すように、ＳｉＯ2により形成された絶縁膜１１上に、Ａｌ合金等の配線材層を被着した後、この配線材層を、フォトリソグラフィー技術およびエッチング技術を用いて、所望の配線パターンに従ってパターニングすることにより、配線層１２ａ，１２ｂを形成する配線工程を行う。 A method for planarizing an interlayer insulating film according to an embodiment of the present invention will be described with reference to the drawings.
First, as shown in FIG. 1A, after depositing a wiring material layer such as an Al alloy on the insulating film 11 formed of SiO 2 , this wiring material layer is applied with a photolithography technique and an etching technique. Then, a wiring process for forming the wiring layers 12a and 12b is performed by patterning according to a desired wiring pattern.

次に、図１（Ｂ）に示すように、絶縁膜１１および配線層１２ａ，１２ｂ上に、高密度プラズマＣＶＤにより、ＳｉＯ2からなる第１ＨＤＰ酸化膜１３（第１シリコン酸化膜）を形成する第１ＨＤＰ成膜工程を行う。 Next, as shown in FIG. 1B, a first HDP oxide film 13 (first silicon oxide film) made of SiO 2 is formed on the insulating film 11 and the wiring layers 12a and 12b by high-density plasma CVD. A first HDP film forming step is performed.

次に、図１（Ｃ）に示すように、第１ＨＤＰ酸化膜上に、ＴＥＯＳガスを用いたプラズマＣＶＤにより、ＳｉＯ2からなるＰＬ−ＴＥＯＳ酸化膜１４（第２シリコン酸化膜）を形成するＰＬ−ＴＥＯＳ成膜工程を行う。 Next, as shown in FIG. 1C, a PL-TEOS oxide film 14 (second silicon oxide film) made of SiO 2 is formed on the first HDP oxide film by plasma CVD using TEOS gas. -A TEOS film-forming process is performed.

次に、図２（Ａ）に示すように、ＰＬ−ＴＥＯＳ酸化膜１４上に、高密度プラズマＣＶＤにより、ＳｉＯ2からなる第２ＨＤＰ酸化膜１５（第３シリコン酸化膜）を形成する第２ＨＤＰ成膜工程を行う。 Next, as shown in FIG. 2A, a second HDP oxide film 15 is formed on the PL-TEOS oxide film 14 by high-density plasma CVD to form a second HDP oxide film 15 (third silicon oxide film) made of SiO 2. A film process is performed.

例えば、ＰＬ−ＴＥＯＳ酸化膜１４上に第２ＨＤＰ酸化膜１５を形成しない場合には、ＰＬ−ＴＥＯＳ酸化膜１４の厚みを厚くする必要がある。これは、配線層１２ａ，１２ｂや他の配線層の粗密の影響による凹凸をＣＭＰにより平坦化するためには、ある程度の研磨量が必要となるからである。しかし、ＰＬ−ＴＥＯＳ酸化膜１４の厚みが厚いと、配線層１２ａ，１２ｂの凹凸が転写された第１ＨＤＰ酸化膜１３の凹凸面の影響を大きく受けてしまう。   For example, when the second HDP oxide film 15 is not formed on the PL-TEOS oxide film 14, it is necessary to increase the thickness of the PL-TEOS oxide film 14. This is because a certain amount of polishing is required to flatten the unevenness due to the influence of the density of the wiring layers 12a, 12b and other wiring layers by CMP. However, if the thickness of the PL-TEOS oxide film 14 is thick, it is greatly affected by the uneven surface of the first HDP oxide film 13 to which the unevenness of the wiring layers 12a and 12b is transferred.

本実施の形態の平坦化方法では、ＰＬ−ＴＥＯＳ酸化膜１４上に、第２ＨＤＰ酸化膜１５を形成しているので、ＰＬ−ＴＥＯＳ酸化膜１４を薄く形成することができる。従って、ＰＬ−ＴＥＯＳ酸化膜１４は、配線層１２ａ，１２ｂの凹凸が転写された第１ＨＤＰ酸化膜１３の凹凸面の影響を小さく抑えることができる。
また、高密度プラズマＣＶＤによる酸化シリコン膜である第２ＨＤＰ酸化膜１５は、ＰＬ−ＴＥＯＳ酸化膜１４より硬質であるため、ＰＬ−ＴＥＯＳ酸化膜１４より均一性が良好である。 In the planarization method of this embodiment, since the second HDP oxide film 15 is formed on the PL-TEOS oxide film 14, the PL-TEOS oxide film 14 can be formed thin. Therefore, the PL-TEOS oxide film 14 can suppress the influence of the uneven surface of the first HDP oxide film 13 to which the unevenness of the wiring layers 12a and 12b is transferred.
The second HDP oxide film 15, which is a silicon oxide film formed by high-density plasma CVD, is harder than the PL-TEOS oxide film 14, and therefore has better uniformity than the PL-TEOS oxide film 14.

次に、図２（Ｂ）に示すように、ＰＬ−ＴＥＯＳ酸化膜１４が露出するまでＣＭＰにより第２ＨＤＰ酸化膜１５を研磨する第１ＣＭＰ工程を行う。
この第１ＣＭＰ工程により、配線層１２ａ，１２ｂの凹凸が転写され、第１ＨＤＰ酸化膜１３の影響を受けたＰＬ−ＴＥＯＳ酸化膜１４の凹部に残る第２ＨＤＰ酸化膜１５と、露出したＰＬ−ＴＥＯＳ酸化膜１４とによる研磨面Ｓを、平坦化することができる。 Next, as shown in FIG. 2B, a first CMP process is performed in which the second HDP oxide film 15 is polished by CMP until the PL-TEOS oxide film 14 is exposed.
By this first CMP step, the irregularities of the wiring layers 12a and 12b are transferred, and the second HDP oxide film 15 remaining in the recess of the PL-TEOS oxide film 14 affected by the first HDP oxide film 13 and the exposed PL-TEOS oxide are exposed. The polished surface S formed by the film 14 can be flattened.

そして、図２（Ｃ）に示すように、露出したＰＬ−ＴＥＯＳ酸化膜１４と、第２ＨＤＰ酸化膜１５とを同時に、ＣＭＰにより平坦化する第２ＣＭＰ工程を行う。
ほぼ平坦化された研磨面Ｓでは、均等な研磨速度が得られるので、第２ＣＭＰ工程を行って、第２ＨＤＰ酸化膜１５が除去されるまで研磨することにより、ウエハ全体が平坦化された層間絶縁膜１０を得ることができる。従って、ウエハエッジ部分で層間絶縁膜１０が薄くなることが防止できる。 Then, as shown in FIG. 2C, a second CMP step is performed in which the exposed PL-TEOS oxide film 14 and the second HDP oxide film 15 are simultaneously planarized by CMP.
Since an even polishing rate can be obtained on the substantially flattened polishing surface S, the second CMP process is performed and polishing is performed until the second HDP oxide film 15 is removed, whereby the entire wafer is flattened. The membrane 10 can be obtained. Accordingly, it is possible to prevent the interlayer insulating film 10 from being thinned at the wafer edge portion.

また、層間絶縁膜１０は、第２ＨＤＰ酸化膜１５からＰＬ−ＴＥＯＳ酸化膜１４までをＣＭＰすることで、高密度プラズマＣＶＤにより形成した酸化シリコン膜が表面膜とならないため、第１ＨＤＰ酸化膜１３や第２ＨＤＰ酸化膜１５にパーティクルが混入しても、層間絶縁膜１０の表面に凹凸が発生したり、表面がえぐられたりすることがない。   In addition, since the silicon oxide film formed by high-density plasma CVD does not become a surface film by CMP from the second HDP oxide film 15 to the PL-TEOS oxide film 14, the interlayer insulating film 10 includes the first HDP oxide film 13 and Even if particles are mixed into the second HDP oxide film 15, the surface of the interlayer insulating film 10 is not uneven and the surface is not swept away.

このように、本実施の形態に係る平坦化方法は、配線層１２ａ，１２ｂによる第１ＨＤＰ酸化膜１３およびＰＬ−ＴＥＯＳ酸化膜１４の凹凸の影響を排除することができるので、層間絶縁膜１０の平坦化を容易とすることができる。   As described above, the planarization method according to the present embodiment can eliminate the influence of the unevenness of the first HDP oxide film 13 and the PL-TEOS oxide film 14 due to the wiring layers 12a and 12b. Flattening can be facilitated.

なお、本実施の形態では、第２ＨＤＰ酸化膜１５とＰＬ−ＴＥＯＳ酸化膜１４の一部を研磨する工程が、第１ＣＭＰ処理工程および第２ＣＭＰ処理工程としているが、これを一連の工程とすることもできる。   In the present embodiment, the process of polishing part of the second HDP oxide film 15 and the PL-TEOS oxide film 14 is the first CMP process and the second CMP process, but this is a series of processes. You can also.

本発明は、配線層を覆う層間絶縁膜の表面をＣＭＰにより平坦化する際に好適である。   The present invention is suitable when the surface of the interlayer insulating film covering the wiring layer is planarized by CMP.

１０：層間絶縁膜、１１：絶縁膜、１２ａ，１２ｂ：配線層、１３：第１ＨＤＰ酸化膜、１４：ＰＬ−ＴＥＯＳ酸化膜、１５：第２ＨＤＰ酸化膜Ｓ：研磨面 10: interlayer insulating film, 11: insulating film, 12a, 12b: wiring layer, 13: first HDP oxide film, 14: PL-TEOS oxide film, 15: second HDP oxide film S: polished surface

Claims (1)

配線層を形成する工程と、
前記配線層を覆って第１シリコン酸化膜を、高密度プラズマＣＶＤにより形成する工程と、
前記第１シリコン酸化膜上に、第２シリコン酸化膜を、テトラエトキシシランガスを用いたプラズマＣＶＤにより形成する工程と、
前記第２シリコン酸化膜上に、第３シリコン酸化膜を、高密度プラズマＣＶＤにより形成する工程と、
前記第２シリコン酸化膜が露出するまでＣＭＰにより研磨する工程と、
前記第３シリコン酸化膜が除去されるまで、前記第２シリコン酸化膜と第３シリコン酸化膜を同時にＣＭＰにより平坦化する工程とを含むことを特徴とする層間絶縁膜の平坦化方法。 Forming a wiring layer;
Forming a first silicon oxide film by high density plasma CVD covering the wiring layer;
Forming a second silicon oxide film on the first silicon oxide film by plasma CVD using tetraethoxysilane gas;
Forming a third silicon oxide film on the second silicon oxide film by high-density plasma CVD;
Polishing by CMP until the second silicon oxide film is exposed;
And a step of planarizing the second silicon oxide film and the third silicon oxide film simultaneously by CMP until the third silicon oxide film is removed.
JP2009145605A 2009-06-18 2009-06-18 Method for leveling interlayer insulating film Pending JP2011003734A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818684B2 (en) 2018-04-09 2020-10-27 Samsung Electronics Co., Ltd. Vertical memory devices and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818684B2 (en) 2018-04-09 2020-10-27 Samsung Electronics Co., Ltd. Vertical memory devices and methods of manufacturing the same
US11322510B2 (en) 2018-04-09 2022-05-03 Samsung Electronics Co.. Ltd. Vertical memory devices and methods of manufacturing the same

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