JP2011003238A - Device and system for inspecting memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory inspection device efficiently performs redundancy processing without adding a CPU exclusive for redundancy operation.SOLUTION: The memory inspection device, which is configured so that the redundancy processing for relieving fail cells is performed based on fail information obtained from DUT, includes a relief solution storage part in which the relief solutions of the fail cells are previously obtained and stored with respect to all fail cell generation patterns having possibility of generation in the DUT, then, the relief solution of redundancy processing corresponding to fail information of the DUT is obtained from the relief solution storage part.

Description

  The present invention relates to a memory inspection device and a memory inspection system, and more particularly to speeding up redundancy processing.

  2. Description of the Related Art Recent semiconductor memories are provided with a plurality of spare memory cells (hereinafter referred to as spare cells) on the premise that a certain number of defective memory cells are inevitably generated in the manufacturing process due to high integration. When a defective cell (hereinafter referred to as a fail cell) is detected in a test by the memory inspection apparatus, a predetermined pattern in the semiconductor memory under test (hereinafter referred to as DUT) is cut with a laser, and the fail cell is replaced with a spare cell. . As a result, the fail cell can be remedied, and the failure of the DUT caused by the fail cell can be remedied. Data necessary for such defect repair is created by a redundancy arithmetic unit.

  In the redundancy calculation device, redundancy calculation processing for fail cell relief is performed based on the fail information obtained from the DUT. Here, the DUT measurement based on the redundancy calculation is referred to as redundancy measurement.

  The redundancy calculation is usually performed according to an algorithm based on a predetermined regular process by a redundancy calculation dedicated CPU provided in the memory inspection device.

  When a fail cell is detected from the DUT, it is determined whether or not all the fail cells can be rescued by assigning a combination of column spare cells and row spare cells to each of the detected fail cells. The assigned replacement address information is output to the control unit of the memory inspection device.

  FIG. 5 is a block diagram showing an example of a redundancy function in a conventional memory inspection apparatus. A CPU 2 dedicated to redundancy calculation is connected to the DUT 1. The CPU 2 performs a redundancy calculation process for fail cell relief on the DUT 1 based on fail information obtained from the DUT according to an algorithm based on a predetermined regular process.

  FIG. 6 is a conceptual explanatory diagram of redundancy processing based on the configuration of FIG. In the example of FIG. 6 (A), as shown in (B), two fail cells are detected at the 10th X line, one at the 650th X line, and two at the 800th Y line. Regarding these fail cells, the X-line and 650-th fail cells are replaced by the X-line spare cell line XSL, and the Y-line 800-th fail cell is replaced by the Y-line spare cell line YSL. With these replacements, all the fail cells are relieved, and the DUT 1 is determined as a non-defective product.

  By the way, the efficiency of such a series of redundancy processing greatly affects the test efficiency of the memory tester. Therefore, in the current system, the number of CPUs dedicated for redundancy calculation is increased or the time for redundancy calculation is shortened by mounting a dedicated processing circuit.

  Patent Literature 1 describes a memory inspection device configured to increase the speed of redundancy calculation.

JP 2008-65897 A

  However, the addition of a redundancy calculation dedicated CPU increases the amount of heat generated by the device, so the cooling unit must be strengthened. As a result, the manufacturing cost, power consumption, volume, etc. of the memory inspection device increase. Problems will occur.

  The present invention pays attention to such conventional problems, and an object of the present invention is to provide a memory inspection apparatus and a memory inspection system capable of performing redundancy processing efficiently without adding a redundancy calculation dedicated CPU. .

The invention of claim 1 which achieves such a problem,
In a memory inspection apparatus configured to perform redundancy processing for fail cell relief based on fail information obtained from a DUT,
A repair solution storage unit in which a repair solution for the fail cell repair is obtained and stored in advance for all fail cell occurrence patterns that may occur in the DUT;
A repair solution for redundancy processing corresponding to the fail information of the DUT is obtained from the repair solution storage unit.

According to a second aspect of the present invention, in the memory inspection apparatus of the first aspect,
The repair solution storage unit is provided with a normalized address space obtained by extracting only a matrix in which a fail cell exists from the address space of the DUT,
The fail cell position in the address space of the DUT is replaced with a position in a normalized address space of the repair solution storage unit.

The invention of claim 3
A repair solution storage unit according to claim 1 or 2 is provided in a server,
A plurality of memory inspection devices configured to perform redundancy processing for fail cell relief based on DUT fail information are connected to the server,
These memory inspection devices are memory inspection systems characterized in that a repair solution for redundancy processing corresponding to the fail information of the DUT is obtained from a repair solution storage unit provided in the server.

  Accordingly, it is possible to realize a memory inspection device and a memory inspection system capable of reducing the DUT test cost by reducing the redundancy calculation processing time.

It is a block diagram which shows one Example of the redundancy function in the memory test | inspection apparatus of this invention. It is operation | movement explanatory drawing of the normalization part 3 of FIG. FIG. 7 is a diagram illustrating a specific repair solution registration example in the repair solution storage unit 4 of FIG. 1. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows an example of the redundancy function in the conventional memory test | inspection apparatus. FIG. 6 is a conceptual explanatory diagram of redundancy processing based on the configuration of FIG. 5.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a redundancy function in the memory inspection apparatus of the present invention, and the same reference numerals are given to the parts common to FIG. In FIG. 1, the normalization unit 3 prepares an address space (normalized address space) obtained by extracting only the row and column where the fail cell exists from the address space of the DUT 1, and replaces the fail cell position on the normalized address space. Therefore, the fail cell relief data is made easier to use by modifying it according to a certain rule.

  FIG. 2 is an operation explanatory diagram of the normalization unit 3 of FIG. FIG. 2 shows an example in which five fail cells of DUT 1 are detected at the same position as in FIG. 6 as shown in (A). However, the normalizing unit 3 determines the positions of these five fail cells as ( As shown in B), it is specified from the X line and Y line directions of the address space of DUT1. That is, two in the 10th direction from the X line direction, one in each of the 450th, 451th and 650th X lines, and one in the 100th, 300th and 600th directions from the Y line direction, and 800th Two are detected.

  Further, as shown in (C), the normalization unit 3 further extracts the X-line 0th to 3rd lines and the Y-line 0 that extract only the rows and columns in which the fail cells exist from the address space of the DUT 1 shown in (B) Replace with a 4 × 4 normalized address space consisting of the third through third.

  In the repair solution storage unit 4, for all fail cell occurrence patterns based on conditions such as a preset memory size and the number of spare cell lines, those repair solutions are obtained in advance and stored and registered. Here, by making the registration order of these repair solutions regular, the position of the solution to be referred to on the repair solution storage unit 4 can be known from the position of the fail cell, and an appropriate optimal repair solution can be obtained instantly. Can do.

  FIG. 3 is a specific example of repair solution registration in the repair solution storage unit 4. The normalized address space is 4 × 4, and the number of spare cell lines is two for each of X and Y. (A) shows the position of the fail cell in the 4 × 4 normalized address space, and (B) shows each position in the 4 × 4 normalized address space with address numbers 0 to 15 (C ) Indicates the combination of the presence / absence of a fail cell in each address number 0 to 15 in the normalized address space, and the repair solution for each combination by the numbers of the X and Y lines in the normalized address space, and the storage areas # 0 to # The state stored in n−1 is shown.

  In the storage area # 0 in (C), it is stored that all cells in the normalized address space are normal and the solution is not required to be relieved.

  In the storage area # m + 1, four normal addresses 0, 4, 13, and 14 are fail cells, and the repair solutions are stored in the 0th and 3rd X lines and the 3rd Y line. Yes.

  In the storage area # m + 2, five of the normalized address spaces 0, 1, 4, 13, and 14 are fail cells, and the repair solutions are the X line 0th and 1st, the Y line 2nd and 3rd. That is stored.

  In the storage area # n-1, it is stored that all cells in the normalized address space are fail cells, and the solution cannot be repaired.

  However, since the repair solution obtained in the repair solution storage unit 4 is in the normalized address space, the repair solution is restored to the original address space of the DUT 1 and repaired by the spare cell line in the final address space of the DUT 1. A solution can be obtained.

  As described above, since the memory inspection apparatus according to the present invention has a configuration centered on the large-capacity repair solution storage unit 4, the overall configuration can be simplified as compared with the case where an additional redundancy calculation CPU is added. Problems such as heat and volume can be greatly alleviated.

  FIG. 4 is a block diagram showing another embodiment of the present invention. In FIG. 4, the server 5 is provided with a repair solution storage unit 4, and the repair solution storage unit 4 provided in the server 5 is configured to be shared by a plurality of testers 61 to 63.

  According to such a configuration, for example, when a plurality of testers are used in parallel in a semiconductor factory or the like, it is not necessary to provide the repair solution storage unit 4 individually for each tester. It can be carried out efficiently at low cost.

  As described above, according to the present invention, it is possible to obtain the line fail count number stored in the fail memory in a short time, and it is possible to realize a memory inspection device and a memory inspection system with excellent inspection efficiency.

1 Semiconductor memory under test (DUT)
3 Normalization unit 4 Repair solution storage unit 5 Server 6 Tester

Claims (3)

In a memory inspection apparatus configured to perform redundancy processing for fail cell relief based on fail information obtained from a DUT,
A repair solution storage unit in which a repair solution for the fail cell repair is obtained and stored in advance for all fail cell occurrence patterns that may occur in the DUT;
A memory inspection apparatus, wherein a repair solution for redundancy processing corresponding to the fail information of the DUT is obtained from the repair solution storage unit. The repair solution storage unit is provided with a normalized address space obtained by extracting only a matrix in which a fail cell exists from the address space of the DUT,
2. The memory inspection device according to claim 1, wherein a fail cell position in the address space of the DUT is replaced with a position in a normalized address space of the repair solution storage unit. A repair solution storage unit according to claim 1 or 2 is provided in a server,
A plurality of memory inspection devices configured to perform redundancy processing for fail cell relief based on DUT fail information are connected to the server,
These memory inspection apparatuses obtain a repair solution for redundancy processing corresponding to the fail information of the DUT from a repair solution storage unit provided in the server.