KR102013185B1 - Memory device and repair analysis method for the memory device - Google Patents
Memory device and repair analysis method for the memory device Download PDFInfo
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- KR102013185B1 KR102013185B1 KR1020150190011A KR20150190011A KR102013185B1 KR 102013185 B1 KR102013185 B1 KR 102013185B1 KR 1020150190011 A KR1020150190011 A KR 1020150190011A KR 20150190011 A KR20150190011 A KR 20150190011A KR 102013185 B1 KR102013185 B1 KR 102013185B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
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Abstract
The present invention discloses a repair analysis method of a memory device which performs an analysis for repairing a fail of the memory device by using a memory device having repair lines of various structures and the repair lines of various structures. And a plurality of repair lines for repairing memory blocks arranged in a multi-block structure and fail occurring in one memory block or two or more memory blocks arranged in one direction.
Description
The present invention relates to a memory device, and more particularly, to a memory device having repair lines of various structures and a repair of the memory device for performing an analysis for repairing a fail of the memory device using the repair lines of various structures. It relates to an analysis method.
Repair is a necessary method to improve the yield of memory devices. With increasing memory capacity of memory devices, recent memory devices are designed to include a plurality of memory blocks and a repair cell for repairing a failure of the memory blocks.
Currently, a large number of repair analysis algorithms for performing redundancy analysis have been developed for the repair of memory devices. However, repair analysis algorithms are being developed to perform analysis on failing of a single memory block.
As the density of memory devices increases, there is a limitation in applying a repair analysis algorithm that performs repair analysis on a failure of a single memory block to a memory device including multiple memory blocks.
Therefore, it is necessary to present a memory device having repair lines of various structures capable of repairing failing of several memory blocks at once, and to repair failing of several memory blocks at once based on repair lines of various structures. It is necessary to present a solution to analyze the method.
SUMMARY An object of the present invention is to provide a memory device including repair lines having various structures capable of repairing repairs of several memory blocks at once in a multi-block structure.
Another problem to be solved by the present invention is to use a repair line of various structures such as a local spare line (Common Spare Line), a common spare line (Common Spare Line) and a global spare line (Global Spare Line), The present invention provides a repair analysis method of a memory device which performs an analysis for repairing a fail of several memory blocks at once by performing a must-repare analysis.
The memory device of the present invention comprises: memory blocks arranged in a multi-block structure; And a plurality of repair lines for repairing a fail occurring in one memory block or two or more memory blocks arranged in one direction. The plurality of repair lines may include: a common spare line disposed between the memory blocks and replacing a cell line of the adjacent memory block in which the fail occurs to repair the fail; And a global spare line replacing a cell line at the same address of the memory blocks for repairing some of the memory blocks arranged in one direction to repair the fail. At least one of the.
The plurality of repair lines may further include a local spare line disposed adjacent to each of the memory blocks and replacing the cell line in which the fail occurs.
The common spare line may include at least one of a low common spare line and a column common spare line.
The global spare line may include at least one of a row global spare line and a column global spare line.
The global spare line may include a single global spare line that replaces the cell line of some of the memory blocks among the memory blocks arranged in one direction; A total global spare line replacing the cell line of all of the memory blocks arranged in one direction; It may include at least one of.
Meanwhile, a repair analysis method of a memory device of the present invention may include analyzing whether a fail generation state of a cell line of the memory blocks arranged in a multi-block structure corresponds to a must repair condition; And when the memory block corresponding to the must repair condition exists, selecting a repair line for must repair according to a fail occurrence state of the cell line at the same address of other memory blocks arranged in one direction; It is characterized by. The selecting of the repair line for the must repair may include: a local spare line disposed adjacent to each of the memory blocks and replacing the cell line in which the fail occurs; A common spare line disposed between the memory blocks and replacing a cell line of the adjacent memory block in which the fail occurs to repair the fail; And a global spare line for replacing a cell line of the same address of at least some of the memory blocks arranged in one direction to repair the fail. Select one of the repair lines.
Here, the repair line of the row may be selected for the must repair corresponding to the must repair analysis in the column direction, and the repair line of the column may be selected for the must repair corresponding to the must repair analysis in the row direction. have.
The global spare line replaces the cell line of both the single global spare line replacing the cell line of the memory blocks of some of the memory blocks disposed in the one direction and the memory blocks arranged in the one direction. When the global spare line is selected in the step of selecting the repair line for the must repair, one of the single global spare line and the total global spare line may be selected as the repair line. have.
In the selecting of the repair line for the must repair, the priority of selecting the single global spare line as the repair line may be higher than that of the total spare line.
The selecting of the repair line for the must repair may include selecting the global spare line corresponding to the cell line in which the fail occurs when all of the memory blocks arranged in one direction satisfy the must repair condition. .
The selecting of the repair line for the must repair may include: corresponding to the cell line in which the fail occurs when only one of the memory blocks disposed in the one direction satisfies the must repair condition. One of the local spare line and the common spare line may be selected.
The selecting of the repair line for the must repair may include: only one memory block among the memory blocks arranged in the one direction satisfies the must repair condition and the cell line at the same address of the other memory block may be selected. When there is no fail, one of the local spare line and the common spare line corresponding to the cell line in which the fail occurs may be selected.
The selecting of the repair line for the must repair may include: when the at least one of the memory blocks arranged in one direction does not satisfy the must repair condition, the local spare corresponding to the cell line in which the fail occurs. One of the remaining lines, the common spare line and the global spare line, can be selected.
The local spare line, the common spare line and the global spare line may be selected as the repair line according to a predetermined priority.
According to the present invention, a repair line having various structures can be provided in a memory device having a multi-block structure, and a method of repairing several memory blocks of the memory device at once can be easily obtained.
In addition, according to the present invention, a repair line including a common spare line and a global spare line may be used to correspond to a failure of a memory block corresponding to a must-repare condition. A method of repairing failing of several memory blocks at once can be analyzed.
1 is a block diagram illustrating one embodiment of a system for repairing a memory device of the present invention.
2 is a diagram illustrating memory blocks and repair lines implemented in one embodiment of a memory device of the present invention.
3 and 4 are diagrams illustrating one embodiment of a repair analysis method of a memory device of the present invention.
5 and 6 are diagrams illustrating another embodiment of the repair analysis method of the memory device of the present invention.
7 to 9 are diagrams illustrating another embodiment of a repair analysis method of a memory device of the present invention.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The same reference numerals among the reference numerals shown in each drawing represent the same members.
In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.
Terms such as 'first' and 'second' may be used to describe various components, but the components are not limited by the terms, and the terms are only used to distinguish one component from another component. Used.
The present invention discloses a repair analysis method of a memory device including repair lines of various structures and a memory device capable of repairing a fail of several memory blocks in a multi-block structure at once. .
The repair analysis method of the memory device according to the present invention may be performed in the system environment of FIG. 1.
1 illustrates that the
The
The
As shown in FIG. 2, the
Each of the memory blocks B00 to B11 includes a plurality of cell lines in which memory cells are divided into columns and rows. That is, each of the memory blocks B00 to B11 includes row cell lines and column cell lines, and FIG. 2 is illustrated as including eight row cell lines and eight column cell lines. For the purpose of explanation, the row cell lines and the column cell lines are collectively referred to as cell lines, and the number of cell lines of each of the memory blocks B00 to B11 of the present invention may be variously performed by the manufacturer. have.
The memory blocks B00 to B11 may be formed in various matrix structures according to the capacity of the memory device. In FIG. 2, two memory blocks are arranged in a row line and two memory blocks are arranged in a column line. Illustrates the arrangement. For the purpose of explanation, the row line and the column line of the memory blocks are described as the row block line and the column block line, and in general, the block line is described as the block line. The block lines mean memory blocks arranged in one direction, and the number of block lines of the memory blocks of the present invention may be variously performed by the manufacturer.
Meanwhile, repair lines are formed adjacent to the memory blocks B00 to B11. Repair lines mean that a number of unit memory cells that can correspond to a row or a column of memory blocks of each memory block or block line are continuously arranged in a line shape. The repair lines include two or more types of repairing a fail generated in at least one memory block and distinguishing at least one memory block that can be repaired.
More specifically, FIG. 2 illustrates a repair line including a local spare line, a common spare line and a global spare line. Repair lines may include local spare lines, common spare lines and global spare lines, as well as various uses.
First, the local spare lines may be column local spare lines corresponding to the rows of the row local spare lines RLS00 to RLS11 and the columns of the memory blocks B00 to B11 respectively corresponding to the rows of the memory blocks B00 to B11. (CLS00 to CLS11). Each local spare line includes memory cells of a capacity that can replace cell lines of a corresponding memory block and has a structure in which memory cells are continuously arranged in lines.
Local spare lines may be replaced with a failed cell line corresponding to a specific memory block, and row local spare lines RLS00 through RLS11 may be replaced with a row cell line of each of the memory blocks B00 through B11. The column local spare lines CLS00 to CLS11 may be replaced with column cell lines of each of the memory blocks B00 to B11. One or more row local spare lines RLS00 to RLS11 may be formed on at least one of upper and lower portions of the memory blocks B00 to B11, and the column local spare lines CLS00 to CLS11. ) May be formed on one or more of at least one of both sides of the memory blocks (B00 ~ B11). In more specific example, the row local spare line RLS00 is formed under the memory block B00, and the column local spare line CLDS is formed on the left side of the memory block B00.
The common spare lines include row common spare lines RCS00 and RCS11 and column common spare lines CCS00 and CCS11. Common spare lines are formed between the memory blocks B00 to B11, respectively. The common spare lines are shared to adjacent memory blocks and replaced with cell lines of a memory block in which adjacent memory blocks fail. Each common spare line includes memory cells of a capacity that can replace cell lines of an adjacent memory block, and has a structure in which memory cells are continuously arranged in lines.
More specifically, the low common spare line RCS00 is formed between the memory blocks B00 and B01 and replaced with the low cell line of the memory block in which the adjacent memory blocks B00 and B01 have failed, and the low common spare line The line RCS11 is formed between the memory blocks B10 and B11 and is replaced with the low cell line of the memory block in which the fail among the adjacent memory blocks B10 and B11 occurs, and the column common spare line CCS00 is the memory block. Formed between the blocks B00 and B10 and replaced with the column cell line of the memory block in which the adjacent memory blocks B00 and B10 fail, and the column common spare line CCS11 is disposed between the memory blocks B01 and B11. Is formed in the memory block B01 and B11 and is replaced by a column cell line of a memory block in which a fail occurs.
The global spare line includes a single global spare line for repairing a fail corresponding to a specific block line in a multi-block structure, and a total global spare line for repairing the fail corresponding to all block lines in a multi-block structure. . One or more global spare lines may be formed on at least one of the top, bottom, left, and right sides of the block line by the memory blocks. Each global spare line includes memory cells of a capacity that can replace cell lines of memory blocks of a corresponding block line, and has a structure in which memory cells are continuously arranged in a line.
The single global spare line includes row single global spare lines RGS1 and RGS2 and column single global spare lines CGS1 and CGS2. Low single global spare line RGS1 is formed on top of a specific block line by memory blocks B00 and B10, and low single global spare line RGS2 is a specific block line by memory blocks B01 and B11. The column single global spare line CGS1 is formed at the left side of the specific block line by the memory blocks B00 and B01, and the column single global spare line CGS2 is formed at the bottom of the memory block B10 and B11. Is formed on the right side of a particular block line. The row single global spare line RGS1 is for simultaneously repairing a specific block line, that is, a fail of the same row address of the memory blocks B00 and B10, and the row single global spare line RGS2 is a specific block line, that is, memory blocks. This is to repair failing at the same row address of (B01, B11) at the same time. The column single global spare line CGS1 is for repairing a specific block line, that is, a fail of the same column address of the memory blocks B00 and B01, and the column single global spare line CGS2 is used for a specific block line, namely, memory. This is for repairing the fail of the same column address of the blocks B10 and B11 at the same time.
The total global spare line includes a low total global spare line (RTGS) and column total global spare lines (CTGS). The low total global spare line RTGS is formed below the block line by the memory blocks B01 and B11, and the column total global spare line CTGS is the right side of the block line by the memory blocks B10 and B11. Is formed. Alternatively, the low total global spare line RTGS may be formed on or between the block lines by the memory blocks B00 and B10, and the column total global spare line CTGS may be formed by the memory blocks. It may be formed on the left side of the block line by (B00, B01) or formed between the block lines. The row total global spare line RTGS is used to simultaneously repair cell blocks of the same row address of memory blocks B00 and B10 or memory blocks B01 and B11, that is, all block lines forming a row in a multi-block structure. The column total global spare line CTGS simultaneously repairs the cell lines of the same column address of the memory blocks B00 and B01 or the memory blocks B10 and B11, that is, all the block lines forming the column in the multi-block structure. It is to.
2 illustrates eight local spare lines (four row local spare lines and four column local spare limes) and four common spare lines corresponding to four memory blocks B00, B01, B10, and B11. 2 low common spare lines and 2 column common spare lines) and 6 global spare lines (2 low single global spare lines, 2 column single global spare lines, 1 low total global spare line and 1 column total global) Spare lines) are illustrated. That is, the embodiment of Figure 2 illustrates that a total of 18 spare lines are formed.
Therefore, in the case of the memory block B00, the number of column local spare lines, columns, common spare lines, column single global spare lines, and column total global spare lines that can be used to repair the failure of one row cell line is limited.
In the embodiment of FIG. 2, if all of the column local spare line, column common spare line, column single global spare line, and column total global spare line are available for repair, fail of one low cell line of memory block B00. There are four repair lines that can be used to repair. It may be determined that the number of failing lines of the low cell line of the memory block B00 exceeds the number of repair lines of the available columns corresponds to a must-repair condition. In this case, the low cell line of the memory block B00 may be replaced with any one of a low local spare line, a low common spare line, a low single global spare line, and a low total global spare line for repair of a fail.
In addition, in the embodiment of FIG. 2, when all of the low local spare line, low common spare line, low single global spare line and low total global spare line are available for repair, one column cell line of memory block B00 There are four repair lines that can be used to repair a fail. It may be determined that the fail repair condition of the column cell line of the memory block B00 exceeds the number of repair lines in the row that can be used. In this case, the column cell line of the memory block B00 may be replaced with any one available among the column local spare line, the column common spare line, the column single global spare line, and the column total global spare line for repair of the fail.
The repair analysis method of a memory device according to the present invention performs the above step of analyzing whether a fail occurrence state of a cell line of memory blocks arranged in a multi-block structure corresponds to a must repair condition, and a memory block corresponding to a must repair condition. If is present, selecting the repair line for the must repair according to the fail generation state of the cell line of the same address of the other memory blocks on the block line.
The step of selecting a repair line for the must repair may be divided into three cases and select one of a local spare line, a common spare line, and a global spare line.
In the first case, all memory blocks included in the block line satisfy the must repair condition. In the second case, only one memory block among the memory blocks included in the block line satisfies the must repair condition. This is the case in which at least one of the memory blocks included in the M2 does not satisfy the must repair condition. In the second case, there may be additionally required that there is no fail in the cell line of the same address of the remaining memory blocks.
3 to 9, a step of selecting a repair line for a must repair in response to the above cases will be described. 3 to 9 illustrate a memory device including three memory blocks B0, B1, and B2 and eight repair lines for explaining an embodiment of the repair analysis method of the present invention. Repair lines include one row global spare line (RGS2), two column common spare lines (CCS1 and CCS2), two column local spare lines (CLS0 and CLS2) and three row local spare lines (RLS0 to RLS2). do. One low global spare line RGS2 may be configured as either a low single global spare line or a low total global spare line. The repaired address may be represented as a (row address, column address). For example, the memory block B0 of FIG. 3 may include (3, 2), (3, 4), In (3, 6), the fail is marked with an 'X' mark, respectively.
A first case of selecting a repair line for a must repair may be described with reference to FIGS. 3 and 4, and in the first case, a global spare line corresponding to a cell line in which a fail occurs may be selected. This will be described with reference to FIGS. 3 and 4.
Referring to FIG. 3, the memory blocks B0 to B2 have failed at the same row address, that is, the row cell line R3. That is, FIG. 3 corresponds to a first case in which all memory blocks included in a block line satisfy a must repair condition.
FIG. 3 assumes that column local spare lines CLS0 and CLS2, column common spare lines CCS1 and CCS2, row local spare lines RLS0 to RLS2 and global spare line RGS2 are available.
In this case, two repair lines of a column that can be used to repair failings of the row cell line R3 of the memory block B0 are two column local spare lines CLS0 and two column common spare lines CCS1.
If the number of failings of the low cell line R3 of the memory block B0 is two or less, the failings of the memory block B0 are repaired using one or both of the column local spare line CLS0 and the column common spare line CCS1. Can be. However, the number of failes of the memory block B0 of FIG. 3 exceeds two, the number of column local spare lines CLS0 and column common spare lines CCS1 that can be used as three. That is, the fail state of the memory block B0 corresponds to a must repair condition. In addition, the memory blocks B1 and B2 correspond to a must repair condition similarly to the memory block B0.
When all of the memory blocks B0 to B2 included in the block line satisfy the must repair condition, as shown in FIG. 3, each of the memory blocks B0 to B2 is formed by using each row local spare line RLS0 to RLS2. Repairing the failing of cell lines of the same address in is inefficient. Therefore, the repair analysis method of the present invention selects the global spare line RGS2 corresponding to the failed cell line for repairing the failed low cell line as shown in FIG. 4.
By selecting the global spare line RGS2 as described above, failures occurring in the cell lines of the same addresses of the plurality of memory blocks B0 to B2 may be simultaneously resolved. If the global spare line includes a single global spare line and a total global spare line, the repair analysis method of the present invention may select a higher priority among the single global spare line and the total global spare line, preferably total The priority of selecting a single global spare line as a repair line may be higher than that of the spare line.
Meanwhile, referring to FIG. 5, the number of fail corresponding to the must repair condition is generated only in the low cell line R3 of the memory block B0. That is, FIG. 5 corresponds to the second case in which only one memory block B0 among the memory blocks B0 to B2 included in the block line satisfies the must repair condition. The cell line of the same row address of the memory blocks B1 and B2 has no fail.
As shown in FIG. 5, only one memory block B0 among the memory blocks B0 to B2 included in the block line satisfies the must repair condition and fails to a row cell line of the same address of the remaining memory blocks B1 and B2. In this case, it is inefficient to select the global spare line RGS2 that simultaneously resolves the failings of the plurality of memory blocks B0 to B2.
Therefore, for the repair of the low cell line of the memory block B0 in which failings of the must repair condition occur, one of the low local spare line RLS0 corresponding to the failing cell line and the low common spare line (not shown) Can be selected. 5 and 6, since there is no low common spare line, failing of the low cell line R3 of the memory block B0 generated as shown in FIG. 5 may be eliminated by selecting the low local spare line RLS0 as shown in FIG. 6. .
Meanwhile, referring to FIG. 7, the number of failes corresponding to the must repair condition is generated in the row cell line R3 of the memory blocks B0 and B2. That is, FIG. 7 corresponds to a third case in which at least one of the memory blocks included in the block line does not satisfy the must repair condition.
When at least one memory block among the memory blocks B0 to B2 included in the block line does not satisfy the must repair condition as illustrated in FIG. 7, for repair of the low cell line in which the fail occurs, the memory cell corresponds to the low cell line. The remaining one of the low local spare line, the low common spare line, and the low global spare line may be selected. In this case, the low local spare line, the low common spare line, and the low global spare line may be selected as repair lines according to a predetermined priority.
That is, when failures corresponding to the must repair condition occur in the row cell lines of the same addresses of the memory blocks B0 and B1 as shown in FIG. 7, the row local spare lines corresponding to the memory blocks B0 and B2 are generated. Alternatively, the fail of the low cell line of each of the memory blocks B0 and B2 may be eliminated by using the low common spare line.
However, when there is no low local spare line or low common spare line that can be used in any one of the memory blocks B0 as shown in FIG. 8, the respective memory blocks B0 using the global spare line RGS2 as shown in FIG. 9. The failures of the low cell line of B2) can be eliminated.
3 to 9 illustrate a fail repair using row repair lines of a row corresponding to a row cell, in case of a must repair condition in which a repair line of a column cannot be used in response to a failure of a row cell. The following describes a method for repairing failing of multiple memory blocks simultaneously using a repair line. However, the present invention is not limited thereto, and in the present invention, in the case of a must repair condition in which a row repair line cannot be used in response to a fail of a column cell line, the present invention may also use a repair line of a column corresponding to the column cell line to resolve the fail. Include.
As described above, the present invention can propose repair lines having various structures capable of repairing repairs of several memory blocks at once in a multi-block structure, and include a local spare line and a common spare line. Must-Repare analysis is performed using repair lines of various structures such as Spare Line and Global Spare Line to perform the analysis to repair the failure of several memory blocks at once. Can be.
Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
Claims (14)
And a plurality of repair lines for repairing a failure occurring in one memory block or a block line including two or more of the memory blocks arranged in one direction.
The plurality of repair lines,
A common spare line disposed between the memory blocks and replacing a cell line of the adjacent memory block in which the fail occurs to repair the fail; And
A global spare line replacing the cell lines of the same address of the memory blocks of one block line for repair of some of the plurality of block lines including the memory blocks arranged in one direction to repair the fail (Global Spare Line);
The global spare line,
A single global spare line for replacing the cell lines of the same address of the memory blocks corresponding to a particular one block line; And
And at least one of a total global spare line corresponding to all the block lines to replace the cell lines at the same address of the memory blocks.
And the plurality of repair lines further comprises local spare lines disposed adjacent each of the memory blocks and replacing the cell lines in which the failure occurred.
And the common spare line comprises at least one of a low common spare line and a column common spare line.
The global spare line includes at least one of a low single global spare line and a column single global spare line as the single global spare line, and a low total global spare line and a column total global spare line and a low global spare line as the total global spare line. And at least one of a column global spare line.
Selecting a repair line for a must repair according to a fail occurrence state of the cell line at the same address of other memory blocks arranged in one direction when the memory block corresponding to the must repair condition exists; and
Selecting the repair line for the must repair,
A local spare line disposed adjacent each of the memory blocks and replacing the cell line in which the fail has occurred;
A common spare line disposed between the memory blocks and replacing a cell line of the adjacent memory block in which the fail has occurred to repair the fail; And
A global spare line for replacing a cell line of a same address of at least some of the memory blocks arranged in one direction to repair the fail; Selecting one of the repair lines as a repair analysis method of a memory device.
Select the repair line of a row for the must repair corresponding to the analysis whether the corresponding to the must repair condition in the column direction;
And selecting the repair line of a column for the must repair corresponding to an analysis that corresponds to the must repair condition in a row direction.
The global spare line is a single global spare line that replaces the cell line of some of the memory blocks of the memory blocks arranged in one direction and a total global that replaces the cell line of all of the memory blocks arranged in the one direction. Separated by spare lines,
And when the global spare line is selected in the selecting of the repair line for the must repair, selecting one of the single global spare line and the total global spare line as the repair line.
And selecting the repair line for the must repair, wherein the single global spare line is selected as the repair line rather than the total global spare line.
When all of the memory blocks arranged in one direction satisfy the must repair condition,
And selecting the global spare line corresponding to the cell line in which the fail occurred.
When only one of the memory blocks arranged in the one direction satisfies the must repair condition,
And selecting one of the local spare line and the common spare line corresponding to the cell line in which the fail has occurred.
When only one memory block among the memory blocks arranged in the one direction satisfies the must repair condition and there is no fail in the cell line at the same address of the remaining memory block,
And selecting one of the local spare line and the common spare line corresponding to the cell line in which the fail has occurred.
When at least one of the memory blocks arranged in one direction does not satisfy the must repair condition,
And selecting one of the local spare line, the common spare line, and the global spare line corresponding to the cell line in which the fail has occurred.
And the local spare line, the common spare line and the global spare line are selected as the repair line according to a predetermined priority.
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| KR102400631B1 (en) * | 2020-12-10 | 2022-05-19 | 연세대학교 산학협력단 | Redundancy analysis method and apparatus |
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2015
- 2015-12-30 KR KR1020150190011A patent/KR102013185B1/en active IP Right Grant
Non-Patent Citations (1)
| Title |
|---|
| Bing-Yang Lin et al., Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints, IEEE, 2013.12.23.* |
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| KR20170079439A (en) | 2017-07-10 |
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