JP2010532905A5 - - Google Patents

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JP2010532905A5
JP2010532905A5 JP2010518258A JP2010518258A JP2010532905A5 JP 2010532905 A5 JP2010532905 A5 JP 2010532905A5 JP 2010518258 A JP2010518258 A JP 2010518258A JP 2010518258 A JP2010518258 A JP 2010518258A JP 2010532905 A5 JP2010532905 A5 JP 2010532905A5
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processor
processors
parallel
operable
memory
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JP2010518258A
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JP2010532905A (en
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Priority claimed from US12/147,332 external-priority patent/US8984256B2/en
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ダイナミックランダムアクセスメモリ（ＤＲＡＭ）のダイに埋め込まれた複数の並列プロセッサを備えていて、
前記複数の並列プロセッサは、外部メモリコントローラおよび外部プロセッサと通信し、
前記並列プロセッサの各々は、スレッドレベルの並列処理のために最適化された命令セットを処理するように動作可能であり、前記プロセッサの各々は、単一のスレッドを処理するように動作可能であり、複数のスレッドが、共有メモリまたは１つ以上の共有変数を通してデータを共有することを特徴とするシステム。 A plurality of parallel processors embedded in a dynamic random access memory (DRAM) die;
The plurality of parallel processors communicate with an external memory controller and an external processor;
Each of the parallel processors is operable to process an instruction set optimized for thread-level parallel processing, and each of the processors is operable to process a single thread. A system wherein multiple threads share data through shared memory or one or more shared variables. 前記ダイは、ＤＲＡＭピン配列を有するパッケージに入れられていることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein the die is in a package having a DRAM pin array. 前記並列プロセッサは、デュアルインラインメモリモジュール上に搭載されていることを特徴とする請求項１に記載のシステム。   The system according to claim 1, wherein the parallel processor is mounted on a dual in-line memory module. 前記システムは、前記プロセッサがＤＲＡＭモードレジスタを通してイネーブルにされる時以外は、ＤＲＡＭとして動作することを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein the system operates as a DRAM except when the processor is enabled through a DRAM mode register. 前記外部プロセッサは、関連する永久記憶装置から前記ＤＲＡＭにデータおよび命令を転送するように動作可能であることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein the external processor is operable to transfer data and instructions from an associated permanent storage device to the DRAM. 前記永久記憶装置は、フラッシュメモリであることを特徴とする請求項５に記載のシステム。   6. The system of claim 5, wherein the permanent storage device is a flash memory. 前記外部プロセッサは、前記並列プロセッサと外部装置との間の入出力インターフェースを提供するように動作可能であることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein the external processor is operable to provide an input / output interface between the parallel processor and an external device. メモリモードレジスタに割り当てられる１以上のビットは、前記並列プロセッサのうちの１つ以上をイネーブルまたはディスエーブルにするように動作可能であることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein one or more bits assigned to a memory mode register are operable to enable or disable one or more of the parallel processors. 少なくとも一つの前記並列プロセッサがマスタプロセッサとみなされ、他の前記並列プロセッサはスレーブプロセッサとみなされることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein at least one of the parallel processors is considered a master processor and the other parallel processors are considered slave processors. 各プロセッサは、クロック速度を有していて、前記マスタプロセッサ以外の各プロセッサは、性能または電力消費を最適化するように調整された前記プロセッサのクロック速度を有するように動作可能であることを特徴とする請求項９に記載のシステム。   Each processor has a clock speed, and each processor other than the master processor is operable to have the clock speed of the processor adjusted to optimize performance or power consumption. The system according to claim 9. 各プロセッサは、マスタプロセッサまたはスレーブプロセッサとみなされるように動作可能であることを特徴とする請求項９に記載のシステム。   The system of claim 9, wherein each processor is operable to be considered a master processor or a slave processor. 前記マスタプロセッサは、いくつかのスレーブプロセッサによる処理を要求し、前記いくつかのスレーブプロセッサからの出力を待ち、かつ前記出力を結合することを特徴とする請求項９に記載のシステム。   The system of claim 9, wherein the master processor requests processing by a number of slave processors, waits for output from the number of slave processors, and combines the outputs. 前記マスタプロセッサは、前記出力が前記いくつかのプロセッサの各々から受信されるとき、前記いくつかのプロセッサからの出力を結合することを特徴とする請求項１２に記載のシステム。   The system of claim 12, wherein the master processor combines outputs from the several processors as the outputs are received from each of the several processors. 停止されるべき前記並列プロセッサのうちの１つ以上をイネーブルにすることによって、低電力消費が提供されることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein low power consumption is provided by enabling one or more of the parallel processors to be halted. 前記並列プロセッサの各々は、プログラムカウンタを伴っていて、前記並列プロセッサが伴っているプログラムカウンタに全て１を書き込むことによって停止されるように動作可能であることを特徴とする請求項１４に記載のシステム。   15. Each of the parallel processors is associated with a program counter and is operable to be stopped by writing all ones to the program counter associated with the parallel processor. system. 複数のプロセッサは、モノリシックメモリデバイスのために設計された半導体製造プロセスを用いて前記チップ上に配置されるコンピュータメモリと共に前記チップ上に製造されることを特徴とする請求項１に記載のシステム。   The system of claim 1, wherein the plurality of processors are fabricated on the chip along with computer memory disposed on the chip using a semiconductor fabrication process designed for monolithic memory devices. 半導体製造プロセスは、４層未満のメタル相互接続を用いることを特徴とする請求項１６に記載のシステム。   The system of claim 16, wherein the semiconductor manufacturing process uses less than four metal interconnects. 半導体製造プロセスは、３層未満のメタル相互接続を用いることを特徴とする請求項１７に記載のシステム。   The system of claim 17, wherein the semiconductor manufacturing process uses less than three metal interconnects.
JP2010518258A 2008-06-26 2008-06-27 Thread-optimized multiprocessor architecture Pending JP2010532905A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture

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JP2010532905A JP2010532905A (en) 2010-10-14
JP2010532905A5 true JP2010532905A5 (en) 2012-06-07

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US (2) US8984256B2 (en)
EP (1) EP2288988A4 (en)
JP (1) JP2010532905A (en)
KR (1) KR101121606B1 (en)
CN (2) CN101796484B (en)
AU (1) AU2008355072C1 (en)
BR (1) BRPI0811497A2 (en)
CA (1) CA2684753A1 (en)
RU (1) RU2450339C2 (en)
WO (1) WO2009157943A1 (en)

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