JP2010521717A - Information processing apparatus and storage media drive - Google Patents

Abstract

In the information processing apparatus according to the present invention, the information processing apparatus main body has a main control unit that controls the power-on of the storage media drive based on the power-on operation of the power operation unit. The storage media drive has a storage memory having a plurality of storage areas in which information can be written and information read, and a counter whose count value is incremented when the power is turned on. And a control unit as a memory controller that stores the contents of the access request in the storage area of the storage memory determined based on the count value.

Description

  The present invention relates to an information processing apparatus and a storage media drive.

  As a conventional technique, there is an information processing apparatus that includes a trace writing circuit and a tracer memory and includes two processors that perform the same operation on the master side and the slave side (see, for example, Patent Document 1).

  According to this information processing apparatus, during normal operation, the same trace information is traced by each processor to perform a double check, while at the time of debugging or when a failure occurs, the two processors execute tracing in different modes.

  The tracer writing circuit as a master writes the trace information instructed by a normal microprogram into the tracer memory. On the other hand, for example, when writing of only a branch instruction is instructed by the tracer control signal, the tracer write circuit as a slave extracts only the branch instruction in the tracer information and writes it to the tracer memory. As a result, there is an effect that it is possible to obtain trace information according to the purpose content such as failure analysis.

  Incidentally, trace information is also collected when extracting trace information when a problem occurs. Therefore, in the conventional information processing apparatus, there is a possibility that important trace information indispensable for problem analysis does not remain (because the trace information collected when the trace information is extracted is overwritten).

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an information processing apparatus and a storage media drive that realizes problem analysis while reliably leaving trace information.

JP-A-9-114695

  According to an example, the information processing apparatus of the present invention includes an information processing apparatus main body and a storage media drive accommodated in the information processing apparatus main body. The information processing apparatus main body includes main control means for controlling the power-on of the storage media drive based on the power-on operation of the power operation unit. The storage media drive includes a storage memory having a plurality of storage areas where information can be written and read, a counter whose count value is incremented when the power is turned on, and when there is a request to access the storage memory, Memory control means for storing the contents of the access request in a storage area on the storage memory determined based on the value.

FIG. 1 is a schematic diagram illustrating an appearance of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the embodiment. FIG. 3 is a block diagram showing a schematic configuration of an SSD (Solid State Drive) according to the embodiment. FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD according to the embodiment. FIG. 5 is a schematic configuration diagram of the NAND memory according to the embodiment. FIG. 6 is a flowchart showing command trace in the information processing apparatus according to the embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Configuration of information processing device)
FIG. 1 is a schematic diagram showing an appearance of an information processing apparatus 1 according to an embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 1 includes a main body 2 and a display unit 3 attached to the main body 2.

  The main body 2 has a box-shaped housing 4, and the housing 4 includes an upper wall 4 a, a peripheral wall 4 b, and a lower wall (not shown). The upper wall 4 a of the housing 4 has a front part 40, a central part 41, and a back part 42 in order from the side close to the user who operates the information processing apparatus 1. The lower wall is located on the opposite side of the upper wall 4a and faces the installation surface on which the information processing apparatus 1 is placed. The peripheral wall 4b has a front wall 4ba, a rear wall 4bb, and left and right side walls 4bc, 4bd.

  The front unit 40 includes a touch pad 20 that is a pointing device, a palm rest 21, and an LED (Liquid Crystal Display) 22 that is lit in conjunction with the operation of each unit of the information processing apparatus 1.

  The central portion 41 includes a keyboard placement portion 23 to which a keyboard 23a capable of inputting character information and the like is attached.

  The back portion 42 is detachably attached to the battery pack 24, the power switch 25 for turning on the information processing apparatus 1 on the right side of the battery pack 24, and the display unit 3 can be rotated to the left and right of the battery pack 24. And a pair of hinge portions 26a, 26b.

  A discharge port 29 (not shown) for discharging the wind W from the inside of the housing 4 to the outside is provided in the left side wall 4bc of the housing 4. In addition, on the right side wall 4bd, for example, an ODD (Optical Disc Drive) 27 capable of reading and writing data to and from an optical storage medium such as a DVD, and a card slot 28 into which various cards are inserted and removed are arranged.

  The casing 4 is formed by a casing cover including a part of the peripheral wall 4b and the upper wall 4a, and a casing base including a part of the peripheral wall 4b and the lower wall. The housing cover is detachably combined with the housing base to form an accommodation space with the housing base. In this accommodation space, an SSD (Solid State Drive) 10 or the like as a nonvolatile semiconductor memory drive is accommodated. Details of the SSD 10 will be described later.

  The display unit 3 includes a display housing 30 having an opening 30a, and a display unit 31 including an LCD or the like that can display an image on a display screen 31a. The display unit 31 is accommodated in the display housing 30, and the display screen 31a is exposed to the outside of the display housing 30 through the opening 30a.

  In the housing 4, in addition to the SSD 10, the battery pack 24, the ODD 27, and the card slot 28, a main circuit board, an expansion module, a fan, and the like (not shown) are accommodated.

  FIG. 2 is a block diagram showing a schematic configuration of the information processing apparatus 1 according to the embodiment of the present invention.

  As shown in FIG. 2, the information processing apparatus 1 includes the SSD 10, the expansion module 12, the fan 13, the touch pad 20, the LED 22, the keyboard 23a, the power switch 25 as the power operation unit, the ODD 27, the card slot 28, and the display. In addition to the unit 31, an EC (Embedded Controller) 111 that is an embedded system that controls each unit, a flash memory 112 that stores a BIOS (Basic Input Output System) 112a, and an LSI (Large Scale Integration) chip and various buses A south bridge 113 that functions as a controller and an I / O controller, and a north bridge that is an LSI chip and controls connections between a CPU (Central Processing Unit) 115, a GPU (Graphic Processing Unit) 116, a main memory 117, and various buses, which will be described later. 114 and various signals With the CPU115 of the main control unit which, with the GPU116 for display control by processing a video signal, and a main memory 117 to be read or written by the CPU115.

  The power switch 25 turns on the power of the information processing apparatus 1 and the SSD 10 built in the information processing apparatus 1 based on a user's pressing operation in the power-on operation. In order to perform the power shut-off operation, for example, the information processing apparatus 1 and the information are operated by operating the end screen displayed on the display screen 31a of the display unit 3 with the touch pad 20 or the like based on the key operation of the keyboard 23a. The power supply of the SSD 10 built in the processing apparatus 1 is shut off. In such a power operation, the touch pad 20, the keyboard 23a, and the power switch 25 constitute a power operation unit.

  The extension module 12 includes an extension circuit board, a card socket provided on the extension circuit board, and an extension module board inserted into the card socket. The card socket is based on, for example, a standard such as Mini-PCI, and examples of the extension module substrate include a 3G (3rd Generation) module, a TV tuner, a GPS module, and a Wimax (registered trademark) module.

  The fan 13 is a cooling unit that cools the inside of the housing 4 based on the blown air, and discharges the air in the housing 4 to the outside as the wind W through the discharge port 29 (not shown).

  The EC 111, the flash memory 112, the south bridge 113, the north bridge 114, the CPU 115, the GPU 116, and the main memory 117 are electronic components mounted on the main circuit board.

(Configuration of SSD)
FIG. 3 is a block diagram showing a schematic configuration of the SSD 10 according to the embodiment of the present invention. As shown in FIG. 3, the SSD 10 is roughly configured to include a temperature sensor 101, a connector 102, a control unit 103, NAND memories 104 </ b> A to 104 </ b> H, a DRAM 105, and a power supply circuit 106. This is an external storage device that stores a program and does not erase the recording without supplying power. Although it does not have a drive mechanism such as a magnetic disk or a head like a conventional hard disk drive, a program such as an OS (Operating System), data created based on execution of a user or software, etc. in a storage area of a NAND memory Is a non-volatile semiconductor memory drive that can be stored in a readable and writable manner for a long time like a conventional hard disk drive and can operate as a start-up drive of the information processing apparatus 1.

  The control unit 103 as a memory controller is connected to the connector 102, the eight NAND memories 104A to 104H, the DRAM 105, and the power supply circuit 106, respectively.

  The control unit 103 is connected to the host device 8 via the connector 102, and is connected to the external device 9 as necessary. Further, the control unit 103 is provided with a power cycle counter (hereinafter referred to as “PCC”) 103A that counts the number of times the SSD 10 is turned on.

  The power source 7 is a battery pack 24 or an AC adapter (not shown), and for example, DC 3.3 V is supplied to the power circuit 106 via the connector 102. The power source 7 supplies power to the entire information processing apparatus 1.

  The host device 8 is a main circuit board in the present embodiment, and the south bridge 113 mounted on the main circuit board and the control unit 103 are connected. Data transmission / reception is performed between the south bridge 113 and the control unit 103 based on a standard such as serial ATA.

  The external device 9 is another information processing device different from the information processing device 1. The external device 9 is connected to the control unit 103 based on a standard such as RS-232C, for example, with respect to the SSD 10 removed from the information processing device 1, and has a function of reading data stored in the NAND memories 104A to 104H. Have.

  The board on which the SSD 10 is mounted has an outer size equivalent to, for example, a 1.8 inch type or 2.5 inch type HDD (Hard disk drive). In this embodiment, it is equivalent to the 1.8 inch type.

  The control unit 103 controls operations on the NAND memories 104A to 104H. Specifically, the control unit 103 controls data reading and data writing to the NAND memories 104 </ b> A to 104 </ b> H in response to a request from the host device 8. The data transfer rate is, for example, 100 MB / Sec when reading data and 40 MB / Sec when writing.

  Each of the NAND memories 104A to 104H is a non-volatile semiconductor memory having a storage capacity of, for example, 16 GB. For example, an MLC (Multi Level Cell) -NAND memory (multi-level cell) capable of recording 2 bits in one memory cell. Value NAND memory). The MLC-NAND memory is generally inferior to the number of rewritable times compared to an SLC (Single Level Cell) -NAND memory, but it is easy to increase the storage capacity.

  The DRAM 105 is a buffer in which data is temporarily stored when data is read from and written to the NAND memories 104A to 104H under the control of the control unit 103.

  The connector 102 has a shape based on a standard such as serial ATA. Note that the control unit 103 and the power supply circuit 106 may be connected to the host device 8 and the power supply 7 through separate connectors, respectively.

  The power supply circuit 106 converts DC 3.3V supplied from the power supply 7 into, for example, DC 1.8V, 1.2V, and the like, and supplies these three types of voltages to each unit according to the drive voltage of each unit of the SSD 10. .

(About SSD storage capacity)
FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD 10 according to the embodiment of the present invention. As shown in FIG. 4, the storage capacity of the SSD 10 includes storage capacities 104a to 104g.

  The storage capacity 104a is a NAND capacity, and is the maximum storage capacity using the storage areas of all the NAND memories 104A to 104H. For example, when the storage capacity of each of the NAND memories 104A to 104H is 16 GB, the storage capacity 104a is 128 GB. The storage capacity 104a is given by NAND configuration information of a manufacturing information write command of a UART (Universal Asynchronous Receiver Transmitter).

  The storage capacity 104b is Max Logical Capacity, and is the maximum storage capacity that can be accessed by LBA (Logical Block Addressing).

  The storage capacity 104c is S.I. M.M. A. R. T (Self-Monitoring Analysis and Reporting Technology) log area start LBA, which is provided to divide the storage capacity 104b and the storage capacity 104d described below. Details will be described later.

  The storage capacity 104d is Vendor Native Capacity, and is the maximum storage capacity given as a user use area. It is given in the initial Identical Device data of the ATA special command. The storage capacity 104d is determined at the design stage of the SSD 10 by the manufacturer (Vender) based on the IDEMA (The International Disk Drive Equipment and Materials Association) standard, and is expressed by the following equation (1).

LBA = 97,696,368 + (1,953,504 × ((Capacity in GB)-50)) ... number 1
The storage capacity 104e is an OEM Native Capacity, and is a storage capacity determined at the time of manufacture according to a request from an OEM (Original Equipment Manufacturer). It is given by writing the unique information of the ATA special command. The storage capacity 104e is a value returned by the Device Configuration Identify command when the Device Configuration Overlay Feature Set is supported.

  The storage capacity 104f is a native capacity, and the initial value is the same as the storage capacity 104e. When Feature Set is supported, it is a value that can be changed with the Device Configuration Set command. The storage capacity 104f is a value returned by a Read Native Max Address (EXT) command.

  The storage capacity 104g is a current capacity and is a storage capacity in use by the user, and an initial value is the same as the storage capacity 104f. It can be changed with the Set Max Address command. It is a value returned by Word 61:60 and Word 103: 100 of the Identify Device command.

  In addition, the storage area of the SSD 10 exists between the storage capacities 104a to 104g.

  In the storage area between the storage capacities 104a and 104b, the management data (management information) 107a for operating the SSD 10 and the logical address of the data converted from the LBA are sectors that are storage units of the NAND memories 104A to 104H. And a logical / physical table 108a for converting to a physical address corresponding to. The management data 107a and the logical / physical table 108a are data that cannot be accessed using the LBA as a key, and are recorded in fixed areas in the NAND memories 104A to 104H by a fixed access path.

  In the storage area between the storage capacities 104b and 104c, the S.P. M.M. A. R. T.A. Log data 107b is stored. S. M.M. A. R. T.A. The log data 107b is accessed using the LBA as a key when recorded inside the firmware, and is not accessed from the host device 8 by a normal Read command or Write command.

  S. M.M. A. R. T.A. The log management area header 107c of the log data 107b is provided with a count value based on power-on counted by the PCC 103A, and a command trace pointer 0 and a command trace pointer 1 indicating a storage area for storing a trace result at the time of command tracing. ing.

  For example, an unused storage area having a storage capacity of 2 MB is set in the storage area between the storage capacities 104c and 104d. This is because the minimum storage unit of LBA is 8 sectors and is a storage unit corresponding to 4 KB (a large storage unit is 1 MB), but the actual minimum recording unit of data is naturally 1 sector, so 1 MB By providing an empty storage area with the above storage capacity, S.I. M.M. A. R. T.A. This is because the log data 107b and the data recorded below the storage capacity 104d are handled independently.

  The storage area between the storage capacities 104d and 104e is unused, and the storage capacities 104d and 104e have the same value except in special cases.

  The storage area between the storage capacities 104e and 104f is a storage area used for the OEM, and the unique information 107e determined by the OEM request is written as described above.

  A storage area between the storage capacities 104f and 104g is a storage area used by the OEM or the user, and data is written according to the setting of the OEM or the user.

  The storage area of the storage capacity 104g is a storage area used by the user, and data is written according to user settings.

  The storage capacities 104a to 104g satisfy the relationship represented by the following formula 2.

Storage capacity 104a> Storage capacity 104b> Storage capacity 104c> Storage capacity 104d
≧ Storage capacity 104e ≧ Storage capacity 104f ≧ Storage capacity 104g
At the time of shipment from the manufacturer (Vender), the storage capacities 104d to 104g have the same value.

(Configuration of NAND memory)
FIG. 5 is a schematic configuration diagram of a NAND memory according to the embodiment of the present invention. Since the NAND memories 104A to 104H have the same function and configuration, the NAND memory 104A will be described. As an example, the numbers 0 to 7 attached to the left of the sector 1042 indicate the sector number.

  The NAND memory 104A is composed of a plurality of blocks 1040. The block 1040 is composed of 1024 clusters 1041, and the cluster 1041 is further composed of eight sectors 1042.

(Operation)
FIG. 6 is a flowchart showing command trace in the information processing apparatus 1 according to the embodiment of the present invention. Hereinafter, the operation of the information processing apparatus 1 will be described with reference to FIGS. 1 to 5.

First, when the user turns on the power by operating the power switch 25 of the information processing apparatus 1 (S1), the south bridge 113 gives an activation instruction to the SSD 10 (S2), and the NAND memory 104A of the SSD 10 The OS stored in .about.104H is read into the information processing apparatus 1 and activated. In the SSD 10, first, the PCC 103A is incremented by the control unit 103 (S3), and the temperature sensor 101, the NAND memories 104A to 104H, and the DRAM 105 are energized. Next, in the control unit 103, the boot loader included in the management data 107a of the SSD 10 reads the firmware (FW) stored in the NAND memories 104A to 104H into the DRAM 105 and expands it. The firmware developed in the DRAM 105 further reads the storage state stored in the NAND memories 104A to 104H. Thereafter, the SSD 10 performs a normal operation (S4).

  When the control unit 103 of the SSD 10 receives a command as an access request to the NAND memories 104A to 104H based on an input operation from the keyboard 23a by the user in the information processing apparatus 1, for example, the control unit 103 is included in the log management area header 107c. It is confirmed whether the count value of the PCC 103A is an even number or an odd number (S6). Here, when the count value of the PCC 103A is an even number (Yes in S6), the command traced in the storage area defined in advance in the NAND memories 104A to 104H is stored as the first storage area. In this command trace, commands other than reading and reset are traced. One record is 32 bytes, and the latest 256 commands are stored in the storage area when executing the command trace.

  When the count value of the PCC 103A is an odd number (No in S6), the command traced in the storage areas defined in advance in the NAND memories 104A to 104H is stored as the second storage area.

  When the SSD 10 receives a command (for example, a standby command) for ending the operation of the information processing apparatus 1 based on an input operation from the keyboard 23a by the user after the command trace is completed, for example, the SSD 10 displays the display screen 31a. The end screen of the information processing apparatus 1 is displayed at the same time, and the current state is stored in the NAND memories 104A to 104H (S9). Here, the “state” refers to a storage state of information stored in the NAND memories 104A to 104H as the SSD 10 operates.

  Next, based on the end screen displayed on the display screen 31a, for example, when the user performs a power shutdown operation using the keyboard 23a, a power shutdown request signal is output to the CPU 115 via the south bridge 113. The CPU 115 terminates the operation of each unit of the information processing apparatus 1 based on the power shutoff request signal, shuts off the supply of power to the SSD 10 and terminates the operation.

  As described above, when the command trace result is stored in the NAND memories 104A to 104H, the count value of the PCC 103A is referred to. When the count value is an even number, the count value is stored in the first storage area of the NAND memories 104A to 104H. When the value is an odd number, it is stored in the second storage area of the NAND memories 104A to 104H, so that the result of the command trace executed at the previous activation can be saved.

  That is, the failure analysis can be performed reliably by storing the command trace result in a different storage area from the storage area storing the command trace result at the previous activation.

  In the command trace described above, the trace result of the command trace is stored in the first storage area or the second storage area based on whether the count value of the PCC 103A is an even number or an odd number. The storage area is not limited to the above-described contents, and may be stored in a predetermined order in the first to nth storage areas, for example.

  As for the storage method, when the count value of the PCC 103A is an even number, the trace results of the command trace are stored in a plurality of storage areas provided as the first storage area, respectively, and when the count value of the PCC 103A is an odd number The same trace result may be stored in a plurality of storage areas such that the command trace trace results are stored in a plurality of storage areas provided as the second storage area. By doing so, the trace result of the command trace can be saved more reliably.

  Further, the selection of the storage area based on the count value of the PCC 103A described above is not limited to storing the command trace result, but can be applied to other information storage methods such as event log storage. is there.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  According to the present invention, it is possible to reliably and easily perform debugging and failure analysis of a storage area where wear leveling is performed.

Claims (8)

An information processing apparatus,
An information processing apparatus main body;
A storage media drive accommodated in the information processing apparatus body;
Comprising
The information processing apparatus main body has main control means for controlling power-on of the storage media drive based on a power-on operation of a power operation unit,
The storage media drive is
A storage memory having a plurality of storage areas capable of writing information and reading the information;
A counter whose count value is incremented when the power is turned on;
When there is an access request to the storage memory, memory control means for storing the content of the access request in a storage area of the storage memory determined based on the value of the counter;
Having
Information processing device.   The information processing apparatus according to claim 1, wherein the storage media drive is a nonvolatile semiconductor memory drive.   The memory control unit of the storage media drive stores the content of the access request in the first storage area of the storage memory when the value of the counter when the access request to the storage memory is received is an even number. The information processing apparatus according to claim 1, wherein when the value of the counter when receiving an access request to the storage memory is an odd number, the content of the access request is stored in a second storage area of the storage memory. .   The memory control means of the storage media drive provides the content of the access request as a first storage area of the storage memory when the value of the counter is an even number when receiving the access request to the storage memory Each of the plurality of storage areas, and when the value of the counter is odd when receiving an access request to the storage memory, the contents of the access request are stored in the second storage area of the storage memory. The information processing apparatus according to claim 1, wherein each of the information processing apparatuses is stored in a plurality of storage areas. A storage media drive accommodated in the information processing apparatus body,
A storage memory having a plurality of storage areas capable of writing information and reading information;
A counter whose count value is incremented when the power is turned on;
When there is an access request to the storage memory, memory control means for storing the content of the access request in a storage area of the storage memory determined based on the count value;
A storage media drive comprising:   6. The storage media drive according to claim 5, wherein the storage media drive is a non-volatile semiconductor memory drive.   When the value of the counter when receiving an access request to the storage memory is an even number, the memory control means stores the content of the access request in a first storage area of the storage memory, and the storage memory 6. The storage media drive according to claim 5, wherein when the value of the counter at the time of receiving an access request is an odd number, the content of the access request is stored in a second storage area of the storage memory.   When the value of the counter when the memory control unit receives an access request to the storage memory is an even number, a plurality of storage areas provided as contents of the access request as a first storage area of the storage memory When the count value when the access request to the storage memory is received is an odd number, the contents of the access request are stored as a second storage area of the storage memory. 6. The storage media drive according to claim 5, wherein the storage media drive is stored in each area.

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