JP2010515275A5 - - Google Patents

Claims (15)

Forming a plurality of vias in a semiconductor wafer;
Making at least some of the plurality of vias conductive;
Forming a metallization layer on the plurality of vias using the same process used to render at least some of the plurality of vias conductive:
Semiconductor wafer processing method.   The step of making at least some of the plurality of vias conductive includes the step of disposing one of a metal, a metal alloy, and polysilicon in the via, wherein the disposing step forms the metallized layer. The method of claim 1, wherein the method is performed substantially simultaneously. The step of arranging includes
Applying a solid photoresist to the semiconductor wafer;
Patterning the solid photoresist;
Applying a seed layer to the areas exposed by the patterning;
Disposing a plating material in the via and plating the seed layer to form the metallization layer:
The method of claim 2. Applying the solid photoresist comprises applying a solid photoresist over at least one via such that the via is not filled with the plating material during the step of plating the seed layer:
The method of claim 3. The step of forming the plurality of vias comprises the step of forming an annular via:
The method of claim 1. Forming the annular via comprises forming the annular via partially passing through the semiconductor wafer:
The method of claim 5. The method further includes filling the annular via with a conductive material:
The method of claim 6. The method further comprises removing a central post surrounded by the annular via:
The method of claim 7. Making at least some of the plurality of vias conductive;
Filling the annular via with an insulator;
Doping a central post surrounded by the annular via to make the central post conductive;
The method of claim 6. The doping step is performed in a front-end process, and the method further comprises removing the bottom of the semiconductor wafer:
The method of claim 9. The method further includes filling the via after formation of the at least one metallization layer:
The method of claim 1. The semiconductor wafer is a blank wafer and the method forms devices on the semiconductor wafer after forming the plurality of vias and making at least some of the plurality of vias conductive. The process further includes:
The method of claim 1. The semiconductor wafer is a device-mounted semiconductor wafer, and the method further comprises performing a back-end process on the device-mounted semiconductor wafer after making at least some of the plurality of vias conductive.
The method of claim 1. The step of performing the back-end process includes a step of forming a metal-X layer through a plating process, where X is an integer:
The method of claim 13. The step of executing the back-end process further comprises stopping for an intermediate device inspection:
The method of claim 13.