JP2010283580A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of obtaining a satisfactory image by reducing a conversion error resulting from the variation of a delay time between control signals. <P>SOLUTION: A control signal adjustment circuit 45 receives a start pulse ϕRDLIST_DLY 13, a count enable signal ϕCNTEN_DLY 14 and an RDL latch signal ϕRDLLAT_DLY 15, and outputs the ϕCNTEN_DLY 14 and the ϕRDLLAT_DLY 15 while uniformizing the falling timing of them by ORing and outputting the ϕRDLST_DLY 13 and the ϕCNTEN_DLY 14. Consequently, timing when a counter circuit 42 ends a count operation is matched with timing when an RDL latch circuit 43 holds outputs of each of an inverting circuit 40a and a NAND circuit 40b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device used for a digital camera / digital video camera, an endoscope, and the like.

  In recent years, digital cameras, digital video cameras, and endoscopes have been reduced in size and power consumption, and accordingly, solid-state imaging devices have been required to be reduced in size and power consumption. In order to realize the downsizing and low power consumption, a solid-state imaging device in which an A / D converter is configured by a digital circuit has been proposed (for example, see Patent Document 1). Also, a so-called column A / D type solid-state imaging device having an A / D converter for each pixel column in order to read out a signal from a sensor at high speed has been proposed (known technique).

  FIG. 8 shows the configuration of the A / D converter 201 described in Patent Document 1. The A / D converter 201 includes a RingDelayLine (RDL) 102, a counter circuit 103, and an RDL latch circuit 104.

  The RDL102 inverts and outputs an input signal, and a plurality of inverting circuits 101a whose delay time varies depending on the power supply voltage, and one NAND circuit 101b that operates by receiving a pulse signal at one input terminal in a ring shape It is arranged and configured. When the input voltage is connected to the power supply of the inverting circuit 101a and the NAND circuit 101b, the RDL 102 outputs a clock signal φORDL101 having a frequency corresponding to the magnitude of the input voltage.

  The counter circuit 103 counts the falling edge of the clock signal φORDL101 output from the RDL 102, and outputs the count result as binary digital data φOCNT106. The RDL latch circuit 104 holds the outputs of the inverting circuits 101a and the NAND circuit 101b, and outputs the held values as binary digital data φOLAT107 indicating the position information of the clock signal φORDL101 in the RDL102.

  Also outputs signals (start pulse φRDLST102, latch signal φRDLLAT103, count enable signal φCNTEN104, counter reset signal φCNTRST105) that control each block (RDL102, counter circuit 103, RDL latch circuit 104) constituting the A / D converter 201 A control signal output circuit 105 is separately provided.

  The operation of the A / D converter 201 having the above configuration will be described using the timing chart shown in FIG. First, φCNTRST105 becomes High at timing T101. As a result, the count value φOCNT 106 held by the counter circuit 103 is reset. Thereafter, when φCNTRST105 becomes Low at timing T102, the counter circuit 103 ends the reset operation.

  Subsequently, φCNTL104 becomes High at the same time as φRLDST102 becomes High at timing T103. As a result, the RDL 102 outputs the clock signal φORDL101 having a frequency corresponding to the magnitude of the input voltage, and at the same time, the counter circuit 103 starts the count operation at the falling of the φORDL101.

  Subsequently, φRDLLAT103 becomes High at timing T104. Thereafter, at timing T105, φCNTEN104 goes low, and at the same time φRDLLAT103 goes low. Thereby, at the same time as the counting operation of the counter circuit 103 is completed, the RDL latch circuit 104 holds the outputs of the inverting circuits 101a and the NAND circuit 101b. Thereafter, φRDLST102 becomes Low at timing T106. As a result, the RDL 102 finishes outputting the clock signal φORDL101.

  By the above operation, the count number φOCNT106 when a certain period (T103-T105) elapses and the position information φOLAT107 of φORDL101 in the RDL102 can be obtained. Thereafter, the A / D converter 201 outputs a digital signal having the count number φOCNT106 as the upper bits and the position information φOLAT107 as the lower bits as an A / D conversion result. Through the above operation, the A / D converter 201 described in Patent Document 1 can obtain a digital signal corresponding to the magnitude of the input voltage.

JP 2006-287879 A

  FIG. 10 shows a column A / D in which an A / D converter 201 described in Patent Document 1 is provided for each pixel column in order to realize downsizing and low power consumption and to read out a signal from a sensor at high speed. 1 shows the configuration of a solid-state imaging device of the type. FIG. 11 shows the configuration of an A / D converter 201 used in this solid-state imaging device.

  10 includes a pixel array 2, a vertical scanning circuit 3, an A / D converter 201 (ADC1, ADC2, ADC3, ADC4), an AD latch circuit 5, a control signal output circuit 6, And a horizontal scanning circuit 7.

  The pixel array 2 has a structure in which pixels 1 that have at least photoelectric conversion elements and output pixel signals corresponding to the amount of incident light are arranged two-dimensionally (in the illustrated example, 4 rows and 4 columns). The vertical scanning circuit 3 performs row selection of the pixel array 2 by row selection signals φV1, φV2, φV3, and φV4. The A / D converter 201 is arranged for each pixel column of the pixel array 2, and performs analog / digital conversion on the pixel signal φPIX1 read from the pixel 1. The AD latch circuit 5 holds the output of the A / D converter 201. The control signal output circuit 6 outputs signals (φRDLST3, φCNTEN4, φRDLLAT5, φCNTRST6, φADLAT8) for controlling the A / D converter 201 and the AD latch circuit 5. The horizontal scanning circuit 7 controls the AD latch circuit 5 by the column selection signals φH1, φH2, φH3, and φH4, and outputs the held digital signal for each column.

  The control signal output circuit 6 outputs a start pulse φRDLST3, a count enable signal φCNTEN4, and a latch signal φRDLLAT5 to control each block (RDL102, counter circuit 103, RDL latch circuit 104) constituting the A / D converter 201 To do. The signals φRDLST3, φCNTEN4, and φRDLLAT5 are input to the RDL 102, the counter circuit 103, and the RDL latch circuit 104, respectively. At this time, since the circuit configurations of the RDL 102, the counter circuit 103, and the RDL latch circuit 104 are different, the load capacitance connected to each signal line is also different. Therefore, φRDLST3, φCNTEN4, and φRDLLAT5 are input to each block with different delay times. In the column A / D type solid-state imaging device, since a large number of A / D converters 201 are connected to one signal line, variation in delay time increases. In the A / D converter 201 described in Patent Document 1, a conversion error due to this variation in delay time occurs. As a result, the problem is that the image quality is degraded.

  A conversion error due to delay time variation will be described with reference to FIGS. As shown in FIG. 11, the delayed signals of φRDLST3, φCNTEN4, φRDLLAT5 input to each A / D converter 201 (ADC1, ADC2, ADC3, ADC4) are φRDLST_DLY13 (ADC1, ADC2, ADC3, ADC4), respectively. , ΦCNTEN_DLY14 (ADC1, ADC2, ADC3, ADC4), φRDLLAT_DLY15 (ADC1, ADC2, ADC3, ADC4).

  Here, the variation of the delay time is considered in two cases. First, the operation when the delay time Tcntdly4 of φCNTEN_DLY14 and the delay time Trdldly3 of φRDLST_DLY13 are equal and the delay time Tlatdly5 of φRDLLAT_DLY15 is smaller than the delay times of the other two signals will be described. Second, the operation when the delay time Tcntdly4 of φCNTEN_DLY14 is equal to the delay time Tlatdly5 of φRDLLAT_DLY15 and the delay time Trdldly3 of φRDLST_DLY13 is larger than the delay times of the other two signals will be described. Actually, since each signal has a different delay time, the following problems occur in combination. Note that the delay of the counter reset signal φCNTRST6 is not related to the subject conversion error, and therefore it will be assumed that the delay of φCNTRST does not occur. In addition, it is assumed that the position information φOLAT107 in the RDL102 of φORDL101 output from the RDL latch circuit 104 is 4-bit binary digital data.

  First, the operation in the first case will be described with reference to the timing chart of FIG. More specifically, the row selection signal φV1 becomes High, the pixel 1 (P11, P12, P13, P14) in the first row is selected, and the pixel signal φPIX1 (P11, P12, P13, P14) is A / D The operation of the A / D converter 201 when it is input to the converter 201 will be described.

  First, φCNTRST6 becomes High. As a result, the count value φOCNT 106 held by the counter circuit 103 is reset. Thereafter, when φCNTRST6 becomes Low, the counter circuit 103 ends the reset operation.

  Subsequently, the count enable signal φCNTEN4 becomes High simultaneously with the start pulse φRLDST3 becoming High. Thereby, at timing T111, φCNTEN_DLY14 becomes High, and simultaneously, φRDLST_DLY13 becomes High. Therefore, at the timing T111, the RDL 102 outputs the clock signal φORDL101 having a frequency corresponding to the magnitude of the pixel signal φPIX1, and at the same time, the counter circuit 103 starts the count operation of the falling of φORDL101.

  Subsequently, φRDLLAT5 becomes High. Then, φRDLLAT5 goes Low at the same time as φCNTEN4 goes Low. As a result, φRDLLAT_DLY15 becomes Low at timing T112 and φCNTEN_DLY14 becomes Low at timing T113. Therefore, after the RDL latch circuit 104 takes in the outputs of the inverting circuits 101a and the NAND circuit 101b at the timing T112, the counter circuit 103 ends the counting operation at the timing T113. That is, the lower bit A / D conversion period Tad2 is shorter than the upper bit A / D conversion period Tad1, which is a desired A / D conversion period.

  At this time, the count number φOCNT106 at the timing T112 when the RDL latch circuit 104 takes in the outputs of the inversion circuits 101a and NAND circuits 101b is different from the count number φOCNT106 at the timing T113 when the counter circuit 103 finishes the counting operation. As a result, the A / D conversion result obtained with the count number φOCNT106 at the timing T113 as the upper bit and the position information φOLAT107 at the timing T112 as the lower bit is obtained from the count number φOCNT106 and the position information φOLAT107 at the timing T114. Shows the same result as the / D conversion result. Therefore, the above A / D conversion result is obtained from the A / D conversion obtained from the count number φOCNT106 and the position information φOLAT107 at the timing T113 when the upper bit A / D conversion period Tad1 as the desired A / D conversion period ends. There is a 6-count shift in the lower order bits. As described above, there is a technical problem that a conversion error due to variations in delay time occurs.

  Next, the operation in the second case will be described using the timing chart of FIG. More specifically, A / D conversion when the row selection signal φV1 becomes High and the pixel signal φPIX1 (P11, P12, P13, P14) of the first row is input to the A / D converter 201. The operation of the device 201 will be described.

  First, the counter reset signal φCNTRST6 becomes High. As a result, the count value φOCNT 106 held by the counter circuit 103 is reset. Thereafter, when φCNTRST6 becomes Low, the counter circuit 103 ends the reset operation.

  Subsequently, the count enable signal φCNTEN4 becomes High simultaneously with the start pulse φRLDST3 becoming High. As a result, φCNTEN_DLY14 becomes High at timing T121 and φRDLST_DLY13 becomes High at timing T122. Therefore, after the counter circuit 103 starts counting the falling of φORDL101 at timing T121, the RDL 102 outputs a clock signal φORDL101 having a frequency corresponding to the magnitude of the input voltage at timing T122.

  Subsequently, φRDLLAT5 becomes High. Then, φRDLLAT5 goes Low at the same time as φCNTEN4 goes Low. Thereby, at timing T123, φRDLLAT_DLY15 becomes Low, and at the same time, φCNTEN_DLY14 becomes Low. Therefore, at the timing T123, the counter circuit 103 ends the counting operation, and at the same time, the RDL latch circuit 104 takes in the outputs of the inverting circuits 101a and the NAND circuit 101b.

  In such a case, as shown in FIG. 13, the actual A / D conversion period Tad3 becomes shorter than the desired A / D conversion period Tad1, so the A / D converter 4 has 3 counts in the lower bits. Conversion error occurs. As described above, there is a technical problem that a conversion error due to variations in delay time occurs.

  Furthermore, the delay time variation between each signal differs for each A / D converter 4 (ADC1, ADC2, ADC3, ADC4), so for each A / D converter 4 (ADC1, ADC2, ADC3, ADC4) There is a technical problem that different conversion errors occur.

  The present invention has been made in view of the problems described above, and in a column A / D type solid-state imaging device, conversion errors due to variations in delay time between control signals are reduced, and a good image is obtained. An object of the present invention is to provide a solid-state imaging device capable of performing the above-described operation.

  The present invention has been made in order to solve the above-described problem, and includes a pixel array in which a plurality of pixels each having a photoelectric conversion element are two-dimensionally arranged, and is arranged for each pixel column of the pixel array. A plurality of A / D converters that convert the read pixel signals into digital signals, and a control signal that outputs a start pulse, a count enable signal, and a latch signal to the plurality of A / D converters The A / D converter includes a plurality of delays for transmitting a clock signal with a delay time corresponding to an analog signal during a period from a first state change to a second state change of the start pulse. An annular delay circuit having a unit and outputting the clock signal at a frequency corresponding to the analog signal; a period from a first state change to a second state change of the count enable signal; A counter for counting the number of state changes of the clock signal output from the extension circuit, and a period from the first state change to the second state change of the latch signal from the first state change of the count enable signal A latch circuit for storing a transmission position of the clock signal at the time of the second state change of the latch signal when at least one part overlaps with a period until the second state change, and an output of the counter circuit And a time A / D conversion circuit for generating a digital signal from the output of the latch circuit, and a correction latch signal so that the second state change of the latch signal is aligned with the second state change of the count enable signal And a control signal adjustment circuit that outputs the correction latch signal to the latch circuit as the latch signal.

  In the solid-state imaging device of the present invention, the control signal output circuit may include the count enable signal and the latch so that the second state change of the latch signal comes after the second state change of the count enable signal. The control signal adjustment circuit generates a correction latch signal using a logical product of the count enable signal and the latch signal.

  In the solid-state imaging device of the present invention, the control signal adjustment circuit further generates a corrected start pulse so that the first state change of the start pulse is aligned with the first state change of the count enable signal, The correction start pulse is output to the annular delay circuit as the start pulse.

  In the solid-state imaging device of the present invention, the control signal output circuit includes the count enable signal and the start signal so that the first state change of the start pulse comes after the first state change of the count enable signal. The control signal adjustment circuit generates a correction start pulse by using a logical sum of the count enable signal and the latch signal.

  In the solid-state imaging device according to the present invention, the control signal adjustment circuit further includes a circuit that delays the count enable signal.

  In the solid-state imaging device of the present invention, the time A / D conversion circuit is arranged between a pixel array and the control signal adjustment circuit.

  In the solid-state imaging device according to the present invention, the start pulse is input to a delay unit disposed at a position closest to the control signal adjustment circuit among the plurality of delay units.

  According to the present invention, for each A / D converter, the difference between the timing at which the counter finishes the counting operation and the timing at which the latch circuit stores the transmission position of the clock signal is reduced, thereby reducing the conversion error. And good images can be obtained.

1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of an A / D converter according to a first embodiment of the present invention. 3 is a timing chart showing an operation of the solid-state imaging device according to the first embodiment of the present invention. 1 is a circuit diagram showing a configuration of an A / D converter according to a first embodiment of the present invention. 3 is a timing chart showing an operation of the solid-state imaging device according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of an A / D converter according to a second embodiment of the present invention. 6 is a timing chart showing an operation of the solid-state imaging device according to the second embodiment of the present invention. It is a circuit diagram which shows the structure of the conventional A / D converter. It is a timing chart which shows operation | movement of the conventional A / D converter. 1 is a block diagram illustrating a configuration of a column A / D type solid-state imaging device. FIG. It is a circuit diagram which shows the structure of the A / D converter used for a column A / D system. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the solid-state imaging device according to the present embodiment. A solid-state imaging device according to this embodiment includes a pixel array 2, a vertical scanning circuit 3, an A / D converter 4 (ADC1, ADC2, ADC3, ADC4), an AD latch circuit 5, a control signal output circuit 6, And a horizontal scanning circuit 7.

  The pixel array 2 has a structure in which pixels 1 having at least photoelectric conversion elements and outputting a pixel signal φPIX1 corresponding to the amount of incident light are arranged two-dimensionally (4 rows and 4 columns in the illustrated example). The vertical scanning circuit 3 performs row selection of the pixel array 2 by row selection signals φV1, φV2, φV3, and φV4. The A / D converter 4 (ADC1, ADC2, ADC3, ADC4) is arranged for each pixel column of the pixel array 2, and performs analog / digital conversion on the pixel signal φPIX1 read from the pixel 1. The AD latch circuit 5 holds the output of the A / D converter 4. The control signal output circuit 6 outputs signals (φRDLST3, φCNTEN4, φRDLLAT5, φCNTRST6, φADLAT8) for controlling the A / D converter 201 and the AD latch circuit 5. The horizontal scanning circuit 7 controls the AD latch circuit 5 by the column selection signals φH1, φH2, φH3, and φH4, and outputs the held digital signal for each column.

  FIG. 2 shows the configuration of the A / D converter 4. The A / D converter 4 includes a time A / D converter 44 and a control signal adjustment circuit 45. The time A / D converter 44 includes a RingDelayLine (RDL) 41, a counter circuit 42, and an RDL latch circuit 43.

  The RDL41 inverts and outputs an input signal and has a plurality of inverting circuits 40a whose delay time varies depending on the power supply voltage, and one NAND circuit 40b that operates by receiving a pulse signal at one input terminal in a ring shape. It is arranged and configured. When the pixel signal φPIX1 output from the pixel 1 is connected to the power supply of each inversion circuit 40a and NAND circuit 40b, the RDL 41 outputs a clock signal φORDL2 having a frequency corresponding to the magnitude of the pixel signal φPIX1.

  The counter circuit 42 counts the falling edge of the clock signal φORDL2 output from the RDL 41, and outputs the count result as binary digital data φOCNT7. The RDL latch circuit 43 holds the output of each inverting circuit 40a and NAND circuit 40b, and outputs the held value as position information in the RDL 41 of the clock signal φORDL2 as binary digital data φOLAT9.

  Control signal adjustment circuit 45 receives φRDLST_DLY13, φCNTEN_DLY14, and φRDLLAT_DLY15, which are delay signals of start pulse φRDLST3, count enable signal φCNTEN4, RDL latch signal φRDLLAT5 output from control signal output circuit 6, and takes the logical sum of φRDLST_DLY13 and φCNTEN_DLY14. An OR circuit 45a-1 for outputting, and an AND circuit 45a-2 for taking and outputting the logical product of φCNTEN_DLY14 and φRDLLAT_DLY15. With this configuration, the control signal adjustment circuit 45 outputs the aligned rising timings of φCNTEN_DLY14 and φRDLST_DLY13 and outputs the aligned falling timings of φCNTEN_DLY14 and φRDLLAT_DLY15.

  The time A / D converter 44 is disposed between the control signal adjustment circuit 45 and the pixel array 2. Further, among the plurality of inverting circuits 40a and one NAND circuit 40b constituting the RDL 41, the NAND circuit 40b is disposed at a position closest to the control signal adjustment circuit 45.

  Next, the operation of the solid-state imaging device according to this embodiment will be described. First, a first operation example will be described using the timing chart shown in FIG. The operation of A / D converter 4 (ADC1, ADC2, ADC3, ADC4) will be described only for A / D converter 4 (ADC4), and other A / D converter 4 (ADC1, ADC2, ADC3) Since the operation is the same as that of the A / D converter 4 (ADC4), description thereof is omitted.

  First, at timing T1, the row selection signal φV1 becomes High. Thereby, the pixel 1 (P11, P12, P13, P14) in the first row controlled by the row selection signal φV1 is selected, and the pixel signal φPIX1 (P11, P12, P14) of the pixel 1 (P11, P12, P13, P14) is selected. P13, P14) are output to the A / D converter 4, respectively. At this time, the other row selection signals φV2, φV3, φV4 are kept low.

  Subsequently, at timing T2, the counter reset signal φCNTRST6 becomes High. As a result, the count value φOCNT7 held by the counter circuit 42 is reset. Thereafter, φCNTRST6 becomes Low, and the counter circuit 42 ends the reset operation.

  Subsequently, as soon as φRDLST3 becomes High, φCNTEN4 becomes High. At this time, different loads are connected to the signal lines φRDLST3, φCNTEN4, and φRDLLAT5 output from the control signal output circuit 6, respectively. Therefore, φRDLST3, φCNTEN4, and φRDLLAT5 are input to each A / D converter 4 with different delay times Trdldly3, Tcntdly4, and Tlatdly5.

  Below, the delay signals at the input of each A / D converter 4 (ADC1, ADC2, ADC3, ADC4) are φRDLST_DLY13 (ADC1, ADC2, ADC3, ADC4), φCNTEN_DLY14 (ADC1, ADC2, ADC3, ADC4), φRDLLAT_DLY15 ( ADC1, ADC2, ADC3, ADC4). Note that the delay of φCNTRST6 need not be considered in describing the present invention, and will be described assuming that φCNTRST6 is not delayed.

  After φRDLST3 and φCNTEN4 become High, φCNTEN_DLY14 (ADC4) becomes High at timing T3, and φRDLST_DLY13 (ADC4) becomes High at timing T4. The control signal adjustment circuit 45 receives φCNTEN_DLY14 (ADC4) and φRDLST_DLY13 (ADC4), and starts RDL41 with a signal φRDLST23 (correction start pulse) that aligns the rise timing of φCNTL_DLY13 (ADC4) with the rise timing of φCNTEN_DLY14 (ADC4). Output as a pulse. More specifically, the OR circuit 45a-1 receives CNTEN_DLY14 (ADC4) and φRDLST_DLY13 (ADC4) and outputs a signal φRDLST23 obtained by ORing the signals as a start pulse of RDL41.

  As a result, at timing T3, the RDL outputs the clock signal φORDL2 having a frequency corresponding to the pixel signal φPIX1 (P14), and at the same time, the counter circuit starts the count operation of the falling of φORDL2. Thereafter, after a certain period of time, φRDLLAT5 becomes High.

  Subsequently, φRDLLAT5 goes low simultaneously with φCNTEN4 going low. Then, φCNTEN_DLY14 (ADC4) becomes Low at timing T5, and φRDLLAT_DLY15 (ADC4) becomes Low at timing T6. The control signal adjustment circuit 45 receives φCNTEN_DLY14 (ADC4) and φRDLLAT_DLY15 (ADC4), and outputs a signal φRDLLAT25 (correction latch signal) that aligns the falling timing of φLATCH_DLY15 (ADC4) to the falling timing of φCNTEN_DLY14 (ADC4). Output as 43 latch signals. More specifically, the AND circuit 45a-2 receives φCNTEN_DLY14 (ADC4) and φRDLLAT_DLY15 (ADC4), and outputs a signal φRDLLAT25 obtained by logical AND thereof as a latch signal of the RDL latch circuit 43.

  Thereby, at the timing T5, the counter circuit 42 ends the counting operation, and at the same time, the RDL latch circuit 43 holds the outputs of the inverting circuits 40a and the NAND circuit 40b. Subsequently, when φRDLST3 becomes Low, φRDLST_DLY13 becomes Low at timing T7, and RDL41 ends the output of the clock signal φORDL2. Further, after the AD latch signal φADLAT8 becomes High at timing T8, the AD latch signal φADLAT8 becomes Low at timing T9. Thereby, the AD latch circuit 5 holds the output of the A / D converter 4 (ADC1, ADC2, ADC3, ADC4).

  After that, φV1 becomes Low at timing T10. As a result, the pixel 1 (P11, P12, P13, P14) in the first row is in a non-selected state. Subsequently, at timing T11, φH1 becomes High, so that the AD latch circuit 5 outputs a digital signal corresponding to the pixel signal φPIX1 (P11) in the first column. Further, when φH1 becomes high at the same time as φH1 becomes low at timing T12, the AD latch circuit 5 outputs a digital signal corresponding to the pixel signal φPIX1 (P12) in the second column.

  Thereafter, the column selection signals φH2, φH3, and φH4 are sequentially switched at timing T13, timing T14, and timing T15, whereby the read operation for the first row is completed. Subsequently, φV2 becomes High at timing T16. Thereby, pixel 1 (P21, P22, P23, P24) in the second row is selected. Thereafter, by performing the same operation as in the first row, the pixel signal reading operation in the second row is completed. For the third and fourth rows, the same operation as in the first and second rows is performed to complete the readout operation for all pixels.

  Next, a second operation example will be described. For convenience of explanation, as shown in FIG. 4, the signals output from the control signal adjustment circuit 45 to the RDL 41, the counter circuit 42, and the RDL latch circuit 43 are denoted as φRDLST33, φCNTEN34, and φRDLLAT35, respectively.

  The operation of the A / D converter 4 will be described using the timing chart shown in FIG. In the second operation example, the rising timing of the start pulse φRDLST3 output from the control signal output circuit 6 and the falling timing of the latch signal φRDLLAT5 are different from those in the first operation example. Specifically, after φCNTEN4 becomes High, φRDLST3 becomes High when a certain period of time Tdelay1 has elapsed, and after φCNTEN4 becomes Low, φRDLLAT5 becomes Low when a certain period of time Tdelay2 has elapsed This is different from the first operation example.

  Thus, by taking the logical sum of φCNTEN_DLY14 and φRDLST_DLY13 regardless of how the delay times of each signal vary, the rise timing of φCNTL_DLY13 can be aligned with the rise timing of φCNTEN_DLY14, and the logical product of φCNTEN_DLY14 and φRDLLAT_DLY15 By taking this, the falling timing of φRDLLAT_DLY13 can be aligned with the falling timing of φCNTEN_DLY14. Since other operations are the same as those in the first operation example, description thereof is omitted.

  First, φCNTRST6 becomes High. As a result, the count value φOCNT7 held by the counter circuit 42 is reset. Thereafter, φCNTRST6 becomes Low, and the counter circuit 42 ends the reset operation.

  Subsequently, after φCNTEN4 becomes High, φRDLST3 becomes High. Then, φCNTEN_DLY14 becomes High at timing T21, and φRDLST_DLY13 becomes High at timing T22. The OR circuit 45a-1 receives φCNTEN_DLY14 and φRDLST_DLY13, and outputs a signal φRDLST33 obtained by ORing them as a start pulse of RDL41. Therefore, the output signal φRDLST33 of the OR circuit 45a-1 becomes High at timing T21. As a result, at timing T21, the RDL 41 outputs the clock signal φORDL2 having a frequency corresponding to the pixel signal φPIX1, and at the same time, the counter circuit 42 starts the count operation of the falling of φORDL2.

  After that, φRDLLAT5 becomes High. Then, φRDLLAT_DLY15 becomes High at timing T23. Subsequently, after φCNTEN4 becomes Low, φRDLLAT5 becomes Low. Thereby, φCNTEN_DLY14 becomes Low at timing T24, and φRDLLAT_DLY15 becomes Low at timing T25. The AND circuit 45a-2 receives φCNTEN_DLY14 and φRDLLAT_DLY15, and outputs a signal φRDLLAT35 obtained by ANDing them as a latch signal of the RDL latch circuit 43. Therefore, the output signal φRDLLAT35 of the AND circuit 45a-2 becomes Low at timing T24. Therefore, at the timing T24, the counter circuit 42 ends the counting operation, and at the same time, the RDL latch circuit 43 holds the outputs of the inverting circuits 40a and the NAND circuit 40b.

  Subsequently, φRDLST3 becomes Low. Thereafter, when φRDLST_DLY13 becomes Low, RDL41 finishes outputting the clock signal φORDL2. By the above operation, it is possible to obtain the count number φOCNT7 when a certain period (T21-T24) elapses and the position information φOLAT9 of φORDL2 in the RDL41. Thereafter, the A / D converter 4 outputs a digital signal having the count number φOCNT7 as the upper bit and the position information φOLAT9 as the lower bit as an A / D conversion result.

  With the above operation, the timing at which the counter circuit 42 finishes the counting operation and the timing at which the RDL latch circuit 43 holds the output of each inverting circuit 40a and NAND circuit 40b (the RDL latch circuit 43 stores the transmission position of the clock signal φRDLST33) The timing at which the counter circuit 42 starts the count operation and the timing at which the RDL 41 starts outputting φORDL2 can be aligned. Therefore, according to the present embodiment, it is possible to reduce the conversion error of the A / D converter 4 due to the variation in delay time between the signals, and to obtain a good image.

  Furthermore, using the count enable signal φCNTEN_DLY14 as a reference signal, the rising timing of φCNTL_DLY13 is aligned with the rising timing of φCNTEN_DLY14, and the falling edge of φRDLLAT_DLY15 is aligned with the falling edge of φCNTEN_DLY14. 4 (ADC1, ADC2, ADC3, ADC4) can be the same.

  Since the time A / D converter 44 is arranged between the pixel array 2 and the control signal adjustment circuit 45, the analog part and the digital part can be separated, and the clock signal in the control signal adjustment circuit 45 can be separated. It is possible to prevent the signal level of the pixel signal φPIX1 from fluctuating due to the switching.

  Further, since the NAND circuit 40b is disposed at the position closest to the control signal adjustment circuit 45, the variation in delay time generated in the A / D converter 4 can be reduced.

  The configuration of the control signal adjustment circuit 45 is not limited to the configuration shown in FIGS. 2 and 4, and any configuration that can obtain the function of the control signal adjustment circuit 45 of the present embodiment may be used.

(Second embodiment)
Next, a second embodiment of the present invention will be described. FIG. 6 shows a configuration of the A / D converter 4 according to the present embodiment. The A / D converter 4 according to the present embodiment differs from the A / D converter 4 according to the first embodiment in the configuration of the control signal adjustment circuit 45. The control signal adjustment circuit 45 according to this embodiment receives φCNTEN_DLY14, φRDLST_DLY13, and φRDLLAT_DLY15, takes the logical sum of φCNTEN_DLY14 and φRDLST_DLY13, and outputs the logical product of φCNTEN_DLY14 and φRDLLAT_DLY15. The circuit 45b-2 and the DU45b-3 that receives and delays φCNTEN_DLY14 and outputs it. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

  The operation of the A / D converter 4 according to the present embodiment will be described using the timing chart shown in FIG. Since other operations are the same as those in the first embodiment, description thereof is omitted. Further, description will be made assuming that a delay occurs in each logic circuit of the OR circuit 45b-1, the AND circuit 45b-2, and the DU45b-3. However, the variation in delay time between the logic circuits is not considered, and it is assumed that the OR circuit 45b-1, the AND circuit 45b-2, and the DU45b-3 each generate a delay for the same period Tlogdly1.

  First, φCNTRST6 becomes High. As a result, the count number φOCNT7 held by the counter circuit 42 is reset. Subsequently, after φCNTEN4 becomes High, φRDLST5 becomes High. Then, φCNTEN_DLY14 becomes High at timing T31, and φRDLST_DLY15 becomes High at timing T33.

  The OR circuit 45b-1 receives φCNTEN_DLY14 and φRDLST_DLY13, calculates the logical sum of them, and outputs the result. Therefore, the output signal φRDLST43 of the OR circuit 45b-1 becomes High at timing T32 when Tlogdly1 has elapsed from timing T31. DU45b-3 receives φCNTEN_DLY14 and outputs a signal φCNTEN44 delayed by Tlogdly1. Therefore, the output signal φCNTEN44 of Du45b-3 becomes High at timing T32. Therefore, at the timing T32, the RDL 41 outputs the clock signal φORDL2 having a frequency corresponding to the pixel signal φPIX1, and at the same time, the counter circuit 42 starts the count operation of the falling of φORDL2.

  After that, φRDLLAT5 becomes High. Then, φRDLLAT_DLY15 becomes High at timing T34. Subsequently, after φCNTEN4 becomes Low, φRDLLAT5 becomes Low. Thereby, φCNTEN_DLY14 becomes Low at timing T35, and φRDLLAT_DLY15 becomes Low at timing T37. The AND circuit 45b-2 receives φCNTEN_DLY14 and φRDLLAT_DLY15, takes the logical product thereof, and outputs it. For this reason, the output signal φRDLLAT45 of the AND circuit 45b-2 becomes Low at timing T36 when Tlogdly1 has elapsed from timing T35. At this time, the output signal φCNTEN44 of DU45b-3 also becomes Low. Therefore, at the timing T36, the counter circuit 42 ends the counting operation, and at the same time, the RDL latch circuit 43 holds the outputs of the inverting circuits 40a and the NAND circuit 40b.

  Subsequently, when φRDLST3 becomes Low, φRDLST_DLY13 becomes Low. Thereafter, when φRDLST43 becomes Low, RDL41 finishes outputting the clock signal φORDL2. By the above operation, the count number φOCNT7 when a certain period (T32-T36) elapses and the position information φOLAT9 of φORDL2 in the RDL 41 can be obtained. Thereafter, the A / D converter 4 outputs a digital signal having the count number φOCNT7 as the upper bit and the position information φOLAT9 as the lower bit as an A / D conversion result.

  With the above operation, in this embodiment as well, in the same manner as in the first embodiment, the timing at which the counter circuit 42 finishes the counting operation and the timing at which the RDL latch circuit 43 holds the outputs of the inverting circuits 40a and NAND circuits 40b ( The timing at which the RDL latch circuit 43 stores the transmission position of the clock signal φRDLST43), and the timing at which the counter circuit 42 starts the count operation and the timing at which the RDL 41 starts to output φORDL2 . Therefore, according to the present embodiment, it is possible to reduce the conversion error of the A / D converter due to the delay time variation between the signals.

  Furthermore, since the rising edge of φCNTL_DLY13 is aligned with the rising edge of φCNTEN_DLY14 and the falling edge of φRDLLAT_DLY15 is aligned with the falling edge of φCNTEN_DLY14, the A / D conversion period is the same for each A / D converter 4 (ADC1, ADC2, ADC3, ADC4). can do.

  Since the time A / D converter 44 is arranged between the pixel array 2 and the control signal adjustment circuit 45, the analog part and the digital part can be separated, and the clock signal in the control signal adjustment circuit 45 can be separated. It is possible to prevent the signal level of the pixel signal φPIX1 from fluctuating due to the switching.

  Further, since the NAND circuit 40b is disposed at the position closest to the control signal adjustment circuit 45, the variation in delay time generated in the A / D converter 4 can be reduced.

  Furthermore, since the DU45b-3 is arranged, the conversion error of the A / D converter 4 due to the delay time of the OR circuit 45b-1 and the AND circuit 45b-2 constituting the control signal adjustment circuit 45 can be reduced. Better images can be obtained.

  Note that the configuration of the control signal adjustment circuit 45 is not limited to the configuration shown in FIG.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  1 ... Pixel, 2 ... Pixel array, 3 ... Vertical scanning circuit, 4,201 ... A / D converter, 5 ... AD latch circuit, 6,105 ... Control signal output Circuit, 7 ... Horizontal scanning circuit, 40a, 101a ... Inverting circuit, 40b, 101b ... NAND circuit, 41, 102 ... RDL, 42, 103 ... Counter circuit, 43, 104 ...・ RDL latch circuit, 44 ・ ・ ・ Time A / D converter, 45 ・ ・ ・ Control signal adjustment circuit, 45a-1, 45b-1 ・ ・ ・ OR circuit, 45a-2, 45b-2 ・ ・ ・ AND circuit 45b-3 ... DU

Claims (8)

A pixel array in which a plurality of pixels having photoelectric conversion elements are two-dimensionally arranged;
A plurality of A / D converters arranged for each pixel column of the pixel array and converting pixel signals read from the pixel array into digital signals;
A control signal output circuit that outputs a start pulse, a count enable signal, and a latch signal for the plurality of A / D converters,
The A / D converter is
A plurality of delay units for transmitting a clock signal with a delay time corresponding to an analog signal during a period from a first state change to a second state change of the start pulse, and the clock at a frequency corresponding to the analog signal; An annular delay circuit for outputting a signal;
A counter that counts the number of state changes of the clock signal output from the annular delay circuit during a period from a first state change to a second state change of the count enable signal;
When the period from the first state change to the second state change of the latch signal overlaps at least one part with the period from the first state change to the second state change of the count enable signal, A latch circuit for storing the transmission position of the clock signal when the state changes in 2;
A time A / D conversion circuit for generating a digital signal from the output of the counter circuit and the output of the latch circuit;
Control signal adjustment for generating a correction latch signal and outputting the correction latch signal to the latch circuit as the latch signal so that the second state change of the latch signal is aligned with the second state change of the count enable signal Circuit,
A solid-state imaging device. The control signal output circuit outputs the count enable signal and the latch signal so that the second state change of the latch signal comes after the second state change of the count enable signal;
The solid-state imaging device according to claim 1, wherein the control signal adjustment circuit generates the correction latch signal using a logical product of the count enable signal and the latch signal.   The control signal adjustment circuit further generates a correction start pulse such that the first state change of the start pulse is aligned with the first state change of the count enable signal, and the correction start pulse is used as the start pulse. The solid-state imaging device according to claim 1, wherein the solid-state imaging device outputs to an annular delay circuit. The control signal output circuit outputs the count enable signal and the start pulse so that the first state change of the start pulse comes after the first state change of the count enable signal,
The solid-state imaging device according to claim 3, wherein the control signal adjustment circuit generates the correction start pulse by using a logical sum of the count enable signal and the latch signal.   The solid-state imaging device according to claim 2, wherein the control signal adjustment circuit further includes a circuit that delays the count enable signal.   The solid-state imaging device according to claim 4, wherein the control signal adjustment circuit further includes a circuit that delays the count enable signal.   2. The solid-state imaging device according to claim 1, wherein the time A / D conversion circuit is disposed between a pixel array and the control signal adjustment circuit.   2. The solid-state imaging device according to claim 1, wherein the start pulse is input to a delay unit disposed at a position closest to the control signal adjustment circuit among the plurality of delay units.

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