JP2010283022A - Silicon wafer and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure sufficient gettering capability even when a device is made thinner and to prevent injection atoms from affecting a device active layer and deteriorating device characteristics. <P>SOLUTION: A method of manufacturing a silicon wafer includes: an injection step; and an injection peak layer removal step of removing an injection peak layer from the surface of the wafer up to a peak layer including a peak position where the concentration of injection elements injected is at its peak in the direction of wafer thickness and containing 50-98% of the injection element. A gettering layer is formed which has the peak of the gettering capability corresponding to a depth position deeper than the peak position of the concentration of the injection element. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a silicon wafer and a method for manufacturing the same, and more particularly, to a technique suitable for use in a silicon wafer that improves gettering ability and is used for manufacturing a thin device.

  A thin semiconductor device made of silicon is manufactured by forming a circuit on a silicon wafer sliced from a silicon single crystal pulled by a CZ (Czochralski) method or the like. When heavy metal is mixed with impurities in the silicon wafer, the device characteristics are remarkably deteriorated.

  Factors causing heavy metal impurities in silicon wafers include, firstly, metal contamination in the manufacturing process of silicon wafers consisting of single crystal pulling, slicing, chamfering, and surface treatment such as polishing, grinding, and etching, and second, silicon There is heavy metal contamination in the device manufacturing process, which is a process of forming a circuit on a wafer, shaving the back surface of the wafer after circuit formation, and reducing the thickness to about 50 μm.

Conventionally, an IG (intrinsic gettering) method for forming oxygen precipitates on a silicon wafer and an EG (exotic tricktering) method for forming gettering sites such as backside damage on the back surface of the silicon wafer have been used. .
Patent Document 1 proposes a technique for performing IG processing.
Patent Document 2 describes an example of the EG method in 0005 and a technique related to carbon ion implantation.

JP-A-6-338507 JP 2006-313922 A

  As described above, silicon wafers used for device manufacture include an intrinsic gettering method in which oxygen precipitation heat treatment is performed before epitaxial growth to form oxygen precipitates, or an ion implantation method in which ions such as carbon ions are implanted into a silicon wafer. It is used.

    However, with the recent progress of thinning of devices, the thickness of silicon wafers as elements is required to be 50 μm to 40 μm or less and about 30 μm, and heavy metal contamination occurs most particularly in the thinning process of the final device manufacturing process. Therefore, in the case of the conventional IG (intrinsic gettering) method as described above, when the device is thinned to this extent, most of the IG layer exhibiting the IG effect is removed in the thinning step. Therefore, there has been a problem that a sufficient cause of the gettering ability is not exhibited and a cause of device failure is formed.

  Further, in the case of the conventional EG (exotic trick gettering) method as described above, the silicon wafer is likely to be cracked or chipped with the above-mentioned thinning, and this thinning process is performed by mechanical polishing or the like. Therefore, there is a problem that handling is deteriorated, workability is lowered, manufacturing time is increased, and device yield (yield) is lowered as a result. As described above, the deterioration of the yield generated in the final process is generated in the final stage with a great deal of process, time and cost, so it has the greatest impact on the device manufacturing efficiency, and there is a demand to prevent anything. was there.

In recent years, demands for MCP (Multi Chip Package), SiP (System in Package), etc. are increasing in order to cope with mobile devices that are becoming smaller in size. Due to the structure in which semiconductor chips are stacked, the thickness thereof is decreasing year by year, and is expected to be 10 μm or less and about several μm (1 to 10 μm) after 2010.
In the semiconductor chip thinned to this extent, there is a concern that the gettering capability is further insufficient with respect to the impurity metal introduced by contamination. For this reason, it is necessary to form a stronger gettering layer than in the prior art directly under the device active layer.

  As this means, when ion implantation is performed directly under the device active layer and the impurity metal is gettered into the implanted layer, the distance in the thickness direction between the implanted atom and the device region is closer, A problem has arisen that atoms implanted by a heat treatment in a device process or the like diffuse into the device active layer, which may adversely affect device characteristics.

  The present invention has been made in view of the above circumstances, and has sufficient gettering capability even when the device is thinned, and prevents the device characteristics from being deteriorated due to the influence of implanted atoms on the device active layer. An object of the present invention is to provide a silicon wafer and a method for manufacturing the same.

The method for producing a silicon wafer of the present invention includes an implantation step of implanting an implantation element into a silicon wafer with an acceleration energy of 50 keV to 800 keV at a peak concentration of 5 × 10 ¹⁹ cm ⁻³ or less,
Implantation peak layer removal which removes from the wafer surface to a peak layer containing a peak position where the concentration of the implanted element implanted in the implantation step includes a peak in the wafer thickness direction and containing 50% to 98% of the implanted element. Process,
The above problem has been solved by forming a gettering layer having a peak of gettering capability corresponding to a depth position deeper than the peak position of the implanted element concentration.
In the present invention, the implanted element may be one or more selected from C, B, O, N, As, P, Sb, Si, Ge, H, Ar, and He.
The present invention can have an outward diffusion heat treatment step having an outward diffusion heat treatment for outward diffusion of the remaining implanted elements after the implantation step of the present invention.
Moreover, in this invention, it can have the damage recovery heat processing process for recovering injection | pouring damage after the said injection | pouring process.
Moreover, an epitaxial process for forming an epitaxial layer on the wafer surface can be provided.
The present invention may include a second implantation step of implanting a second implantation element different from the implantation step so as to have a concentration peak at a second peak position deeper than the peak position.
Furthermore, it can have the bonding process which adheres another silicon wafer to the said wafer.
Further, the implantation peak layer removing step can be a grinding process, a polishing process, or an etching process.
The silicon wafer of the present invention can be a silicon wafer manufactured by any one of the manufacturing methods described above.

The method for producing a silicon wafer of the present invention includes an implantation step of implanting an implantation element into a silicon wafer with an acceleration energy of 50 keV to 800 keV at a peak concentration of 5 × 10 ¹⁹ cm ⁻³ or less,
Implantation peak layer removal which removes from the wafer surface to a peak layer containing a peak position where the concentration of the implanted element implanted in the implantation step includes a peak in the wafer thickness direction and containing 50% to 98% of the implanted element. Process,
And forming a defect layer to be a gettering layer having a peak of gettering ability corresponding to a depth position deeper than the peak position of the implanted element concentration by the occurrence of damage due to ion implantation. Even when such a gettering layer is formed in the vicinity of the lower side in the vicinity of the most effective device region by atomic implantation and thinned to about 10 μm, it is possible to have sufficient gettering ability, By removing most of the implanted elements contained in the peak layer so as to include the peak position, the implanted elements remaining on the wafer are reduced, and such implanted elements are diffused to the device region side by the heat treatment in the subsequent process. It is possible to reduce adverse effects on device characteristics.

  Here, the injection speed energy can be acceleration energy of 50 keV or more and 800 keV or less, 50 to 200 keV, or 200 to 400 keV. If the range is different from the above range, injection is performed at a predetermined depth position. This is not preferable. On the other hand, if the peak concentration is in a range different from the above range, an EOR defect layer having the necessary gettering ability cannot be formed, or implantation damage becomes too large.

In the present invention, the implanted element may be one or more selected from C, B, O, N, As, P, Sb, Si, Ge, H, Ar, and He, Other than that, ion implantation can be performed. By implanting these elements, it is possible to form a damaged defect layer generated by ion implantation to be a gettering layer.
The conditions for this implantation process vary depending on the type of implanted element, and it is preferable to set the acceleration energy and peak concentration for each element as follows.
C; 50 to 200 keV, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³
B; 50 to 200 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³
O: 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³
N: 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ^{−3
As; 50~200keV, 1 × 10 16} ~5 × 10 19 cm -3
P: 50 to 200 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³
Sb: 50 to 200 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³
Si; 50 to 200 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³
Ge; 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³
H; 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³
Ar; 50 to 200 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³
He; 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³

The present invention has an outer diffusion heat treatment step having an outer diffusion heat treatment for outward diffusion of the remaining implanted elements after the implantation step of the present invention, so that it remains without being removed in the implantation peak layer removal step. It is possible to reduce the amount of implanted elements by outward diffusion and reduce the possibility of adversely affecting device characteristics by reducing implanted elements that affect the device region in the device process.
The processing conditions in this outward diffusion heat treatment process vary depending on the type of implanted element, and for each element, the processing temperature, processing time, temperature increase / decrease rate, and processing atmosphere should be set as follows: Is preferred.
C: 800-1200 ° C., 10-120 min, temperature increase rate 0.1-0.2 ° C./second, temperature decrease rate 0.02-0.1 ° C./second, treatment atmosphere; N ₂ gas B; 800-1200 ° C. 10 to 120 min, temperature increase rate 0.1 to 0.2 ° C./second, temperature decrease rate 0.02 to 0.1 ° C./second, treatment atmosphere; N ₂ gas,
O: 800-1200 ° C., 10-120 min, temperature increase rate 0.1-0.2 ° C./second, temperature decrease rate 0.02-0.1 ° C./second, treatment atmosphere; N ₂ gas N; 800-1200 ° C. 10 to 120 min, temperature rising rate 0.1 to 0.2 ° C./s, temperature decreasing rate 0.02 to 0.1 ° C./s, treatment atmosphere; N ₂ gas As; 800 to 1200 ° C., 10 to 120 min, rising Temperature rate 0.1-0.2 ° C./second, temperature drop rate 0.02-0.1 ° C./second, treatment atmosphere; N ₂ gas P; 800-1200 ° C., 10-120 min, temperature increase rate 0.1 0.2 ° C./sec, temperature drop rate 0.02-0.1 ° C./sec, treatment atmosphere; N ₂ gas Sb; 800-1200 ° C., 10-120 min, temperature rise rate 0.1-0.2 ° C./sec , cooling rate 0.02 to 0.1 ° C. / sec, the treatment atmosphere; _{N 2} gas Si; 800 to 1200 ° C., 1 ～120Min, heating rate 0.1 to 0.2 ° C. / sec, cooling rate 0.02 to 0.1 ° C. / sec, the treatment atmosphere; _{N 2} gas Ge; 800~1200 ℃, 10~120min, heating rate 0.1 to 0.2 ° C./second, temperature decrease rate 0.02 to 0.1 ° C./second, treatment atmosphere; N ₂ gas H; 800 to 1200 ° C., 10 to 120 min, temperature increase rate 0.1 to 0. 2 ° C./second, temperature drop rate 0.02-0.1 ° C./second, treatment atmosphere; N ₂ gas Ar; 800-1200 ° C., 10-120 min, temperature rise rate 0.1-0.2 ° C./second, temperature drop Speed 0.02 to 0.1 ° C./second, treatment atmosphere; N ₂ gas He; 800 to 1200 ° C., 10 to 120 min, temperature increase rate 0.1 to 0.2 ° C./second, temperature decrease rate 0.02 to 0 .1 ° C./second, treatment atmosphere; N ₂ gas

Further, in the present invention, by having a damage recovery heat treatment step for recovering the implantation damage after the implantation step, the possibility of affecting the device region due to the implantation damage and adversely affecting the device characteristics is reduced. be able to.
The treatment conditions in this damage recovery heat treatment process vary depending on the type of implanted element, and for each element, the treatment temperature, treatment time, heating / cooling speed, and treatment atmosphere can be set as follows. preferable.
C: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
B; 500~1200 ℃, 0.1~60min, heating rate 0.1 to 20 ° C. / sec, cooling rate 0.02 to 10 ° C. / sec, the treatment atmosphere; _{N 2} gas,
O: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
N: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
As: 500 to 1200 ° C., 0.1 to 60 min, temperature rising rate 0.1 to 20 ° C./second, temperature decreasing rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
P: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
Sb: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
Si: 500 to 1200 ° C., 0.1 to 60 min, temperature rising rate 0.1 to 20 ° C./second, temperature decreasing rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
Ge: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
H: 500 to 1200 ° C., 0.1 to 60 min, temperature rising rate 0.1 to 20 ° C./second, temperature decreasing rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
Ar: 500 to 1200 ° C., 0.1 to 60 min, temperature increase rate 0.1 to 20 ° C./second, temperature decrease rate 0.02 to 10 ° C./second, treatment atmosphere; N ₂ gas,
He; 500~1200 ℃, 0.1~60min, heating rate 0.1 to 20 ° C. / sec, cooling rate 0.02 to 10 ° C. / sec, the treatment atmosphere; _{N 2} gas

In addition, by having an epitaxial process for forming an epitaxial layer on the wafer surface, an epitaxial layer that forms a good device region is formed on the wafer surface with reduced implanted elements to form a DZ layer. It is possible to provide a wafer with improved performance.
In this case, the thickness of the epitaxial layer can be appropriately set according to the removal amount in the implantation peak layer removal step, and the removal amount J of the implanted element is 0.5 to 0.98 of the total implantation amount. The product of the removal amount J and the film thickness T (μm) of the epitaxial layer added to the DZ layer is J · T ≧ 1.3.
It is preferable to set so as to satisfy.

In the present invention, there is provided a second injection step of injecting a second injection element different from the injection step so as to have a concentration peak at a second peak position deeper than the peak position. As another atom, effective for gettering of a specific impurity atom, for example, boron or the like is selectively implanted for an impurity copper atom, and the gettering ability for a specific impurity atom is enhanced. A silicon wafer having a second gettering layer can be manufactured.
Here, the second implantation element may be one or more selected from C, B, O, N, As, P, Sb, Si, Ge, H, Ar, and He, and C and B are ions. Implantation, otherwise, it can be atomic implantation. By implanting these elements, it is possible to form a damaged defect layer generated by ion implantation to be a gettering layer.
The implantation process conditions differ depending on the type of the second implanted element with respect to the first implanted element described above, and for each element, the second / first implanted element, the second implanted element acceleration energy, and the peak, respectively. The concentration, the first implanted element acceleration energy, and the peak concentration are preferably set as follows.
B / C; 100 to 400 keV, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³ , 50 to 200 keV, 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³

Furthermore, it can have the bonding process which adheres another silicon wafer to the said wafer, Specifically, it can carry out as follows.
FIG. 7 is a flow sheet showing the bonding process.
As described above, a single crystal silicon ingot pulled up by the CZ method is subjected to block cutting, notching and slicing to form a silicon wafer, and the resulting wafer is chamfered, lapped, polished, and mirrored Two finished silicon wafers 101 and 102 having notches n are prepared (FIG. 7A). Of these, an insulating silicon oxide film 101a is formed on the entire exposed surface of the active layer wafer 101 by thermal oxidation.
Next, using each notch n as an alignment guide, the active layer wafer 101 and the support substrate wafer 102 are superposed at room temperature to produce a bonded wafer 103. As a result, the buried oxide film 101b appears between the two wafers 101 and 102. Thereafter, a predetermined bonding heat treatment is performed on the bonded wafer 103 (FIG. 7B). Thereby, a silicon oxide film 103 a is formed on the entire exposed surface of the bonded wafer 103.
Next, the outer peripheral portion of the wafer 101 for active layer is ground in order to remove a bonding failure portion caused by the outer peripheral shape of both the chamfered wafers 101 and 102 (FIG. 7C). This peripheral grinding is stopped to the extent that it does not reach the bonding interface. As a result, a small amount of uncut portion 101 c appears on the outer peripheral portion of the active layer wafer 101.
Subsequently, the bonded wafer 103 comes into contact with an alkaline etching solution such as KOH, and the uncut portion 101c is melted (FIG. 7D). As a result, the outer peripheral portion of the buried oxide film 101b on the outer peripheral portion of the support substrate wafer 102 is exposed. This exposed area is called a terrace portion.
Next, the bonded SOI in which the thin SOI layer 101A is supported by the support substrate wafer 102 from the back surface side by subjecting the active layer wafer 101 to surface grinding and further surface polishing.
A substrate is produced (FIG. 7E).

Moreover, the said injection | pouring peak layer removal process can be made into a grinding process, a grinding | polishing process, or an etching process, and it is preferable to have a grinding | polishing process after a grinding process or an etching process.
The conditions for these steps can be as follows.
Grinding process: Grinding is performed at a rotational speed of 1000 rpm or less and a lowering speed (grinding speed) of 0.2 μm / second or less by a grinding apparatus employing a # 2000 or higher resinoid grinding wheel.
Etching process: Any of acid etching, alkali etching, or acid and alkali combined etching may be used. As the etching solution, for example, in the case of acid etching, an acidic etching solution such as a mixed acid of HF / HNO ₃ system can be employed. As an example, a solution containing hydrofluoric acid having a concentration of 1 to 10% and nitric acid having a concentration of 20 to 60% is treated at 70 to 90 ° C. for an appropriate time to remove the peak layer. In the case of alkaline etching, an alkaline etching solution such as KOH or NaOH can be employed. Furthermore, as a single wafer etching, only one surface, that is, only the front surface can be processed without processing the back surface.
Polishing process; The type of polishing cloth used in the polishing process may be, for example, a hard polishing cloth or a soft polishing cloth. In the case of a hard polishing cloth, for example, there are a hard foamed urethane foam pad, a pad in which a non-woven fabric is impregnated with a high concentration of urethane resin and cured. As the hard polishing cloth, for example, SUBA1200 (manufactured by Rodel Nitta Co., Ltd.) is available. The polishing apparatus includes a polishing platen having a polishing cloth spread on the upper surface, and a polishing head disposed above the polishing platen and having a semiconductor wafer wax-bonded on the lower surface. The apparatus may be a single wafer polishing apparatus for polishing semiconductor wafers one by one. Further, a batch type polishing apparatus that simultaneously polishes a plurality of semiconductor wafers may be used. For example, in the case of a single wafer type, the polishing platen is rotated at a high speed at 20 rpm or more. On the other hand, the polishing head is rotated at a predetermined rotation speed. While maintaining this state, the polishing liquid is supplied onto the polishing cloth at a predetermined flow rate, and the surface of the semiconductor wafer is pressed against the polishing cloth and polished.

  The silicon wafer of the present invention can be produced by any of the production methods described above.

  According to the present invention, since most of the implanted atoms can be removed by removing the layer where the concentration of implanted atoms reaches a peak, the implanted atoms do not affect the device characteristics, and gettering is performed. Can be performed in the damaged defect layer generated by the ion implantation remaining immediately under the concentration peak layer, so that it has sufficient gettering capability in response to wafer thinning in the device process and depends on the implanted element. The effect that influence can be reduced can be produced.

It is a flowchart which shows 1st Embodiment in the manufacturing method of the silicon wafer which concerns on this invention. It is process drawing which shows 1st Embodiment in the manufacturing method of the silicon wafer which concerns on this invention. It is a flowchart which shows 2nd Embodiment in the manufacturing method of the silicon wafer which concerns on this invention. It is process drawing which shows 2nd Embodiment in the manufacturing method of the silicon wafer which concerns on this invention. It is a graph which shows the Example of this invention. It is a graph which shows the Example of this invention. It is a figure which shows a bonding process.

Hereinafter, a first embodiment of a method for producing a silicon wafer according to the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing a method for manufacturing a silicon wafer according to the present embodiment. In the figure, FIG. 2 is a process diagram showing a method for manufacturing a silicon wafer according to the present embodiment. Symbol W0 is a silicon wafer. .

  In this embodiment, as shown in FIG. 1, wafer preparation step S0, ion implantation step S1, implantation peak layer removal step S2, damage recovery heat treatment step S3, outward diffusion heat treatment step S4, and epitaxial layer formation And a film process S5.

  In the wafer preparation step S0 shown in FIG. 1, a silicon wafer W0 is prepared as shown in FIG. The silicon wafer W0 was prepared by pulling up by a CZ (Czochralski) method or by performing various processes such as slicing, chamfering, lapping, etching, grinding, and polishing from a silicon single crystal obtained by the FZ method. It is supposed to be.

In the ion implantation step (implantation step) S1 shown in FIG. 1, as shown in FIG. 2B, the peak concentration of 5 × 10 ¹⁹ cm ⁻³ or less of an implantation element that is made into carbon at an acceleration energy of 50 keV to 800 keV is shown. The silicon wafer W1 on which the carbon implantation layer Wc to be implanted is formed. At the same time, a layer corresponding to the defect layer Wg0 is formed on the lower side (back side) of the carbon implantation layer Wc by this ion implantation. In this EOR defect layer Wg0, it is considered that interstitial atoms that are point defects or defects caused by the defects are generated by ion implantation.

In the implantation peak layer removal step S2 shown in FIG. 1, the concentration of carbon in the carbon implantation layer Wc implanted in the implantation step S1 is changed to the wafer thickness by grinding processing, polishing processing, or etching processing, as shown in FIG. A silicon wafer W2 is formed by removing from the wafer surface a peak layer Wp including a peak position Cp that is a peak in the vertical direction and containing 50% or more and 98% or less of carbon in the carbon injection layer Wc.
Specifically, a surface grinding process of about 0.1 to 2 μm can be performed.

In the damage recovery heat treatment step S3 shown in FIG.
In addition to recovering the implantation damage by performing a heat treatment in a nitrogen gas atmosphere at 1000 ° C. for 1 hour, in the outward diffusion heat treatment step S4 shown in FIG. 1, the treatment conditions are 1100 ° C., 60 to 120 minutes, treatment atmosphere; N _As shown in FIG. 2D, a silicon wafer W3 having a low carbon layer Wc2 reduced by outward diffusion of carbon that has not been removed in the implantation peak layer removal step S2 is obtained. .
In addition, it is also possible to perform the heat treatment with the treatment conditions of 1100 ° C., 60 to 120 min, treatment atmosphere; N ₂ gas, and simultaneously perform the damage recovery heat treatment step S3 and the outward diffusion heat treatment step S4.
At this time, also in the defect layer Wg0, fine precipitates are deposited by these heat treatments to form the gettering layer Wg1.

In the epitaxial layer film forming step S5 shown in FIG. 1, as shown in FIG. 2E, the epitaxial layer We is formed, and a portion to be a device region is formed as a formed DZ layer.
At this time, the epitaxial layer We can be formed with a thickness of 1 to 8 μm.
Thereby, the silicon wafer W4 in the present embodiment can be manufactured.

  Furthermore, as shown in FIG. 2F, the silicon wafer W4 in the present embodiment can be subjected to a device manufacturing process, and the back surface thereof can be thinned to about 10 μm by grinding or the like. Even in this case, by having the gettering layer Wg1, it is possible to have sufficient gettering ability.

Hereinafter, a second embodiment of a method for producing a silicon wafer according to the present invention will be described with reference to the drawings.
FIG. 3 is a flowchart showing a method for manufacturing a silicon wafer in the present embodiment. In the figure, the difference from the first embodiment described above in the present embodiment is a point related to the second implantation step, and corresponding components are shown in FIG. Are given the same reference numerals and their description is omitted.

The second ion implantation step (second implantation step) S12 shown in FIG. 3 is performed before the ion implantation step (first implantation step) S1 shown in FIG. 3, and as shown in FIG. 4, from the first implantation step. It is assumed that the silicon wafer W10 is formed with the boron implantation layer Wb in which an implantation element which is boron at a high acceleration energy of 100 keV to 800 keV is implanted at a peak concentration of 1 × 10 ¹⁹ cm ⁻³ or less. At the same time, by this second ion implantation, the boron implantation layer Wb is formed below the portion corresponding to the position to be the EOR defect layer Wg0.
In this boron implanted layer Wb, it is considered that defects caused by implanted boron exhibit a gettering ability for Cu in particular.

  As a result, it is possible to provide a silicon wafer in which the gettering capability for Cu is particularly improved and the diffusion of boron itself into the device region is reduced.

  In the present invention, a bonded wafer can be obtained as shown in FIG.

  Examples according to the present invention will be described below.

<Example 1>
A CZ wafer, which is a silicon wafer grown by the CZ method, is prepared. In this CZ wafer, the <100> plane is a mirror-polished surface (mirror surface), the resistivity is 1 to 10 Ωcm, and the oxygen concentration is 1.1 × 10 ¹⁸ atoms / cm ³ . Then, this CZ wafer is first washed with an NH ₄ OH / H ₂ O ₂ aqueous solution, and further with an HCl / H ₂ O ₂ aqueous solution.

Next, carbon is ion-implanted into the wafer from the mirror surface with an acceleration energy of 100 keV and a dose of 1 × 10 ¹⁵ atoms / cm ² .

Next, after annealing at 1000 ° C. for 1 hour in an N ₂ atmosphere, the SiO ₂ film is removed with an HF aqueous solution. Then, an Si epitaxial layer having a resistivity of about 20 to 30 Ωcm was grown on the mirror surface to a thickness of 6 μm at a temperature of about 1130 ° C. using SiHCl ₃ gas to obtain a silicon epitaxial wafer.

Thereafter, Ni contamination was forcibly performed at a concentration of 1 × 10 ¹³ atoms / cm ^{2 on} the obtained wafer surface, and drive-in was performed at 900 ° C. for 30 minutes.

  The concentration distribution of the carbon concentration, Ni concentration, and oxygen concentration in the depth direction from the wafer surface was measured by SIMS (Secondary Ion Mass Spectroscopy). The result is shown in FIG. From this result, it can be seen that a Ni peak exists at a position several hundreds of nanometers deeper than the C peak position, and defects generated by implantation, not carbon, are involved in gettering. FIG. 5 shows a TEM image of defects generated by implantation.

<Example 2>
An FZ wafer obtained by the FZ method was prepared, and the subsequent processing was performed in the same manner as in Example 1, and the concentration distribution of the carbon concentration, Ni concentration, and oxygen concentration in the depth direction from the wafer surface was measured. The result is shown in FIG. From this result, it can be seen that a Ni peak exists at a position several hundreds of nanometers deeper than the C peak position, and defects generated by implantation, not carbon, are involved in gettering.

W ... silicon wafer, Wg1 ... gettering layer

Claims (9)

An implantation step of implanting an implanted element at a peak concentration of 5 × 10 ¹⁹ cm ⁻³ or less at an acceleration energy of 50 keV to 800 keV in a silicon wafer;
Implantation peak layer removal which removes from the wafer surface to a peak layer containing a peak position where the concentration of the implanted element implanted in the implantation step includes a peak in the wafer thickness direction and containing 50% to 98% of the implanted element. Process,
And a gettering layer having a peak of gettering capability corresponding to a depth position deeper than the peak position of the implanted element concentration is formed.   2. The method for producing a silicon wafer according to claim 1, wherein the implanted element is one or more selected from C, B, O, N, As, P, Sb, Si, Ge, H, Ar, and He. .   3. The method for manufacturing a silicon wafer according to claim 1, further comprising an outward diffusion heat treatment step including an outward diffusion heat treatment for outwardly diffusing a remaining implanted element after the implantation step.   4. The method for manufacturing a silicon wafer according to claim 1, further comprising a damage recovery heat treatment step for recovering the injection damage after the injection step.   5. The method for producing a silicon wafer according to claim 1, further comprising an epitaxial step of forming an epitaxial layer on the wafer surface.   6. The method according to claim 1, further comprising a second implantation step of implanting a second implantation element different from the implantation step so as to have a concentration peak at a second peak position deeper than the peak position. Silicon wafer manufacturing method.   The method for producing a silicon wafer according to claim 1, further comprising a bonding step of attaching another silicon wafer to the wafer.   8. The method of manufacturing a silicon wafer according to claim 1, wherein the implantation peak layer removing step is a grinding process, a polishing process, or an etching process.   A silicon wafer manufactured by the manufacturing method according to claim 1.

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