JP2008205218A - Semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate for achieving a high yield in an LSI formed on a substrate by optimizing an uneven shape on the surface of the substrate in the semiconductor substrate having a DSB structure. <P>SOLUTION: On the semiconductor substrate, a first semiconductor wafer is bonded to a second semiconductor wafer having a coating thickness that is thinner than that of the first semiconductor wafer for formation so that an interface oxide film between the wafers becomes ≤1 nm. In this case, when only irregularities, which have a period of ≥100 nm and ≤10 μm on a surface at the side of the second semiconductor wafer, are extracted, an average height (Rc) of the extracted uneven shape should be ≥2 nm. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate, and more particularly to a semiconductor substrate formed by directly bonding two wafers.

  In the manufacture of current semiconductor products, a semiconductor wafer such as a silicon wafer whose surface has a single crystal plane orientation is generally used. In particular, in a large scale integrated circuit (LSI) composed of a metal oxide semiconductor field effect transistor (MOSFET), a silicon wafer having a crystal plane orientation of (100) is mainly used. It has become.

  In a silicon wafer, it is known that among the MOSFET carriers, electrons have a high mobility in the (100) crystal plane orientation and holes have a high mobility in the (110) crystal plane orientation. That is, the hole mobility in the (100) crystal plane orientation is 1/2 to 1/4 compared with the electron mobility. In order to compensate for this imbalance, the channel width of a pMOSFET having holes as carriers is usually designed to be wider than that of an nMOSFET having electrons as carriers. This design maintains a balance between the driving currents of the nMOSFET and the pMOSFET and ensures uniform circuit operation. However, there is another problem that the chip area of the LSI increases due to the wide pMOSFET.

  On the other hand, the hole mobility in the (110) crystal plane orientation is about twice that of the (100) crystal plane orientation. Therefore, the pMOSFET formed on the (110) plane shows a higher driving current than the pMOSFET formed on the (100) plane. However, unfortunately, the electron mobility in the (110) crystal plane orientation is greatly deteriorated compared to the (100) crystal plane orientation, so that the driving capability of the nMOSFET is deteriorated.

  Thus, a silicon wafer having a (110) crystal plane orientation on the surface is suitable for pMOSFET because of its excellent hole mobility, but is not suitable for nMOSFET because of its poor electron mobility. Conversely, a silicon wafer whose surface has a (100) crystal plane orientation is optimal for nMOSFET because of its excellent electron mobility, but is not suitable for pMOSFET because of its poor hole mobility.

Therefore, various techniques for creating regions having different crystal plane orientations on the silicon wafer surface by direct bonding (bonding) of two silicon wafers, and creating nMOSFETs and pMOSFETs on optimal crystal plane orientations, respectively. Has been proposed. That is, for example, by creating (100) and (110) plane regions on the surface of a silicon wafer, forming an nMOSFET on the (100) plane and a pMOSFET on the (110) plane, high performance and high integration A technology that enables realization of an integrated LSI has been proposed.
As one of the technologies, silicon wafers having different crystal plane orientations on the surface are directly joined together, and then the upper silicon single crystal layer is made amorphous to the joining interface with the lower layer by ion implantation of silicon or the like, and the lower layer is annealed. A method of creating regions having different crystal plane orientations on the surface of a silicon wafer by recrystallization based on the crystal orientation information (ATR method: Amorphization / Templated Recrystallization method) is disclosed in, for example, Patent Document 1 Has been.
Note that, as described above, a structure in which two silicon wafers are directly bonded without a thick oxide film is called a DSB structure (Direct Silicon Bonding structure).

When a semiconductor substrate having a DSB structure is formed by joining two wafers as described above, one of the substrates needs to be thinned.
As a method for thinning, there is a method in which two wafers are bonded and then one of them is mechanically ground and mechanically polished to be thinned. However, in this method, since a thick wafer is thinned by mechanical grinding and mechanical polishing, there arises a problem that the film thickness uniformity of the upper semiconductor layer is deteriorated.

Thus, several methods for improving the film thickness uniformity of the upper semiconductor layer have been considered.
For example, a so-called Smart Cut method (for example, Patent Document 2), Nano Cleave method (for example, Patent Document 3) or ELTRAN method developed as a method for manufacturing an SOI (Silicon On Insulator) substrate. (For example, patent document 4) is a method of applying to a DSB structure.
These methods are methods in which a boundary layer such as a microbubble layer or a porous layer is provided in advance on one wafer, and division (cleaving) is performed at the boundary layer after joining the two wafers. Therefore, it is not necessary to thin a thick wafer by mechanical grinding and mechanical polishing, so that the film thickness uniformity of the upper semiconductor layer is improved.
However, since the wafer surface after cleaving is too rough from the viewpoint of device formation, mechanical polishing or wet etching or the like for surface flattening is necessary. By this flattening treatment, the surface of the upper semiconductor layer is flattened. Has been realized.

However, it has been difficult to completely suppress a decrease in film thickness uniformity due to the presence of a mechanical polishing or wet etching process. Therefore, as a method for manufacturing an SOI substrate, as a planarization process after division (cleaving), a method of planarizing the wafer surface only by heat treatment instead of mechanical polishing or wet etching has been proposed (Patent Literature). 5).
US 7,060,585 B1 Japanese Patent Application Laid-Open No. 2000-124092 JP 2001-525991 A JP-A-5-217821 Japanese Patent Laid-Open No. 11-307472

As described above, it is a semiconductor substrate having a DSB structure formed by various methods. However, a conventional semiconductor substrate has a surface shape necessary for forming an LSI on a semiconductor substrate with a high yield. There wasn't.
That is, by providing the divided polishing step, the manufactured semiconductor substrate has no irregularities with a period of about 100 nm to 10 μm on the wafer surface, and longer period irregularities are dominant. For this reason, in the subsequent flattening heat treatment, when a step structure in which the flat surface is a crystal plane is formed, uneven distribution in the surface of the step occurs. Therefore, when a plurality of LSIs having the same pattern are formed on a semiconductor substrate, there is a problem in that individual LSI characteristics vary and yield decreases.
Further, when a method that does not provide a polishing step after the division is adopted for the DSB structure, the surface shape of the heat treatment for flattening is not sufficiently controlled, and thus the optimum uneven shape has not been obtained. Therefore, for example, the unevenness is too large, and there is a concern that the yield may be reduced due to the occurrence of defocusing when patterning the LSI using lithography.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to optimize the shape of an LSI formed on a substrate by optimizing the uneven shape of the substrate surface in a semiconductor substrate having a DSB structure. It is an object of the present invention to provide a semiconductor substrate that makes it possible to achieve a yield.

The semiconductor substrate of one embodiment of the present invention includes:
The first semiconductor wafer and the second semiconductor wafer having a smaller film thickness than the first semiconductor wafer have an interface oxide film of 1 nm or less between the first semiconductor wafer and the second semiconductor wafer. A semiconductor substrate formed by bonding so that
When only irregularities having a period of 100 nm or more and 10 μm or less on the surface of the second semiconductor wafer side are extracted, the average height (Rc) of the extracted irregularities is 2 nm or more.

  Here, it is desirable that the period is 500 nm or more and 10 μm or less.

  The average height (Rc) is preferably 2 nm or more and 5 nm or less.

  Further, the first semiconductor wafer and the second semiconductor wafer are silicon wafers, and one of a crystal plane orientation on the surface of the first semiconductor wafer and a crystal plane orientation on the surface of the second semiconductor wafer. One is in a range having an inclination angle (off angle) of 0 degree or more and 5 degrees or less with respect to the {100} plane, and the other crystal plane orientation is an inclination of 0 degree or more and 5 degrees or less with respect to the {110} plane It is desirable to be in a range having an angle (off angle).

  The inclination angle (off angle) of the second semiconductor wafer surface with respect to the {100} plane is not less than 0 degrees and not more than 0.1 degrees, and the inclination of the second semiconductor wafer surface with respect to the {100} plane is The azimuth angle on the {100} plane of the direction is preferably within a range of ± 21 degrees with respect to the <110> direction.

  In addition, an inclination angle (off angle) of the second semiconductor wafer surface with respect to the {110} plane is 0 degree or more and 0.2 degrees or less, or an inclination of the second semiconductor wafer surface with respect to the {110} plane. It is desirable that the azimuth angle on the {110} plane of the direction is in a range of ± 26 degrees with respect to the <100> direction.

  It is desirable that the azimuth angle on the {110} plane of the second semiconductor wafer surface with respect to the {110} plane is in a range of ± 2 degrees with respect to the <100> direction.

  According to the present invention, it is possible to provide a semiconductor substrate capable of achieving a high yield of LSI formed on the substrate by optimizing the uneven shape of the substrate surface in the semiconductor substrate having a DSB structure. It becomes possible.

Embodiments of a semiconductor substrate according to the present invention will be described below with reference to the accompanying drawings.
In the embodiment, a case where a silicon wafer is used as a semiconductor wafer will be described as an example. However, the present invention is not necessarily limited to a method for manufacturing a semiconductor substrate using a silicon wafer.
In the present specification, the notation {100} plane and {110} plane are used as notations representative of planes crystallographically equivalent to the (100) plane and the (110) plane, respectively. Then, as notations representing the crystallographically equivalent directions of the [100] direction and the [110] direction, the notations of <100> direction and <110> direction are used, respectively.

[First Embodiment]
The semiconductor substrate according to the first embodiment of the present invention has a first silicon wafer and a second silicon wafer having a thickness smaller than that of the first silicon wafer, and an interfacial oxide film between the wafers is 1 nm or less. The crystal plane orientation of the first silicon wafer surface has an inclination angle (off angle) of 0 degree or more and 5 degrees or less with respect to the {100} plane. The crystal plane orientation of the second silicon wafer surface has an inclination angle (off angle) of 0 degree to 5 degrees with respect to the {110} plane, and the second silicon wafer side surface When the measurement region is an arbitrary portion of the above, when only the unevenness having a period of 100 nm or more and 10 μm or less in the measurement region is extracted, the average height (Rc) of the extracted uneven shape is 2 nm or more. Semiconductor It is a substrate.

  Here, the interfacial oxide film between the wafers is 1 nm or less. If the oxide film is thicker than this range, a crystal plane having a different plane orientation is formed on the surface of the semiconductor substrate by the ATR method in a later LSI manufacturing process. This is because it is desirable to form a crystal plane in which crystal defects are suppressed.

FIG. 1 is a conceptual cross-sectional view illustrating the semiconductor substrate of this embodiment. As shown in the figure, a base wafer (first silicon wafer) 102 and a bond wafer (second silicon wafer) 104 are directly bonded to each other at an interface 116 having a silicon oxide film of 1 nm or less, which is not desirable at all. The crystal plane orientation of the surface of the base wafer 102 has an inclination angle (off angle) of 0 degree to 5 degrees with respect to the {100} plane, for example, an inclination angle of 1 degree. The plane orientation has an inclination angle (off angle) of 0 degree or more and 5 degrees or less with respect to the {110} plane, for example, an inclination angle of 0.2 degree.
Further, when an arbitrary portion of the surface of the semiconductor substrate on the bond wafer 104 side is used as a measurement region, except for irregularities with a period of less than 100 nm and irregularities with a period of more than 10 μm as shown in an enlarged view surrounded by a circle, When only irregularities with a period of 100 nm to 10 μm in the measurement region are extracted, the average height (Rc) is 2 nm or more.

Here, by extracting only irregularities having a desired period, here, a period of 100 nm or more and 10 μm or less, it is possible to derive an irregular shape consisting of only this period, for example, measurement with an AFM (Atomic Force Microscope). This is possible by filtering the data. More specifically, for example, a desired frequency is extracted from a spectrum obtained by Fourier transform (FET) of measurement data by a band-pass filter and is inversely converted (iFET).
In this case, in order to effectively extract the irregularities of the period, it is desirable to measure and evaluate a region of 30 μm × 30 μm or more at an interval of 100 nm or less in the AFM.
Moreover, in this specification, as shown in (Formula 1) of FIG. 1, the average height (Rc) is a contour curve element (one mountain and an adjacent valley or vice versa) in the measurement region. It is an average value of the height difference hi. In (Expression 1), m represents the number of contour curve elements in the measurement region.

According to the semiconductor substrate of the present embodiment, it is possible to achieve high performance of LSI nMOSFETs and pMOSFETs formed on the substrate and to achieve high yield of LSIs.
That is, by having irregularities with a period of 100 nm to 10 μm and an average height (Rc) of 2 nm or more, minute irregularities formed on the surface of the semiconductor substrate during heat treatment for surface reconstruction performed at the time of LSI formation The surface distribution of these is averaged and made uniform, and variation in the characteristics of LSIs formed in large numbers in the surface is suppressed, so that high yield of LSIs can be realized.

  Among the functions and effects of the semiconductor substrate of the present embodiment as described above, the surface distribution of minute irregularities (step structure) when heat treatment for surface reconstruction is performed is compared with the case of the prior art. explain. When heat treatment is performed on a silicon wafer at a high temperature, for example, about 1200 ° C. for about 1 hour in a non-oxidizing atmosphere such as a reducing or inert atmosphere, the silicon atoms on the surface are reconfigured and the flat surface becomes It is conventionally known that a step structure which is a crystal plane is formed. According to such a step structure in which the flat surface is a crystal surface, for example, the flatness of the gate oxide film and silicon interface used in transistors and capacitors is improved, so that the mobility of the transistor is improved and the gate insulating film is improved. Leakage current suppression is realized. For this reason, during the process of forming an LSI, for example, by applying a planarization heat treatment before forming a gate oxide film used for a transistor or a capacitor, the unevenness generated on the wafer surface in the previous process is eliminated, and silicon It is conceivable to adopt a process of forming a step structure in which the flat surface is a crystal plane by the reconstruction of atoms.

FIG. 2 is a diagram comparing the effects when surface planarization heat treatment is applied to the semiconductor substrate of the present embodiment and the semiconductor substrate of the prior art. FIG. 2A shows a surface structure when the semiconductor substrate of this embodiment is subjected to a heat treatment performed for surface flattening at the time of LSI formation. In the semiconductor substrate of this embodiment, since the surface has irregularities with a period of 100 nm to 10 μm and an average height (Rc) of 2 nm or more, it is representatively shown in an enlarged view of positions separated on two wafers. As described above, the distribution of the step structure in which the flat surface is the crystal surface is averaged and uniformized. For example, if there are many steps crossing the gate insulating film of one transistor, the carrier mobility is lowered due to the steps. Therefore, if the distribution of the step structure is averaged and made uniform, variation in the characteristics of the LSI is suppressed, and a high yield of the LSI can be realized.
On the other hand, FIG. 2B shows a surface structure in the case where a heat treatment performed for surface flattening is applied to a semiconductor substrate having a relatively long average period of unevenness in LSI formation at the time of LSI formation. . In this case, unlike the case of the present embodiment, as shown by two enlarged views, a flat surface is formed such that a large number of steps are generated at a certain place and no step is generated at a certain place. The variation in the distribution of the step structure which is a surface becomes large. Therefore, the characteristic variation of the LSI becomes large, and the yield of the LSI is reduced.

In this embodiment, the reason why the range of 100 nm or more and 10 μm or less of the period is extracted and the average height (Rc) is numerically limited to the unevenness of 2 nm or more is that when the period is less than this range, the flat surface is a crystal plane. This is because the flat surface width and the unevenness period of the step structure are substantially equal to each other or the period becomes larger, so that it is difficult to expect the effect of improving the distribution of the step structure. Further, if the period exceeds this range, the variation in the distribution of the step structure in which the flat surface is the crystal plane becomes large as in the conventional technique, and the yield is significantly reduced.
If the average height falls below this range, the difference in the distribution of the step structure whose flat surface is the crystal plane becomes large, and the yield is significantly reduced.

  Here, it is more desirable that the average height (Rc) is 2 nm or more when only the irregularities with a period of 500 nm or more and 10 μm or less are extracted. This is because, for example, when a silicon wafer having the (100) plane as the surface is annealed, a wide flat surface can be formed, and the width can be about 50 nm to 300 nm. Therefore, in such a case, if the period is not 500 nm or more, the flat surface width and the period of the step structure whose flat surface is a crystal plane are almost equal or the period becomes larger. This is because it cannot be expected.

  The average height is desirably 2 nm or more and 5 nm or less. If this range is exceeded, the number of flat surfaces (number of steps) in one cycle becomes large, the number of steps crossing one element of the LSI becomes too large, and the device yield may be deteriorated. If the average height exceeds this range, it will be difficult to ensure a sufficient margin for the depth of focus when patterning the LSI using lithography. Therefore, the yield reduction due to defocusing becomes significant.

  In the present embodiment, the inclination angle (off angle) of the first and second silicon wafers is set to 0 degree or more and 5 degrees or less. In order to stably form a step structure having a flat surface as a crystal plane, it is desirable that the tilt angle is in the above range, but the present invention does not exclude a range exceeding the tilt angle.

  Hereinafter, an embodiment of a first manufacturing method of a semiconductor substrate according to the present embodiment will be described with reference to the accompanying drawings.

  The first manufacturing method of the semiconductor substrate of the present embodiment includes a first silicon wafer having a tilt angle (off angle) of 0 degrees or more and 5 degrees or less with respect to the (100) plane of the surface crystal plane orientation; A step of preparing a second silicon wafer having an inclination angle (off angle) of 0 ° or more and 5 ° or less with respect to the (110) plane, the first silicon wafer and the second silicon wafer And a step of bonding the silicon wafer to an interfacial oxide film of 10 nm or less, and the second silicon wafer bonded to the first silicon wafer has a thickness of 300 nm or less and is divided. The second silicon wafer is divided so that RMS (Root Mean Square) of the surface roughness of the second silicon wafer later becomes 3.5 nm or more and 6.5 nm or less. A step of forming a silicon substrate in which a part of the first silicon wafer and a part of the second silicon wafer (silicon upper layer) are bonded; and the silicon substrate in which the wafer surface roughness after the division is maintained A method for producing a silicon substrate, comprising a step of heat treatment in a temperature of 1100 ° C. or higher and 1350 ° C. or lower, a reducing gas, an inert gas, or a mixed gas atmosphere of a reducing gas and an inert gas. Is a method of manufacturing a silicon substrate using a so-called smart cut method (hydrogen ion implantation separation method).

  In this manufacturing method, the semiconductor substrate of this embodiment can be manufactured by limiting the thickness of the interfacial oxide film, the thickness of the second silicon wafer after the division, and the surface roughness of the second silicon wafer. It becomes possible.

  Hereinafter, this manufacturing method will be described more specifically with reference to the manufacturing process flow chart of FIG.

  First, in the step shown in FIG. 3A, for example, a silicon single crystal ingot with a crystal orientation (100) pulled up by the Czochralski method (CZ method) is applied to a predetermined angle, for example, the (100) plane. A silicon wafer is formed by slicing to have an inclination angle (off angle) of 0 degree or more and 5 degrees or less, for example, about 2 degrees. Subsequently, the silicon wafer is subjected to mirror polishing after cleaning with, for example, hydrogen fluoride-nitric acid. By doing so, a base wafer (first semiconductor wafer) 102 whose surface has a predetermined inclination angle (off angle) with respect to the (100) plane is prepared.

  Next, again, in the step shown in FIG. 3A, for example, a silicon single crystal ingot with a crystal orientation (110) pulled by the Czochralski method (CZ method) is applied to a predetermined angle, for example, the (110) plane. The silicon wafer is sliced so as to have an inclination angle (off angle) of 0 degrees or more and 5 degrees or less, for example, about 2 degrees. Subsequently, the silicon wafer is subjected to mirror polishing after cleaning with, for example, hydrogen fluoride-nitric acid. By doing so, a bond wafer (second semiconductor wafer) 104 whose surface has a predetermined inclination angle (off angle) with respect to the (110) plane is prepared.

  Here, heat treatment may be performed on both or one of the first and second silicon wafers using a heat treatment apparatus such as a batch type vertical heat treatment furnace or a single wafer RTP (Rapid Thermal Processing) apparatus. This heat treatment is preferably performed at a temperature of 1025 ° C. to 1250 ° C., a time of 30 seconds to 2 hours, in a reducing gas, an inert gas, or a mixed gas atmosphere of a reducing gas and an inert gas. . This is because the surface of each or one of the silicon wafers is flattened by this heat treatment, and the flatness of the bonding interface between the two wafers is improved. For this reason, the generation of crystal defects at the interface after bonding is suppressed, and the crystal plane orientation different from that of the manufactured silicon substrate due to amorphization by ion implantation and recrystallization by annealing (ATR method). This is because the generation of crystal defects due to crystal defects at the bonding interface can be suppressed in the case of creating a region having a defect.

  In addition, the inclination angle with respect to the (100) plane and the (110) plane is set to 0 degree or more and 5 degrees or less, and if it exceeds this range, the effect of increasing the carrier mobility can be sufficiently obtained for each of the nMOSFET and pMOSFET. This is because it may disappear. Also, if this range is exceeded, it becomes difficult to form a step structure in which the flat surface of the wafer surface becomes a crystal surface when the above-described flattening heat treatment before bonding is added, so that the flatness of the wafer surface deteriorates. This is because a sufficient crystal defect suppressing effect may not be exhibited.

Next, in the process shown in FIG. 3B, hydrogen ions or rare gas ions, here, hydrogen ions are implanted to about 3E16 to 1E17 atoms / cm ^{2 on} one side of the bond wafer 104, and the average ion penetration depth is obtained. Then, a microbubble layer (encapsulation layer) 106 parallel to the wafer surface is formed.

Next, in the step shown in FIG. 3C, the hydrogen ion-implanted surface of the bond wafer 104 into which hydrogen ions have been implanted and the base wafer 102 are brought into close contact with each other. Before the adhesion, a cleaning process such as RCA cleaning is performed to remove deposits and the like on the wafer surface, and a natural oxide film (silicon oxide film) having a thickness of about 1 to 2 nm is grown on each surface. In this step, the silicon wafers can be bonded without using an adhesive or the like by bringing the surfaces of the two wafers into contact with each other in a clean atmosphere at room temperature. However, when there is no fixed silicon oxide film at the interface, bonding is difficult.
In this step, the thickness of the interfacial oxide film 108 is set to 10 nm or less. The film thickness adjustment of the interface oxide film 108 is performed by forming a natural oxide film by a cleaning process before bonding, removing the formed natural oxide film with diluted hydrofluoric acid (HF), or the like. For example, after removing the natural oxide film with dilute hydrofluoric acid (HF), the wafer left in the air can be bonded within about 3 hours to make the thickness 10 nm or less. Here, the reason why the thickness of the interface oxide film 108 is set to 10 nm or less is that when the thickness is larger than this, it is very difficult to remove the interface oxide film by a subsequent heat treatment.

  Next, in the step shown in FIG. 3D, the separation wafer 110 and the silicon substrate 114 are separated with the microbubble layer (encapsulation layer) 106 as a boundary. The silicon substrate 114 is a substrate in which a silicon substrate upper layer 112 that is a part of the bond wafer 104 and the base wafer 102 are bonded. In this step, for example, a heat treatment is performed at a temperature of about 500 ° C. or higher in an inert gas atmosphere, thereby rearranging silicon atoms and aggregating hydrogen bubbles to form the separation wafer 110 and the silicon substrate 114. Divided.

In this manufacturing method, the film thickness of the silicon substrate upper layer 112 which is a part after the bond wafer 104 is divided is controlled to be 300 nm or less. This control is made possible by controlling the acceleration energy of the implanted hydrogen ions in the step of FIG.
Thus, the film thickness is set to 300 nm or less because if it exceeds this range, it becomes difficult to completely remove the interface oxide film 108 by the subsequent planarization / interface oxide film removal heat treatment.

Then, the surface roughness of the silicon substrate upper layer 112 on the surface of the silicon substrate 114, that is, the surface roughness that remains during the division, remains. In the present embodiment, the surface roughness is controlled so that the RMS (Root Mean Square) is 3.5 nm or more and 6.5 nm or less. For example, the control may be performed by implanting ion species or ion implantation amount when forming the microbubble layer (encapsulation layer) 106 in the process of FIG. 1B, or the heat treatment temperature of the process of FIG. This is possible by controlling the heat treatment profile and the like.
In addition, RMS is a parameter | index of surface roughness here, and is a value represented by the square root of the value which averaged the square of the deviation from an average line to a measurement curve. The RMS of the roughness of the surface of the silicon wafer can be easily measured by using, for example, an AFM.
Note that the RMS on the wafer surface in this specification refers to a value measured by AFM for an arbitrary region of about 3 to 30 μm on the wafer surface.
As described above, the RMS of the surface roughness is limited to 3.5 nm or more and 6.5 nm or less because if the surface irregularities are larger than this range, it becomes difficult to planarize the silicon substrate surface. This is because if the surface irregularities are smaller than this range, it becomes difficult to remove the interfacial oxide film.

  Next, in the step of FIG. 3E, the surface roughness of the surface of the silicon substrate upper layer 112 of the divided silicon substrate (wafer) 114 of FIG. 3D is maintained, that is, surface polishing or the like. The silicon substrate 114 is heated to a temperature of 1100 ° C. or higher and 1350 ° C. or lower, a reducing gas, an inert gas, or a mixed gas of a reducing gas and an inert gas in a state where the wafer surface is not actively planarized. Heat treatment in an atmosphere. This heat treatment is a heat treatment for performing the planarization of the surface of the silicon substrate 114 and the removal of the interface oxide film 108 at once. This heat treatment is performed using, for example, a vertical heat treatment furnace by heater heating.

By this planarization / interfacial oxide film removal heat treatment, as shown in FIG. 3F, the silicon substrate upper layer 112 having a crystal orientation (110) whose surface is planarized and the base wafer 102 having a crystal orientation (100) are formed. A silicon substrate 114 bonded at the interface 116 without a silicon oxide film is formed.
The silicon substrate has an average height (Rc) of 2 nm or more when extracting only irregularities having a period of 100 nm or more and 10 μm or less in the measurement region when an arbitrary portion on the silicon wafer side surface is a measurement region. It is the biggest feature.
In this manufacturing method, the planarization / interfacial oxide film removal heat treatment also serves as a bonding heat treatment between the base wafer 102 and the silicon substrate upper layer 112. From the viewpoint of simplifying the manufacturing process of the silicon substrate 114, it is desirable to also serve as a bonding heat treatment as in the present embodiment, but it is also possible to perform the bonding heat treatment separately before the planarization / interfacial oxide film removal heat treatment. The semiconductor substrate of this embodiment can be manufactured.

  As described above, according to this manufacturing method, when a silicon substrate having a DSB structure is manufactured by joining two wafers, the surface uniformity of the silicon substrate that maintains high film thickness uniformity of the upper silicon layer, The silicon oxide film at the wafer interface can be removed by the same heat treatment, and the performance of LSI nMOSFETs and pMOSFETs formed on the substrate is improved, and high LSI yields are achieved. It is possible to manufacture a silicon substrate that makes it possible to do this.

  In such a manufacturing method, it is possible to perform planarization of the silicon substrate surface with high uniformity of the thickness of the upper silicon layer and removal of the silicon oxide film at the interface between the two wafers by the same heat treatment. The reason why the action / effect is obtained and details of the action / effect are described below.

  First, in the planarization / interfacial oxide film removal heat treatment, the unevenness remaining after the wafer division is flattened, as is conventionally known, because the silicon atoms on the wafer surface are reconstructed by thermal energy. This is because a flat surface having a smaller surface energy is formed. However, in an oxidizing atmosphere, since the wafer surface is oxidized and the reconstruction of silicon atoms is hindered, the heat treatment is performed by a reducing gas, an inert gas, or a mixed gas of a reducing gas and an inert gas. Must be done in an atmosphere.

In addition, in the planarization / interfacial oxide film removal heat treatment, the silicon oxide film at the interface is removed because oxygen in the silicon oxide film diffuses in the silicon substrate upper layer 112 and the atmosphere from the surface of the silicon substrate upper layer 112. By diffusing outwards.
FIG. 2 shows the result of calculating the relationship between the film thickness of the upper layer of the semiconductor (silicon) substrate and the reduced thickness of the interface oxide film (silicon oxide film) by the heat treatment using temperature as a parameter.
The calculation was performed based on Fick's first law described below.

J = −D (σC / σX)
= D (Cs-0) / t
J: Oxygen flow rate D: Diffusion coefficient C: Impurity concentration Cs: Oxygen solid solution limit t: Semiconductor substrate upper layer film thickness

In the calculation here, σC / σX = Cs−0 is based on the assumption that the oxygen concentration of the oxide film and the silicon oxide film is the solid solution limit and the oxygen concentration of the silicon surface is 0. Note that the heat treatment time was fixed at 60 minutes in order to obtain the reduction amount of the interfacial oxide film. As is apparent from FIG. 1, since the effect of removing the interfacial oxide film is very small at a temperature lower than 1100 ° C., the heat treatment temperature needs to be 1100 ° C. or higher. In particular, since the effect of removing the interfacial oxide film becomes remarkable at 1200 ° C. or higher, the heat treatment temperature is desirably 1200 ° C. or higher.
Moreover, the heat treatment temperature needs to be 1350 ° C. or lower and is preferably 1300 ° C. or lower from the viewpoint of reducing furnace material deterioration due to high temperature heat treatment and metal contamination on the processed wafer.

  As can be seen from FIG. 4, when the upper layer thickness of the semiconductor substrate is greater than 300 nm, the effect of removing the interfacial oxide film is extremely reduced particularly near 1100 ° C., so that the interfacial oxide film can be removed efficiently. For this, the thickness of the upper layer of the semiconductor substrate needs to be 300 nm or less.

FIG. 5 shows the results of experiments conducted on the heat treatment temperature for planarization and removal of the interface oxide film and the reduced thickness of the interface oxide film by the heat treatment using the thickness of the upper layer of the semiconductor substrate as a parameter. As derived from the above calculation results, it is necessary that the heat treatment temperature is 1100 ° C. or more and the thickness of the upper layer of the semiconductor substrate is 300 nm or less. Particularly, the effect of removing the interfacial oxide film is remarkable at 1200 ° C. or more. For this reason, it has become clear from experiments that the heat treatment temperature is desirably 1200 ° C. or higher.
In this experiment, the RMS before heat treatment is 0.3 nm or less, and the heat treatment time is 60 minutes.

Note that in the case of heat treatment for planarizing the surface of the SOI substrate, heat treatment under a condition in which the buried oxide film (BOX) is removed is not preferable because the interface quality between the SOI layer and the buried oxide film layer is deteriorated. Therefore, heat treatment in a high-temperature reducing gas, inert gas, or mixed gas atmosphere of reducing gas and inert gas to realize planarization is minimized from the viewpoint of manufacturing an SOI substrate. It is desirable to stay. For this reason, it is common to add a step of actively flattening the wafer surface, such as polishing or etching, once after the wafer is divided and before the flattening heat treatment.
On the other hand, in this manufacturing method, unlike the SOI substrate, planarization and removal of the interfacial oxide film are performed by the same heat treatment in the manufacture of a silicon substrate having a DSB structure that requires the removal of the interfacial oxide film. One feature is that the process is simplified by focusing on the above.

  Furthermore, in this manufacturing method, by limiting the RMS (Root Mean Square) of the surface roughness of the bond wafer (second semiconductor wafer) after the division to 3.5 nm or more and 6.5 nm or less, The wafer surface is planarized and the interface oxide film is removed efficiently by the same heat treatment.

FIG. 6 shows the results of an experimental investigation of the relationship between the heat treatment temperature of the planarization / interfacial oxide film removal heat treatment and the surface roughness (flatness) after the heat treatment using the surface roughness (RMS) before the heat treatment as a parameter. Show. The heat treatment is performed for 60 minutes in an argon atmosphere.
As apparent from FIG. 6, if the RMS is 6.5 nm or less before the heat treatment, by performing the heat treatment at 1100 ° C., the RMS is 4 nm or less after the heat treatment, and further by performing the heat treatment at 1200 ° C. An interface state with extremely high flatness with an RMS of 1 nm or less after heat treatment can be realized.

FIG. 7 shows the relationship between the silicon substrate surface roughness before the heat treatment and the reduced thickness of the interfacial oxide film by the heat treatment. The heat treatment is performed for 60 minutes in an argon atmosphere.
As is apparent from the figure, the thinner the surface roughness before heat treatment, the larger the reduction thickness of the interfacial oxide film. This is presumably because the surface area of the wafer increases due to the rough surface of the silicon substrate, and oxygen from the interfacial oxide film efficiently diffuses out into the atmosphere. Therefore, from FIG. 5, it is necessary for effective removal of the oxide film that the effect of increasing the outward diffusion starts to be noticeable, and that it has a surface roughness of 3.5 nm or more in RMS before the heat treatment. is there.

As described above, the RMS (Root Mean Square) of the surface roughness of the bond wafer (second semiconductor wafer) before the planarization / oxide film removal heat treatment, that is, after the division, is planarized on the wafer surface and interface oxidation. From the viewpoint of efficiently realizing film removal, it is necessary to limit the film thickness to 3.5 nm or more and 6.5 nm or less.
As described above, the surface roughness in the above range can be realized by, for example, implanting ion species and ion implantation amount when forming the microbubble layer (encapsulation layer) 106 in the step of FIG. Alternatively, it is possible by controlling the heat treatment temperature, heat treatment profile, etc. in the step of FIG.

  In order to remove the oxide film efficiently and with good reproducibility without increasing the heat treatment time in the process limited to the above surface roughness range, the thickness of the interface oxide film is 3 nm or less. It is desirable to be.

  Further, the diameter of a semiconductor substrate such as a silicon substrate having a DSB junction is mainly 300 mm or more. Therefore, in the high-temperature heat treatment in the reducing gas atmosphere, the heat treatment furnace member is greatly deteriorated due to the reducing gas and the weight of the wafer. Therefore, for example, it is more preferable that the heat treatment is performed in an inert gas atmosphere such as argon gas.

According to the manufacturing method as described above, when a silicon substrate having a DSB structure is conventionally formed, the surface polishing step that has been performed to remove the surface irregularities after the wafer division is omitted, and further, a heat treatment for surface planarization is performed. By performing the heat treatment for removing the interface oxide film by the same heat treatment, the process can be greatly shortened. Further, by omitting the surface polishing step, it is possible to maintain high film thickness uniformity of the upper semiconductor layer.
Furthermore, not only the surface polishing process is omitted, but also the unevenness on the wafer surface that occurs after the division is actively used to promote oxygen out-diffusion to enhance the effect of removing the interfacial oxide film, and efficient planarization and interfacial oxidation. Film removal heat treatment is realized.
Then, the semiconductor substrate of the present embodiment that realizes a high yield of LSI can be manufactured.

  Next, a second manufacturing method of the semiconductor substrate according to the present embodiment will be described. Instead of the smart cut method (hydrogen ion implantation separation method) of the first manufacturing method, a so-called nano cleave method is used. Other than this, the description is omitted because it is the same as the first manufacturing method.

FIG. 8 shows a manufacturing process flow chart of the second manufacturing method of the present embodiment.
The process of preparing the base wafer (first semiconductor wafer) 102 and the bond wafer (second silicon wafer) 104 in FIG. 8A is the same as that in the first embodiment.
Next, as in the first manufacturing method, in the step shown in FIG. 8B, hydrogen ions or rare gas ions are implanted into one surface of the bond wafer 104, and the average penetration depth of the ions is parallel to the wafer surface. A small microbubble layer (encapsulation layer) 106 is formed. However, in this embodiment,
For example, hydrogen ions are implanted at a dose of about 1E17 to 1E18 atoms / cm ² and higher than in the first manufacturing method. This is a request that the nanocleave method of the present manufacturing method does not use foaming by heating, but divides the wafer by a physical cleavage operation, unlike the first embodiment.

Next, in the step shown in FIG. 8C, as in the first manufacturing method, the hydrogen ion-implanted surface of the bond wafer 104 into which hydrogen ions have been implanted and the base wafer 102 are overlapped and brought into close contact with each other.
Next, in the step shown in FIG. 8D, the separation wafer 110 and the silicon substrate 114 are separated with the microbubble layer (encapsulation layer) 106 as a boundary. In this step, not the heat treatment as in the first embodiment, but a pressurized fluid such as gas or liquid, here nitrogen (N ₂ ) gas, is applied from the side surface of the microbubble layer (encapsulation layer) 106. Spray and divide the wafer by physical cleavage.

  Also in the present manufacturing method, the RMS (Root Mean Square) of the surface roughness after the division is controlled to be 3.5 nm or more and 6.5 nm or less, as in the first manufacturing method. This control is performed by, for example, implanting ion species and ion implantation amount when forming the microbubble layer (encapsulation layer) 106 in the process of FIG. 6B, or the fluid ejected in the process of FIG. This is possible by controlling the type, amount, pressure, etc.

  Thereafter, as in the first manufacturing method, the planarization / interfacial oxide film removal heat treatment step of FIG. 8E is performed, and as shown in FIG. 8F, the crystal orientation (110) silicon whose surface is planarized is obtained. A silicon substrate 114 is formed by bonding the substrate upper layer 112 and the base wafer 102 having the crystal orientation (100) at the interface 116 having no silicon oxide film.

As described above, according to this manufacturing method, similarly to the first manufacturing method, when a silicon substrate having a DSB structure is manufactured by joining two wafers, a silicon substrate that maintains a high film thickness uniformity of the upper silicon layer. Surface planarization and removal of the silicon oxide film at the interface between the two wafers can be efficiently performed by the same heat treatment.
Then, the semiconductor substrate of the present embodiment that realizes a high yield of LSI can be manufactured.

  Next, a third method for manufacturing a semiconductor substrate according to the present embodiment will be described, except that a so-called ELTRAN method is used instead of the smart cut method (hydrogen ion implantation separation method) of the first manufacturing method. Since this is the same as the first manufacturing method, the description is omitted.

FIG. 9 shows a manufacturing process flow chart of this manufacturing method.
9A, a base wafer (first semiconductor wafer) 102 and a bond wafer (second silicon wafer) 104 are prepared. Here, the porous silicon layer 118 is formed on the surface of the bond wafer by using an anodizing method (anodic oxidation method) using hydrofluoric acid as a solution.
Next, in the step shown in FIG. 9B, a thin single crystal silicon layer 120 is formed on the surface of the porous silicon layer 118 by epitaxial growth.

Next, in the step shown in FIG. 9C, the surface of the thin film single crystal silicon layer 120 of the bond wafer 104 and the base wafer 102 are overlapped and adhered.
Next, in a process shown in FIG. 9D, the separation wafer 110 and the silicon substrate 114 are separated with the porous silicon layer 118 as a boundary. In this step, the wafer is not formed by using hydrofluoric acid or buffered hydrofluoric acid that can selectively etch only the porous silicon layer 118 with respect to single crystal silicon, instead of the heat treatment as in the first embodiment. To divide.

  Also in the present embodiment, similarly to the first manufacturing method, the RMS (Root Mean Square) of the surface roughness after the division is controlled to be 3.5 nm or more and 6.5 nm or less. This control can be achieved, for example, by controlling the conditions such as the hydrofluoric acid solution concentration in the anodizing method in the step of FIG. 9A or the etching solution concentration in the step of FIG. 9D. .

  Thereafter, as in the first manufacturing method, the planarization / interfacial oxide film removal heat treatment step of FIG. 9E is performed, and as shown in FIG. 9F, the crystal orientation (110) silicon whose surface is flattened is obtained. A silicon substrate 114 is formed by bonding the substrate upper layer 112 and the base wafer 102 having the crystal orientation (100) at the interface 116 having no silicon oxide film.

As described above, according to this manufacturing method, similarly to the first manufacturing method, when a silicon substrate having a DSB structure is manufactured by joining two wafers, a silicon substrate that maintains a high film thickness uniformity of the upper silicon layer. Surface planarization and removal of the silicon oxide film at the interface between the two wafers can be efficiently performed by the same heat treatment.
Then, the semiconductor substrate of the present embodiment that realizes a high yield of LSI can be manufactured.

(Modification of the first embodiment)
Next, a modification of the semiconductor substrate of the present embodiment will be described. The crystal plane orientation of the first silicon wafer surface and the crystal plane orientation of the second silicon wafer surface are, for example, (100) planes or , (110) planes are the same as those of the semiconductor substrate of the first embodiment except that they are the same, and description thereof is omitted.

  According to this modification, the same operation and effect as in the first embodiment can be obtained in a silicon substrate obtained by DSB bonding of wafers having the same plane orientation, as used in MEMS (Micro Electro Mechanical Systems). Is possible.

[Second Embodiment]
In the semiconductor substrate according to the second embodiment of the present invention, the inclination angle (off angle) of the surface of the second silicon wafer with respect to the {100} plane is 0 degree or more and 0.1 degree or less, The same as in the first embodiment, except that the azimuth angle on the {100} plane of the silicon wafer surface with respect to the {100} plane is in the range of ± 21 degrees with respect to the <110> direction. Because there is, description is omitted.

  Here, the azimuth angle on the {100} plane with respect to the {100} plane is in the range of ± 21 degrees with respect to the <110> direction, in other words, <110 on the {100} plane. The angle between the direction and the direction in which the tilt direction is projected on the same {100} plane is in the range of ± 21 degrees.

  In particular, the semiconductor substrate having the silicon surface has a wide flat surface constituted by a crystal plane and can be secured, so that the level difference between the silicon oxide film formed on the silicon surface and the interface can be reduced.

FIG. 10 is an explanatory view schematically showing a surface structure when the semiconductor substrate having the silicon surface is subjected to planarization heat treatment.
This silicon wafer has a step (hereinafter also referred to as a step) structure in which a flat surface (hereinafter also referred to as a terrace) is a (100) crystal plane.
The characteristics of this silicon wafer are characterized by the results of the following evaluation. That is, an arbitrary 3 μm × 3 μm region of this silicon wafer is measured by an atomic force microscope (AFM). The measurement is performed by 10 survey lines with a spacing of approximately 0.3 μm in a direction generally perpendicular to the steps. In this case, 90% or more of the measured value of the terrace width (hereinafter also referred to as terrace width) indicated by W in FIG. 10 is 50 nm or more. Further, 90% or more of the measured value of the step height (hereinafter, step height) represented by H in FIG. 10 corresponds to one atomic layer, that is, 0.136 μm for the (100) plane.
Here, the term “substantially perpendicular” refers to a range of ± 20 degrees with respect to the direction perpendicular to the step, and the term “approximately 0.3 μm interval” refers to a range of 0.25 μm to 0.35 μm.

FIG. 11 shows an AFM image of this silicon wafer. NanoScope IIIa is used as the AFM, and the contact mode is used for measurement. As shown in FIG. 11, the step structure can be clearly seen on the silicon surface. As shown in FIG. 10, the terrace seen in the AFM image of FIG. 11 is the (100) plane. The steps include two types of steps according to Chadi's classification in Physical Review Letters (page 1691, volume 59 (1987)): a linear step Sa and a wavy step Sb. is there. The terrace on the step Sa is characterized by the fact that the arrangement direction of the dimerized atomic sequence is perpendicular to the step as shown in FIG. Further, the terrace on the step Sb is characterized by the fact that the arrangement direction of the dimerized atomic sequence is parallel to the step.
Here, an interval W ′ (FIG. 10) between two adjacent steps Sa is ideally governed by an inclination angle (hereinafter also referred to as an off angle) θ (FIG. 10) with respect to the (100) plane. (Expression 1).
W ′ = 2 × (lattice constant / 4) / tan θ (Expression 1)
For example, in the case of the (100) plane, the lattice constant / 4 = 0.136 nm.

In this embodiment, the inclination angle (off angle) is set to 0 degree or more and 0.1 degree or less when the range is exceeded, the region where the terrace width becomes narrower than 50 nm increases, and one transistor region is formed. This is because there is a probability that the number of such steps will be plural, so that the deterioration of transistor characteristics starts to become remarkable.
That is, as described above, the interval W ′ (FIG. 10) between two adjacent steps Sa is governed by the inclination angle (off angle) θ and can be expressed by the following (Equation 1).
W ′ = 2 × (lattice constant / 4) / tan θ (Expression 1)
Looking at this when θ = 0.1 degrees, W ′ = 156 nm. Since W ′ corresponds to two terrace widths, if Sb comes in the middle of two Sa, the terrace width for one terrace is 78 nm. However, as shown in FIG. 10, since Sb has a wave shape, in order to reliably maintain a terrace width of 50 nm or more in a region of 90% or more, the inclination angle is set to 0.1 degrees or less in view of the margin. It will be necessary.

  FIG. 12 shows a silicon wafer with an azimuth angle of 45 degrees, 20 degrees, and −20 degrees in a hydrogen gas atmosphere at 1200 ° C. for 1 hour with the tilt angle with respect to the {100} plane fixed at 0.0256 degrees. It is a figure which shows the AFM image at the time of performing planarization heat processing. As shown in the figure, no step or terrace was confirmed under the condition of azimuth = 45 degrees. On the other hand, a favorable step structure was confirmed under the conditions of azimuth = 20 degrees and −20 degrees.

  FIG. 13 is a diagram showing an azimuth angle range in which a good step structure is obtained by changing the heat treatment temperature and the azimuth angle. In the figure, when an arbitrary area of 3 μm × 3 μm on the surface of the silicon wafer is set as a measurement area of an atomic force microscope (AFM), the mark “◎” in the measurement area is approximately 0. More than 95% of the measured value of the width (terrace width) of the flat surface measured along 10 measurement lines at intervals of 3 μm is 50 nm or more, and the level difference measured along these 10 measurement lines The case where 95% or more of the measured values of the height (step height) is the height of one atomic layer is shown. In addition, the circles in the figure are the same measurement, and 90% or more of the measured flat surface width (terrace width) is 50 nm or more, and measured along these 10 measurement lines. In this case, 90% or more of the measured height of the step (step height) is the height of one atomic layer. And the x mark in a figure shows the case where a measured value does not correspond to the said range. From this result, it can be seen that a good step structure is formed in the range where the azimuth angle is ± 25 degrees or less.

  As described above, the semiconductor substrate having the silicon surface can secure a wide flat surface composed of crystal planes after heat treatment in an atmosphere of a reducing gas, an inert gas or a mixed gas thereof. The level difference between the silicon oxide film formed on the surface and the interface can be reduced. That is, uneven steps with a period of 100 to 500 nm or less are alleviated. Therefore, the carrier mobility of a transistor using this silicon oxide film as a gate electrode and the leakage current of a capacitor using this silicon oxide film as a gate electrode are further suppressed as compared with the first embodiment. Therefore, the LSI yield can be further improved as compared with the semiconductor substrate of the first embodiment.

[Third Embodiment]
In the semiconductor substrate of the third embodiment of the present invention, the inclination angle (off angle) with respect to the {110} plane of the surface of the second silicon wafer on which the semiconductor device will be formed later is 0 degree or more and 0.2 degree or less. Or the first silicon wafer surface except that the azimuth angle on the {110} plane in the inclined direction with respect to the {110} plane is in the range of ± 26 degrees with respect to the <100> direction. Since this is the same as the embodiment, the description is omitted.

  Here, the azimuth angle on the {110} plane in the tilt direction with respect to the {110} plane is in the range of ± 26 degrees with respect to the <100> direction, in other words, <100 on the {110} plane. The angle between the direction and the direction in which the tilt direction is projected on the same {110} plane is in the range of ± 26 degrees.

  In particular, the semiconductor substrate having the silicon surface can reduce RMS after the surface is heat-treated in a reducing gas, an inert gas, or a mixed gas atmosphere of a reducing gas and an inert gas.

FIG. 14 is a conceptual diagram showing the crystal orientation of the surface of a silicon wafer having a (110) plane. On the (110) plane, for example, when the notch direction is the <100> direction as shown in the figure, the direction orthogonal to this is the <110> direction. Therefore, on the (110) plane, the silicon single crystal is symmetrical twice with respect to the <110> direction indicated by the Z axis in the figure.
FIG. 15 is a diagram showing a result of measuring the RMS of a silicon wafer having a surface of (110) with an off angle of 2 degrees from 0 to 8 degrees, after the surface is mirror-polished and subjected to heat treatment. . The heat treatment was performed in a hydrogen gas atmosphere under conditions of 1200 ° C. and 1 hour, and the furnace discharge was an argon gas atmosphere. In addition, the azimuth angle (tilt direction azimuth) on the (110) plane in the tilt direction is <100> and <110>. Also, the black symbols are when the AFM RMS measurement region is 3 μm × 3 μm, and the white symbols are when the AFM RMS measurement region is 10 μm × 10 μm.

  As is apparent from FIG. 15, the RMS of the (110) surface tends to deteriorate when heat treatment is applied. In particular, when the tilt direction azimuth is <110>, when the tilt angle is in the range of 2 to 5 degrees, the RMS exceeds 1 nm, which is not desirable for securing the yield of semiconductor devices such as LSI. That is, when RMS exceeds 1 nm, there is a risk that the breakdown voltage of an insulating film such as an oxide film formed on the surface and the reliability of the insulating film are deteriorated. In addition, there is a high risk of increased junction leakage at a pn junction that terminates at such a surface.

Therefore, the second silicon wafer surface serving as a device formation region has an inclination angle (off angle) with respect to the {110} plane of 0 ° or more and 0.2 ° or less, or {110} of the second semiconductor wafer surface. It is desirable that the azimuth angle on the {110} plane in the tilt direction with respect to the plane is in a range of ± 26 degrees with respect to the <100> direction.
First, if the tilt angle is 0 ° or more and 0.2 ° or less, an RMS of 1 nm or less that is desirable for device formation can be realized even after heat treatment regardless of the tilt direction orientation. In addition, due to any continuous nature of the crystal, when the tilt direction orientation is changed from <100> to <110>, it is expected that the RMS also deteriorates continuously. Therefore, if the azimuth angle on the {110} plane in the tilt direction with respect to the {110} plane is within a range of ± 26 degrees with respect to the <100> direction, the RMS of 1 nm or less desirable for device formation can be obtained even after heat treatment. Can be expected.
Then, it is confirmed that the azimuth angle of the second semiconductor wafer surface on the {110} plane, which is inclined with respect to the {110} plane, is in the range of ± 2 degrees with respect to the <100> direction. It is more preferable to reliably realize RMS of 1 nm or less desirable for the above.

  As described above, according to the present embodiment, in addition to the operations and effects of the first embodiment, the planarization heat treatment is performed by reconfiguring the silicon surface performed when forming a semiconductor device such as an LSI. In addition, it is possible to obtain an operation and effect that the yield can be improved by preventing the deterioration of the RMS. In other words, according to the present embodiment, uneven steps with a period of 100 to 500 nm or less are alleviated. Therefore, the carrier mobility of a transistor using this silicon oxide film as a gate electrode and the leakage current of a capacitor using this silicon oxide film as a gate electrode are further suppressed as compared with the first embodiment. Therefore, the LSI yield can be further improved as compared with the semiconductor substrate of the first embodiment.

  In the present embodiment, the planarization heat treatment by reconfiguration of the silicon surface has been described by taking a hydrogen gas atmosphere as an example. However, the silicon surface can be regenerated by using other reducing gas, inert gas, or a mixed gas thereof. Because of the construction, these atmospheres are not excluded.

  The embodiments of the present invention have been described above with reference to specific examples. In the description of the embodiment, the description of the semiconductor substrate, the method for manufacturing the semiconductor substrate, etc., which is not directly necessary for the description of the present invention is omitted, but the required semiconductor substrate and the method for manufacturing the semiconductor substrate are omitted. It is possible to appropriately select and use elements related to the above.

  For example, when the crystal plane orientations of the first silicon wafer and the second silicon wafer are different, not only the combination of the {100} plane and the {110} plane described in the embodiment, but also other crystal plane orientation combinations. It does not matter.

Further, for example, in the above embodiment, the case where silicon (Si) is used as the semiconductor material for both the first semiconductor wafer and the second semiconductor wafer has been described. However, it is possible to select any semiconductor material including SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and III / V or II / VI group composite semiconductors.
In addition, all semiconductor substrates that include the elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention.

Sectional conceptual diagram explaining the semiconductor substrate of 1st Embodiment The figure which compares the effect at the time of adding surface planarization heat processing to the semiconductor substrate figure of 1st Embodiment, and the semiconductor substrate of a prior art. The manufacturing process flowchart of the 1st manufacturing method of 1st Embodiment. The figure which shows the result of having calculated the relationship between the film thickness of the semiconductor (silicon) board | substrate upper layer of 1st Embodiment, and the reduction | decrease thickness of the interface oxide film (silicon oxide film) by heat processing by using temperature as a parameter. The figure which shows the result of having investigated the heat processing temperature of planarization and interface oxide film removal of 1st Embodiment, and the reduction | decrease thickness of the interface oxide film by heat processing by experiment using the thickness of the upper layer of a semiconductor substrate as a parameter. The relationship between the heat treatment temperature of the planarization / interfacial oxide film removal heat treatment of the first embodiment and the surface roughness (flatness) after the heat treatment is examined by experiment using the surface roughness (RMS) before the heat treatment as a parameter. FIG. The figure which shows the relationship between the silicon substrate surface roughness before heat processing of 1st Embodiment, and the reduction | decrease thickness of the interface oxide film by heat processing. The manufacturing process flowchart of the 2nd manufacturing method of 1st Embodiment. The manufacturing process flowchart of the 3rd manufacturing method of 1st Embodiment. Explanatory drawing which showed typically the surface structure at the time of performing the planarization heat processing to the silicon substrate of 2nd Embodiment. The AFM image at the time of performing the planarization heat processing to the silicon wafer of 2nd Embodiment. In the second embodiment, an AFM image when the flattening heat treatment is performed by changing the azimuth angle. The figure which shows the azimuth | direction angle range from which the favorable step structure was obtained in 2nd Embodiment. The conceptual diagram which shows the crystal orientation of the silicon wafer surface where the surface has a (110) plane of 3rd Embodiment. The silicon wafer having a (110) surface with an off angle of 2 degrees from 0 degrees to 8 degrees in the third embodiment, the surface was mirror-polished and then heat-treated, and the RMS was measured. FIG.

Explanation of symbols

102 Base wafer (first semiconductor wafer)
104 Bond wafer (second semiconductor wafer)
106 Microbubble layer (encapsulation layer)
108 Interfacial oxide film 110 Release wafer 112 Silicon substrate upper layer 114 Silicon substrate 116 Interface 118 without silicon oxide film Porous silicon layer 120 Thin film single crystal silicon layer

Claims (7)

The first semiconductor wafer and the second semiconductor wafer having a smaller film thickness than the first semiconductor wafer have an interface oxide film of 1 nm or less between the first semiconductor wafer and the second semiconductor wafer. A semiconductor substrate formed by bonding so that
A semiconductor substrate characterized in that when only irregularities having a period of 100 nm or more and 10 μm or less on the surface of the second semiconductor wafer side are extracted, the average height (Rc) of the extracted irregularities is 2 nm or more.   The semiconductor substrate according to claim 1, wherein the period is 500 nm or more and 10 μm or less.   3. The semiconductor substrate according to claim 1, wherein the average height (Rc) is 2 nm or more and 5 nm or less.   The first semiconductor wafer and the second semiconductor wafer are silicon wafers, and one of the crystal plane orientation of the first semiconductor wafer surface and the crystal plane orientation of the second semiconductor wafer surface is , In the range having an inclination angle (off angle) of 0 degree or more and 5 degrees or less with respect to the {100} plane, and the other crystal plane orientation is an inclination angle of 0 degree or more and 5 degrees or less with respect to the {110} plane ( 4. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is in a range having an off angle. The inclination angle (off angle) of the surface of the second semiconductor wafer with respect to the {100} plane is 0 degree or more and 0.1 degree or less,
5. The azimuth angle on the {100} plane of the second semiconductor wafer surface in the tilt direction with respect to the {100} plane is in a range of ± 21 degrees with respect to the <110> direction. Semiconductor substrate. The inclination angle (off angle) of the surface of the second semiconductor wafer with respect to the {110} plane is 0 degree or more and 0.2 degree or less,
Alternatively, the azimuth angle of the second semiconductor wafer surface on the {110} plane inclined with respect to the {110} plane is in the range of ± 26 degrees with respect to the <100> direction. 4. The semiconductor substrate according to 4. The azimuth angle on the {110} plane of the second semiconductor wafer surface with respect to the {110} plane in the inclined direction is in a range of ± 2 degrees with respect to the <100> direction. Semiconductor substrate.