JP2010283021A - Semiconductor sensor device - Google Patents

Semiconductor sensor device Download PDF

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JP2010283021A
JP2010283021A JP2009133178A JP2009133178A JP2010283021A JP 2010283021 A JP2010283021 A JP 2010283021A JP 2009133178 A JP2009133178 A JP 2009133178A JP 2009133178 A JP2009133178 A JP 2009133178A JP 2010283021 A JP2010283021 A JP 2010283021A
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semiconductor sensor
wiring
integrated circuit
chip
sensor device
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JP5427476B2 (en
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Nobunori Sano
宜紀 佐野
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Fujikura Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor sensor device that can reduce the size of a semiconductor sensor device, can avoid a change in the characteristic of a semiconductor sensor, and can electrically connect a semiconductor sensor chip to an integrated circuit chip through the shortest wiring. <P>SOLUTION: The semiconductor sensor device 10 includes an integrated circuit chip 2 embedded in a multilayer wiring board 3, the integrated circuit chip having at one side 2a a particular area α exposed to the outside through an opening 39 formed at the multilayer wiring board. Also, the semiconductor sensor chip 1 is electrically connected via first wiring 25A disposed in a particular area, and supported by a portion required for the connection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体センサ装置に係り、より詳細には、半導体センサの特性の変動を抑制できる半導体センサ装置の構造に関する。   The present invention relates to a semiconductor sensor device, and more particularly to a structure of a semiconductor sensor device that can suppress fluctuations in characteristics of the semiconductor sensor.

従来、半導体センサ装置は、外部環境の状態を検出してセンサ信号を出力する半導体センサチップと、この半導体センサチップから出力されるセンサ信号を演算処理する集積回路チップとを配線基板に実装し、樹脂封止して成形している（たとえば、特許文献１参照）。   Conventionally, a semiconductor sensor device has a semiconductor sensor chip that detects a state of an external environment and outputs a sensor signal, and an integrated circuit chip that performs arithmetic processing on the sensor signal output from the semiconductor sensor chip, mounted on a wiring board, It is molded with resin sealing (see, for example, Patent Document 1).

ところが近年、携帯電話機や、携帯用のパーソナルコンピュータといった携帯電子機器の多機能化に伴い、半導体センサ装置には更なる小型化が要求されている。そこで、従来に比べて小型化を可能とした半導体センサ装置として、厚み方向の一面に半導体センサチップを収容する凹所を形成したパッケージケースを用い、このパッケージケースの上記一面に対向させた状態で信号処理用の集積回路チップを実装するようにしたもの（たとえば、特許文献２参照）や、半導体センサとして圧力センサチップの表面に電気的接続用バンプを形成し、この電気的接続用バンプを半田接合して実装基板上に圧力センサチップを直接実装するようにしたものが提案されている（たとえば、特許文献３参照）。   However, in recent years, with the increase in the number of functions of portable electronic devices such as mobile phones and portable personal computers, further miniaturization of semiconductor sensor devices is required. Therefore, as a semiconductor sensor device that can be reduced in size as compared with the conventional case, a package case in which a recess for housing a semiconductor sensor chip is formed on one surface in the thickness direction is used in a state facing the one surface of the package case. Bumps for electrical connection are formed on the surface of a pressure sensor chip as a semiconductor sensor (for example, see Patent Document 2) on which an integrated circuit chip for signal processing is mounted, and the electrical connection bumps are soldered. There has been proposed one in which a pressure sensor chip is directly mounted on a mounting substrate by bonding (see, for example, Patent Document 3).

また、半導体センサチップと実装基板との線膨張率差に起因して生じる応力を緩和することを可能とするため、実装基板の一表面側と他表面側に応力を緩和する溝部を形成すると共に、この溝部の形成位置を一表面側と他表面側とでずらして蛇腹状構造とするようにしたものが提案されている（たとえば、特許文献４参照）。   In addition, in order to relieve the stress caused by the difference in linear expansion coefficient between the semiconductor sensor chip and the mounting substrate, a groove for relaxing the stress is formed on one surface side and the other surface side of the mounting substrate. There has been proposed a structure in which the formation position of the groove is shifted from one surface side to the other surface side to form a bellows-like structure (see, for example, Patent Document 4).

しかしながら、上述した特許文献１乃至３に記載の半導体センサ装置では、実装基板に対して半導体センサチップを直接実装するものであるため、実装基板と半導体センサチップとの熱膨張率の差異により応力が発生し、半導体センサ特性に変動が生じてしまうことがある。また、上述した特許文献４に記載の半導体センサ装置では、半導体センサチップと、この半導体センサチップから出力されるセンサ信号を演算処理する集積回路チップとを搭載するための実装面積を有する実装基板が必要となり、更なる小型化を達成することができない。しかも、上述した従来の半導体センサ装置では、半導体センサチップと集積回路チップとを実装基板上に実装し、配線によって電気的に接続しなければならず、配線が長くなってしまう。   However, in the semiconductor sensor devices described in Patent Documents 1 to 3 described above, the semiconductor sensor chip is directly mounted on the mounting substrate. Therefore, the stress is caused by the difference in thermal expansion coefficient between the mounting substrate and the semiconductor sensor chip. May occur and the semiconductor sensor characteristics may vary. In the semiconductor sensor device described in Patent Document 4 described above, a mounting substrate having a mounting area for mounting a semiconductor sensor chip and an integrated circuit chip that performs arithmetic processing on sensor signals output from the semiconductor sensor chip is provided. It becomes necessary and further miniaturization cannot be achieved. In addition, in the above-described conventional semiconductor sensor device, the semiconductor sensor chip and the integrated circuit chip must be mounted on the mounting substrate and electrically connected by the wiring, and the wiring becomes long.

特開２００５−１８３８５４号公報JP 2005-183854 A 特開２００５−１２７７５０号公報JP 2005-127750 A 特開平５−３３２８６３号公報Japanese Patent Laid-Open No. 5-332863 特開２００８−４９４６４号公報JP 2008-49464 A

本発明は、上記事情に鑑みて成されたものであり、半導体センサ装置の小型化を達成すると共に、半導体センサの特性の変動を抑制し、半導体センサチップと集積回路チップとを最短配線で電気的に接続することを可能とする半導体センサ装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, achieves downsizing of the semiconductor sensor device, suppresses fluctuations in characteristics of the semiconductor sensor, and electrically connects the semiconductor sensor chip and the integrated circuit chip with the shortest wiring. An object of the present invention is to provide a semiconductor sensor device that can be connected to each other.

本発明の請求項１に係る半導体センサ装置は、多層配線基板と、前記多層配線基板の内部に埋設されると共に、該多層配線基板に設けた開口部により、特定領域が外部へ露呈された一面を有する集積回路チップと、前記集積回路チップの特定領域内に配される第１配線部を介して電気的に接続され、かつ、該接続に要する部位により支持されている半導体センサチップと、を少なくとも備えたことを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor sensor device including a multilayer wiring board and a specific area exposed to the outside by an opening provided in the multilayer wiring board and embedded in the multilayer wiring board. An integrated circuit chip, and a semiconductor sensor chip that is electrically connected via a first wiring portion disposed in a specific region of the integrated circuit chip and supported by a portion required for the connection. It is provided with at least.

本発明の請求項２に係る半導体センサ装置は、請求項１に記載の半導体センサ装置において、前記接続に要する部位が半田バンプであることを特徴とする。   A semiconductor sensor device according to a second aspect of the present invention is the semiconductor sensor device according to the first aspect, wherein the portion required for the connection is a solder bump.

本発明の請求項３に係る半導体センサ装置は、請求項１又は２に記載の半導体センサ装置において、前記多層配線基板は、前記半導体センサチップが配置された側に位置する一面に第２配線部、および、該第２配線部と前記第１配線部とを電気的に接続する貫通電極、を備えていることを特徴とする。   A semiconductor sensor device according to a third aspect of the present invention is the semiconductor sensor device according to the first or second aspect, wherein the multilayer wiring board has a second wiring portion on one surface located on a side where the semiconductor sensor chip is disposed. And a through electrode that electrically connects the second wiring portion and the first wiring portion.

本発明の請求項４に係る半導体センサ装置は、請求項１乃至３のいずれか１項に記載の半導体センサ装置において、前記多層配線基板は、前記一面の反対側に位置する他面に第３配線部、および、該第３配線部と前記第２配線部とを電気的に接続する他の貫通電極、を備えていることを特徴とする。   A semiconductor sensor device according to a fourth aspect of the present invention is the semiconductor sensor device according to any one of the first to third aspects, wherein the multilayer wiring board is third on the other surface located on the opposite side of the one surface. A wiring portion and another through electrode that electrically connects the third wiring portion and the second wiring portion are provided.

本発明の半導体センサ装置は、多層配線基板の内部に集積回路チップが埋設され、この集積回路チップは、多層配線基板に設けた開口部により外部へ露呈される特定領域を一面に有する。また、この特定領域内に配される第１配線部を介して半導体センサチップを電気的に接続し、この半導体センサチップを接続に要する部位により支持する。ゆえに、多層配線基板の内部に埋設された集積回路チップに半導体センサチップが接続されるので、実装面積を縮小することが可能であり、装置が小型化されるものとなる。また、集積回路チップが半導体センサチップを、多層配線基板を介さず、電気的接続に要する部位により支持するので、実装基板と半導体センサチップとの熱膨張率の差異により発生する応力で半導体センサの特性が変動することを防ぎ、装置の長期信頼性が向上するものとなる。さらに、半導体センサチップと集積回路チップとが、特定領域内において対向して配され実装しているので、半導体センサチップと集積回路チップとの接続を最短配線とすることができる。
したがって、半導体センサ装置の小型化を達成すると共に、半導体センサの特性が変動することを抑制し、半導体センサチップと集積回路チップとを最短配線で電気的に接続することを可能とする半導体センサ装置を提供することができる。 In the semiconductor sensor device of the present invention, an integrated circuit chip is embedded in a multilayer wiring board, and this integrated circuit chip has a specific area exposed to the outside through an opening provided in the multilayer wiring board. In addition, the semiconductor sensor chip is electrically connected through the first wiring portion arranged in the specific region, and the semiconductor sensor chip is supported by a portion required for connection. Therefore, since the semiconductor sensor chip is connected to the integrated circuit chip embedded in the multilayer wiring board, the mounting area can be reduced and the apparatus can be miniaturized. In addition, since the integrated circuit chip supports the semiconductor sensor chip by a portion required for electrical connection without using a multilayer wiring board, the stress of the semiconductor sensor due to the difference in coefficient of thermal expansion between the mounting board and the semiconductor sensor chip. The characteristic is prevented from fluctuating and the long-term reliability of the device is improved. Furthermore, since the semiconductor sensor chip and the integrated circuit chip are arranged to be opposed to each other in the specific region, the connection between the semiconductor sensor chip and the integrated circuit chip can be made the shortest wiring.
Therefore, a semiconductor sensor device that achieves miniaturization of the semiconductor sensor device, suppresses fluctuations in the characteristics of the semiconductor sensor, and can electrically connect the semiconductor sensor chip and the integrated circuit chip with the shortest wiring. Can be provided.

本発明に係る半導体センサ装置の一実施の形態の構成を示す断面図。Sectional drawing which shows the structure of one Embodiment of the semiconductor sensor apparatus which concerns on this invention. 本発明に係る半導体センサ装置に埋設される集積回路チップの製造方法を工程順に示す断面図。Sectional drawing which shows the manufacturing method of the integrated circuit chip embed | buried under the semiconductor sensor apparatus which concerns on this invention in process order. 本発明に係る半導体センサ装置の製造方法を工程順に示す断面図。Sectional drawing which shows the manufacturing method of the semiconductor sensor apparatus which concerns on this invention in process order. 図３に続く工程を順に示す断面図。Sectional drawing which shows the process following FIG. 3 in order.

以下、本発明を実施した半導体センサ装置の一例について、図面を参照して説明する。
図１は、本発明に係る半導体センサ装置の一実施の形態の構成を示す断面図である。
図１に示すように、本発明に係る半導体センサ装置１０は、半導体センサチップ１と、この半導体センサチップ１から出力されるセンサ信号を演算処理する集積回路チップ２と、半導体センサチップ１及び集積回路チップ２を実装する多層配線基板３とを少なくとも備える。 Hereinafter, an example of a semiconductor sensor device embodying the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing the configuration of an embodiment of a semiconductor sensor device according to the present invention.
As shown in FIG. 1, a semiconductor sensor device 10 according to the present invention includes a semiconductor sensor chip 1, an integrated circuit chip 2 that performs arithmetic processing on sensor signals output from the semiconductor sensor chip 1, a semiconductor sensor chip 1, and an integrated circuit. At least a multilayer wiring board 3 on which the circuit chip 2 is mounted is provided.

半導体センサチップ１は、物理量を電気信号に変換して出力するものであり、たとえば、半導体圧力センサチップを挙げることができる。この半導体圧力センサは、たとえば、単結晶シリコン等のダイヤフラム上にピエゾ抵抗効果を有する材料でできた複数個の半導体歪ゲージをブリッジ接続した構成となっている。そして、圧力変化によりダイヤフラムが変形すると、その変形量に応じて半導体歪ゲージのゲージ抵抗が変化し、その変化量が電圧信号としてブリッジ回路から取り出されるようになっている。   The semiconductor sensor chip 1 converts a physical quantity into an electrical signal and outputs it, and examples thereof include a semiconductor pressure sensor chip. This semiconductor pressure sensor has, for example, a configuration in which a plurality of semiconductor strain gauges made of a material having a piezoresistance effect are bridge-connected on a diaphragm such as single crystal silicon. When the diaphragm is deformed by a pressure change, the gauge resistance of the semiconductor strain gauge is changed according to the deformation amount, and the change amount is taken out from the bridge circuit as a voltage signal.

集積回路チップ２は、多層配線基板３の内部に埋設されると共に、この多層配線基板３に設けた開口部３９により、特定領域αが外部へ露呈された一面２ａを有する。また、集積回路チップ２は、この一面２ａに第１配線部２５を備える。図１において第１配線部２５は、半導体センサチップ１と半田バンプ５を介して電気的に接続される部分が符号２５Ａで示されている。また、第１配線部２５は、後述する多層配線基板３において半導体センサチップ１が配置された側に位置する一面に形成された第２配線部３２Ａと貫通電極３７を介して電気的に接続される他の第１配線部２５Ｂを備えている。   The integrated circuit chip 2 is embedded in the multilayer wiring board 3 and has a surface 2a in which the specific region α is exposed to the outside through an opening 39 provided in the multilayer wiring board 3. Further, the integrated circuit chip 2 includes a first wiring portion 25 on the one surface 2a. In FIG. 1, the first wiring portion 25 is indicated by reference numeral 25 </ b> A at a portion that is electrically connected to the semiconductor sensor chip 1 via the solder bump 5. Further, the first wiring part 25 is electrically connected to the second wiring part 32A formed on one surface located on the side where the semiconductor sensor chip 1 is arranged in the multilayer wiring board 3 to be described later via a through electrode 37. The other 1st wiring part 25B is provided.

本発明に係る半導体センサ装置１０において、半導体センサチップ１は、集積回路チップ２の特定領域α内に集積回路チップ２と対向して配され、半田バンプ５を介して電気的に集積回路チップ２と接続している。
このように集積回路チップ２が多層配線基板３の内部に埋設され、半導体センサチップ１が、外部へ露呈された特定領域αにおいて集積回路チップ２と対向して配されることで、半導体センサチップ１の搭載に要する基板表面の領域（実装面積）を最小限に抑えることができ、半導体センサ装置１０の小型化を容易に図ることができる。また、半導体センサチップ１と集積回路チップ２との接続を最短配線とすることができる。しかも、半田バンプ５を用いて接続することで、配線を用いる必要もない。 In the semiconductor sensor device 10 according to the present invention, the semiconductor sensor chip 1 is arranged in the specific region α of the integrated circuit chip 2 so as to face the integrated circuit chip 2 and electrically integrated with the integrated circuit chip 2 via the solder bumps 5. Connected.
As described above, the integrated circuit chip 2 is embedded in the multilayer wiring board 3, and the semiconductor sensor chip 1 is disposed so as to face the integrated circuit chip 2 in the specific area α exposed to the outside. The area (mounting area) of the substrate surface required for mounting 1 can be minimized, and the semiconductor sensor device 10 can be easily downsized. Further, the connection between the semiconductor sensor chip 1 and the integrated circuit chip 2 can be the shortest wiring. In addition, since the solder bumps 5 are used for connection, it is not necessary to use wiring.

また、半導体センサ装置１０において、集積回路チップ２は、半導体センサチップ１を第１配線部２５Ａとの接続に要する部位のみにより支持する。すなわち、半導体センサチップ１は多層配線基板３を介さずに支持されている。これにより、多層配線基板３と半導体センサチップ１との熱膨張率の差異により発生する応力で半導体センサの特性が変動することを防ぐことができる。   Further, in the semiconductor sensor device 10, the integrated circuit chip 2 supports the semiconductor sensor chip 1 only by a portion necessary for connection with the first wiring portion 25A. That is, the semiconductor sensor chip 1 is supported without interposing the multilayer wiring board 3. Thereby, it is possible to prevent the characteristics of the semiconductor sensor from fluctuating due to the stress generated due to the difference in thermal expansion coefficient between the multilayer wiring board 3 and the semiconductor sensor chip 1.

多層配線基板３は、予め個別に作製された配線付き基材を積層し、一括して多層化することにより大略構成されている。配線付き基材は、絶縁性基材の片面または両面に銅箔等の導電層が積層されたものである。この絶縁性基材としては、たとえば、ポリイミド、ポリイミド複合材料が用いられる。絶縁性基材の厚さは、５〜５０μｍくらいの範囲であれば特に制限されるものではない。また、銅箔の厚さは、一般的に使用される３〜２５μｍくらいの範囲であれば特に制限されるものではない。図１において多層配線基板３は、配線付き第１基材３Ａ、配線付き第２基材３Ｂ、配線付き第３基材３Ｃといった三つの配線付き基材によって構成されているが、配線付き基材の数はこれに限定されるものではない。   The multilayer wiring board 3 is generally configured by laminating substrates with wiring prepared individually in advance and forming a multilayer in a lump. The substrate with wiring is obtained by laminating a conductive layer such as a copper foil on one or both surfaces of an insulating substrate. As this insulating substrate, for example, polyimide or a polyimide composite material is used. The thickness of the insulating substrate is not particularly limited as long as it is in the range of about 5 to 50 μm. Moreover, the thickness of copper foil will not be restrict | limited especially if it is the range of about 3-25 micrometers generally used. In FIG. 1, the multilayer wiring board 3 is constituted by three substrates with wiring, such as a first substrate with wiring 3A, a second substrate with wiring 3B, and a third substrate with wiring 3C. The number of is not limited to this.

配線付き第１基材３Ａは、多層配線基板３において半導体センサチップ１が配置される一方の側に位置する外層基材となるものであり、一方の面に第２配線部３２Ａを備えると共に、他方の面に接着層３３を備える。また、配線付き第１基材３Ａは、一方の面から接着層３３の他方の面までを貫通する、導電性ペーストからなる貫通電極３７，３８を備える。すなわち、多層配線基板３は、半導体センサチップ１が配置された側に位置する一面に第２配線部３２Ａを備え、および、この第２配線部３２Ａと、半導体センサチップ１と電気的に接続された集積回路チップ２における第１配線部２５Ａとは異なる他の第１配線部２５Ｂとを電気的に接続する貫通電極３７を備えている。   The first base material 3A with wiring is an outer layer base material positioned on one side where the semiconductor sensor chip 1 is disposed in the multilayer wiring board 3, and includes the second wiring portion 32A on one surface, An adhesive layer 33 is provided on the other surface. In addition, the first substrate with wiring 3 </ b> A includes through electrodes 37 and 38 made of a conductive paste that penetrates from one surface to the other surface of the adhesive layer 33. That is, the multilayer wiring board 3 includes the second wiring portion 32A on one surface located on the side where the semiconductor sensor chip 1 is disposed, and is electrically connected to the second wiring portion 32A and the semiconductor sensor chip 1. The integrated circuit chip 2 includes a through electrode 37 that electrically connects the first wiring part 25B different from the first wiring part 25A.

これにより、集積回路チップ２で処理した半導体センサチップ１からの電気信号を、集積回路チップ２の他の第１配線部２５Ｂを介して多層配線基板３の埋設部から貫通電極３７と第２配線部３２Ａにより外部へ出力させることができる。また、装置外部から集積回路チップ２への電源供給を行うことも可能となる。   As a result, the electrical signal from the semiconductor sensor chip 1 processed by the integrated circuit chip 2 is transferred from the embedded portion of the multilayer wiring board 3 to the through electrode 37 and the second wiring via the other first wiring portion 25B of the integrated circuit chip 2. It can be output to the outside by the part 32A. In addition, it is possible to supply power to the integrated circuit chip 2 from the outside of the apparatus.

配線付き第２基材３Ｂは、多層配線基板３における内層基材となるものであり、集積回路チップ２の周囲と隙間を形成する大きさをした開口部を有する。また、配線付き第２基材３Ｂは、一方の面に第１層間配線部４２Ａを備えると共に、他方の面に第２層間配線部４５Ａを備え、さらに、一方の面から他方の面までを貫通する、メッキからなる貫通電極４４を備える   The second base material 3B with wiring is an inner layer base material in the multilayer wiring board 3, and has an opening that is sized to form a gap with the periphery of the integrated circuit chip 2. In addition, the second base material 3B with wiring is provided with the first interlayer wiring portion 42A on one surface and the second interlayer wiring portion 45A on the other surface, and further penetrates from one surface to the other surface. A through electrode 44 made of plating is provided.

配線付き第３基材３Ｃは、多層配線基板３における他方の側に位置する外層基材となるものであり、一方の面（すなわち、半導体センサチップ１が配置された側に位置する一面３ａの反対側に位置する他面３ｂ）に第３配線部５２Ａを備えると共に、他方の面に接着層５３を備え、さらに、一方の面から接着層５３の他方の面までを貫通する、導電性ペーストからなる貫通電極５６を備える。そして、第３配線部５２Ａに半田バンプ６を設けることで、多層配線基板３は、他面３ｂに複数の半田バンプ６・・６を備えるものとすることができる。   The third base material 3C with wiring is an outer layer base material located on the other side of the multilayer wiring board 3, and is provided on one surface (that is, one surface 3a located on the side where the semiconductor sensor chip 1 is disposed). Conductive paste provided with the third wiring portion 52A on the other surface 3b) located on the opposite side, the adhesive layer 53 on the other surface, and penetrating from one surface to the other surface of the adhesive layer 53 A through electrode 56 is provided. The multilayer wiring board 3 can be provided with a plurality of solder bumps 6... 6 on the other surface 3b by providing the solder bumps 6 on the third wiring portion 52A.

以上のように多層配線基板３は、配線付き第２基材３Ｂに形成された開口部４９内に集積回路チップ２を配置し、配線付き第１基材３Ａと配線付き第３基材３Ｃとによって挟み込むと共に、集積回路チップ２の周囲を接着層３３，５３からなる層間接着材４で保護するように、その内部に集積回路チップ２を埋設したものとなっている。   As described above, the multilayer wiring board 3 has the integrated circuit chip 2 disposed in the opening 49 formed in the second base material 3B with wiring, and the first base material 3A with wiring and the third base material 3C with wiring. The integrated circuit chip 2 is embedded inside the integrated circuit chip 2 so that the periphery of the integrated circuit chip 2 is protected by the interlayer adhesive 4 made of the adhesive layers 33 and 53.

層間接着材４（３３，５３）は、一般的に使用されるエポキシ系、アクリル系などの接着材が適用可能であるが、本発明では特に限定されるものではない。図１において、配線付き第１基材３Ａと配線付き第２基材３Ｂとは、接着層３３による接着によって積層され、配線付き第２基材３Ｂと配線付き第３基材３Ｃとは、接着層５３による接着によって積層されている。   The interlayer adhesive 4 (33, 53) may be an epoxy or acrylic adhesive that is generally used, but is not particularly limited in the present invention. In FIG. 1, the first base material 3A with wiring and the second base material 3B with wiring are laminated by adhesion by the adhesive layer 33, and the second base material 3B with wiring and the third base material 3C with wiring are bonded. The layers 53 are laminated by adhesion.

また、多層配線基板３は、一面３ａの反対側に位置する他面３ｂに第３配線部５２Ａ、および、この第３配線部５２Ａと第２配線部３２Ａとを電気的に接続する他の貫通電極３８，４４，５６を備えている。すなわち、配線付き第１基材３Ａの一面に形成された第２配線部３２Ａと、配線付き第２基材３Ｂの一面に形成された第１層間配線部４２Ａとは、層間第１貫通電極３８によって電気的に接続されている。また、配線付き第２基材３Ｂの一面に形成された第１層間配線部４２Ａと配線付き第２基材３Ｂの他面に形成された第２層間配線部４５Ａとは、層間第２貫通電極４４によって電気的に接続されている。さらに、配線付き第２基材３Ｂの他面に形成された第２層間配線部４５Ａと配線付き第３基材３Ｃの一面に形成された第３配線部５２Ａとは、層間第３貫通電極５６によって電気的に接続されている。   In addition, the multilayer wiring board 3 has a third wiring portion 52A on the other surface 3b located on the opposite side of the one surface 3a, and other penetrations that electrically connect the third wiring portion 52A and the second wiring portion 32A. Electrodes 38, 44, and 56 are provided. That is, the second wiring portion 32A formed on one surface of the first base material 3A with wiring and the first interlayer wiring portion 42A formed on one surface of the second base material 3B with wiring are the interlayer first through electrode 38. Are electrically connected. Further, the first interlayer wiring portion 42A formed on one surface of the second base material 3B with wiring and the second interlayer wiring portion 45A formed on the other surface of the second base material 3B with wiring are interlayer second through electrodes. 44 is electrically connected. Furthermore, the second interlayer wiring portion 45A formed on the other surface of the second base material 3B with wiring and the third wiring portion 52A formed on one surface of the third base material 3C with wiring include the interlayer third through electrode 56. Are electrically connected.

したがって、配線付き第１基材３Ａの一面に形成された第２配線部３２Ａと配線付き第３基材３Ｃの一面に形成された第３配線部５２Ａとは、層間第１貫通電極３８、第１層間配線部４２Ａ、層間第２貫通電極４４、第２層間配線部４５Ａ、層間第３貫通電極５６によって電気的に接続されている。これにより、多層配線基板３の他面３ｂにおいて、集積回路チップ２で処理した半導体センサチップ１からの電気信号を外部へ出力させたり、装置外部から集積回路チップ２への電源供給を行ったりすることも可能となる。   Therefore, the second wiring portion 32A formed on one surface of the first base material 3A with wiring and the third wiring portion 52A formed on one surface of the third base material 3C with wiring include the interlayer first through electrode 38, the first The first interlayer wiring portion 42A, the interlayer second through electrode 44, the second interlayer wiring portion 45A, and the interlayer third through electrode 56 are electrically connected. Thereby, on the other surface 3b of the multilayer wiring board 3, an electrical signal from the semiconductor sensor chip 1 processed by the integrated circuit chip 2 is output to the outside, or power is supplied to the integrated circuit chip 2 from the outside of the apparatus. It is also possible.

次に、本発明を実施した半導体センサ装置１０の製造方法について説明する。
初めに、集積回路チップ２となるＩＣチップの製造方法について、図２を参照して説明する。図２（ａ）乃至（ｄ）は、本発明に係る半導体センサ装置１０における多層配線基板３に埋設される集積回路チップ２の製造方法を示す工程断面図である。 Next, a method for manufacturing the semiconductor sensor device 10 embodying the present invention will be described.
First, a method for manufacturing an IC chip to be the integrated circuit chip 2 will be described with reference to FIG. 2A to 2D are process cross-sectional views illustrating a method of manufacturing the integrated circuit chip 2 embedded in the multilayer wiring board 3 in the semiconductor sensor device 10 according to the present invention.

まず、図２（ａ）に示すように、たとえば、各チップ領域内にパッド２２が形成されたシリコンウエハでなる半導体基板２１を準備する。
次いで、図２（ｂ）に示すように、半導体基板２１の表面に、液状の感光性ポリイミド前駆体をスピンコートし、フォトリソグラフィー技術を用いて、パッド２２上にコンタクトホール２４を形成し、これを焼成して絶縁層２３を形成する。 First, as shown in FIG. 2A, for example, a semiconductor substrate 21 made of a silicon wafer having pads 22 formed in each chip region is prepared.
Next, as shown in FIG. 2B, the surface of the semiconductor substrate 21 is spin-coated with a liquid photosensitive polyimide precursor, and a contact hole 24 is formed on the pad 22 by using a photolithography technique. Is fired to form the insulating layer 23.

引き続き、図２（ｃ）に示すように、セミアデイテイブ法を用いて、コンタクトホール２４内および絶縁層２３上に、第１配線部となる導電層２５（２５Ａ，２５Ｂ）を形成する。
そして、プロービングにより検査を行った後、図２（ｄ）に示すように、図示しないダイシングラインに沿って切り離すことによって集積回路チップ２を個片化する。図２（ｄ）において、３つの集積回路チップ２に個片化された状態が示されている。 Subsequently, as shown in FIG. 2C, a conductive layer 25 (25A, 25B) serving as a first wiring portion is formed in the contact hole 24 and on the insulating layer 23 by using a semi-additive method.
Then, after inspection by probing, as shown in FIG. 2D, the integrated circuit chip 2 is separated into pieces by cutting along a dicing line (not shown). FIG. 2D shows a state in which the integrated circuit chip 2 is divided into three pieces.

なお、本実施の形態においては、基板として、線膨張係数がシリコンに近いガラス基板を用いることもできる。また、絶縁層２３の材料として感光性ポリイミド前駆体を用いたが、他の材料として、ベンゾシクロブテン（ＢＣＢ）や、ポリベンゾオキサゾール（ＰＢＯ）などを用いることができる。また、感光性樹脂は、必ずしもスピンコートによって塗布されなくとも良く、カーテンコートやスクリーン印刷、スピレーコートなどで行っても良い。さらに、感光性樹脂は、液状のものに限定されることはなく、フィルム状の樹脂を半導体基板２１にラミネートしても良い。   In this embodiment, a glass substrate having a linear expansion coefficient close to that of silicon can be used as the substrate. Moreover, although the photosensitive polyimide precursor was used as a material of the insulating layer 23, benzocyclobutene (BCB), polybenzoxazole (PBO), etc. can be used as another material. The photosensitive resin is not necessarily applied by spin coating, and may be performed by curtain coating, screen printing, spine coating, or the like. Further, the photosensitive resin is not limited to a liquid resin, and a film-like resin may be laminated on the semiconductor substrate 21.

また、一般的にＩＣチップの表面を被覆、保護している酸化珪素、または窒化珪素などの無機絶縁皮膜上に、直接導電層２５を形成することもできる。
このようにして作製されたＩＣチップの回路には、通常の導電用回路の他、インダクタやキャパシタ、抵抗などの機能を付与させることも可能である。 In general, the conductive layer 25 can also be formed directly on an inorganic insulating film such as silicon oxide or silicon nitride covering and protecting the surface of the IC chip.
In addition to a normal conductive circuit, functions of an inductor, a capacitor, a resistor, and the like can be imparted to the circuit of the IC chip thus manufactured.

引き続き、上記工程で作製した集積回路チップ２を用いて実施した、本発明の半導体センサ装置１０の製造方法について説明する。図３（ａ）乃至（ｆ）、及び図４（ａ）乃至（ｃ）は、本発明に係る半導体センサ装置１０の製造方法を示す工程断面図である。
まず、図３（ａ）に示すように、たとえば、ポリイミド樹脂フィルムでなる絶縁基材３１の一方の面に、たとえば１２μｍの厚さの銅箔を貼り合わせた導電層３２を有する片面銅張板［以下、「ＣＣＬ」（Copper Clad Laminate）という。］を用意する。 Next, a method for manufacturing the semiconductor sensor device 10 of the present invention, which is performed using the integrated circuit chip 2 manufactured in the above process, will be described. 3A to 3F and FIGS. 4A to 4C are process cross-sectional views illustrating a method for manufacturing the semiconductor sensor device 10 according to the present invention.
First, as shown in FIG. 3 (a), for example, a single-sided copper-clad plate having a conductive layer 32 in which a copper foil having a thickness of, for example, 12 μm is bonded to one surface of an insulating base 31 made of a polyimide resin film. [Hereinafter referred to as “CCL” (Copper Clad Laminate). ] Is prepared.

また、本実施の形態では、絶縁基材３１に銅箔を貼り合わせた導電層３２を有するＣＣＬを用いたが、銅箔にポリイミドワニスを塗布してワニスを硬化させた、所謂キャスティング法により作製されたＣＣＬを使用することもできる。また、ポリイミド樹脂フィルム上にシード層をスパッタし、めっきにより銅を成長させたＣＣＬや、圧延または電解銅箔とポリイミド樹脂フィルムとを接着剤によって貼り合わせたＣＣＬを使用することもできる。絶縁基材３１は、液晶ポリマーなどのプラスチックフィルムを使用することもできる。銅のエッチャントは、塩化第二鉄を主成分とするものに限らず、塩化第二銅を主成分とするエッチャントを用いてもよい。   Further, in this embodiment, the CCL having the conductive layer 32 in which the copper foil is bonded to the insulating base material 31 is used. It is also possible to use a CCL that has been modified. Alternatively, CCL obtained by sputtering a seed layer on a polyimide resin film and growing copper by plating, or CCL obtained by bonding rolled or electrolytic copper foil and a polyimide resin film with an adhesive may be used. The insulating base material 31 can also use a plastic film such as a liquid crystal polymer. The copper etchant is not limited to ferric chloride as a main component, and an etchant having cupric chloride as a main component may be used.

次に、図３（ｂ）に示すように、導電層３２上に、フォトリソグラフィー技術を用いて、図示しないエッチングレジストをパターニングした後、たとえば、塩化第二鉄を主成分とするエッチャントを用いてウェットエッチングにより回路パターン（第２配線部）３２Ａを形成し、エッチングレジストを除去する。   Next, as shown in FIG. 3B, after patterning an etching resist (not shown) on the conductive layer 32 using a photolithography technique, for example, using an etchant containing ferric chloride as a main component. A circuit pattern (second wiring portion) 32A is formed by wet etching, and the etching resist is removed.

引き続き、図３（ｃ）に示すように、絶縁基材３１における回路パターン（第２配線部）３２Ａと反対側の面に、接着層３３及び樹脂フィルム３４を加熱圧着により貼り合わせる。接着層３３としては、たとえば、２５μｍ厚のエポキシ系熱硬化性フィルム接着材を用いることができる。また、樹脂フィルム３４は、たとえば、２５μｍ厚のポリイミドフィルムを用いることができる。加熱圧着には、たとえば、真空ラミネータを用い、減圧下の雰囲気中にて、接着層３３の硬化温度以下の温度で、０．３ＭＰａの圧力でプレスして貼り合わせることができる。   Subsequently, as shown in FIG. 3C, the adhesive layer 33 and the resin film 34 are bonded to the surface of the insulating base 31 opposite to the circuit pattern (second wiring portion) 32A by thermocompression bonding. As the adhesive layer 33, for example, an epoxy thermosetting film adhesive having a thickness of 25 μm can be used. Further, as the resin film 34, for example, a polyimide film having a thickness of 25 μm can be used. For thermocompression bonding, for example, a vacuum laminator can be used and pressed and bonded at a temperature not higher than the curing temperature of the adhesive layer 33 at a pressure of 0.3 MPa in an atmosphere under reduced pressure.

なお、使用する接着層３３は、エポキシ系熱硬化性フィルム接着材に限定されることはなく、アクリル系などの接着材も使用できるし、熱可塑性ポリイミドなどに代表される熱可塑性接着材であってもよい。また、接着層３３は、必ずしもフィルム状で無くともよく、ワニス状の「樹脂を用いてもよい。
樹脂フィルム３４は、ポリイミドの他に、ＰＥＴ（ポリエチレンテレフタレート：poly ethylene terephthalate）や、ＰＥＮ（ポリエチレンナフタレート：poly ethylene naphthalate）などのプラスチックフィルムを使用することも可能であり、また、ＵＶ（紫外線）照射によって接着や剥離が可能なフィルムを使用することもできる。 The adhesive layer 33 to be used is not limited to an epoxy thermosetting film adhesive, and an acrylic adhesive can also be used. It is a thermoplastic adhesive represented by thermoplastic polyimide. May be. Further, the adhesive layer 33 is not necessarily in the form of a film, and a varnish-like “resin may be used.
As the resin film 34, it is also possible to use a plastic film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) in addition to polyimide, and UV (ultraviolet light). A film that can be bonded or peeled off by irradiation can also be used.

次いで、図３（ｄ）に示すように、ＹＡＧレーザを用いて、絶縁基材３１、接着層３３及び樹脂フィルム３４に、たとえば直径１００μｍのビアホール３５を形成する。   Next, as shown in FIG. 3D, via holes 35 having a diameter of, for example, 100 μm are formed in the insulating base material 31, the adhesive layer 33, and the resin film 34 using a YAG laser.

さらに、ＣＦ４及びＯ２混合ガスによるプラズマデスミア処理を施した後に、図３（ｅ）に示すように、スクリーン印刷法により、ビアホール３５に導電性ペーストを充填して貫通電極３７，３８を形成すること共に、集積回路チップ２の定領域αを外部へ露呈させるための開口部３９を形成し、樹脂フィルム３４を剥離する。このとき、印刷充填した導電性ペーストからなる貫通電極３７，３８の先端は、剥離した樹脂フィルム３４の厚さ分だけ、接着層３３の表面より突出し、突起を形成している。このようにして、配線付き第１基材３Ａが作製できる。 Further, after performing a plasma desmear process using a mixed gas of CF 4 and O 2 , as shown in FIG. 3E, the via holes 35 are filled with a conductive paste by screen printing to form through electrodes 37 and 38. At the same time, an opening 39 for exposing the constant region α of the integrated circuit chip 2 to the outside is formed, and the resin film 34 is peeled off. At this time, the tips of the through electrodes 37 and 38 made of the conductive paste filled with printing protrude from the surface of the adhesive layer 33 by the thickness of the peeled resin film 34 to form protrusions. Thus, the 1st base material 3A with a wiring can be produced.

そして、図３（ｆ）に示すように、配線付き第１基材３Ａに、先程製造方法を説明した集積回路チップ２を半導体チップマウンタで位置合わせし、接着材及び導電性ペーストの硬化温度以下で加熱して仮留めする。すなわち、集積回路チップ２の特定領域αが配線付き第１基材３Ａの開口部３９より露呈するように、配線付き第１基材３Ａの貫通電極３７と、集積回路チップ２の他の第１配線部２５Ｂとを電気的に接続する。   And as shown in FIG.3 (f), the integrated circuit chip 2 which demonstrated the manufacturing method is aligned with the 1st base material 3A with wiring with a semiconductor chip mounter, and it is below the hardening temperature of an adhesive material and an electrically conductive paste. Heat with tentatively. That is, the through electrode 37 of the first base material 3A with wiring and the other first of the integrated circuit chip 2 so that the specific region α of the integrated circuit chip 2 is exposed from the opening 39 of the first base material 3A with wiring. The wiring part 25B is electrically connected.

また、図４（ａ）に示すように、配線付き第１基材３Ａの接着層３３側に、仮留めされた集積回路チップ２の周囲と隙間を形成する大きさをした開口部４９を有する配線付き第２基材３Ｂを配置する。配線付き第２基材３Ｂは、配線付き第１基材３Ａと同様の方法により、絶縁基材４１の一方の面に回路パターン（第１層間配線部）４２Ａを形成すると共に、貫通電極４４を有し、さらに、絶縁基材４１の他方の面に回路パターン（第２層間配線部）４５Ａを形成する。すなわち、配線付き第２基材３Ｂは、たとえば、ポリイミドでなる絶縁基材４１の一方の面に回路パターン（第１層間配線部）４２Ａが形成されると共に、他方の面に回路パターン（第２層間配線部）４５Ａが形成され、これらの回路パターン（第１層間配線部）４２Ａと回路パターン４５Ａが絶縁基材４１を挟んで重なる部分にビアホールが形成され、このビアホール内に導電性ペーストを印刷充填することで貫通電極４４が形成されている。そして、配線付き第１基材３Ａの貫通電極３８と、配線付き第２基材３Ｂの回路パターン（第１層間配線部）４２Ａとを電気的に接続する。   Further, as shown in FIG. 4A, an opening 49 having a size that forms a gap with the periphery of the temporarily attached integrated circuit chip 2 is provided on the adhesive layer 33 side of the first base material 3A with wiring. A second base material 3B with wiring is disposed. The second base material 3B with wiring forms a circuit pattern (first interlayer wiring portion) 42A on one surface of the insulating base material 41 by the same method as the first base material 3A with wiring, and the through electrode 44 is formed. Furthermore, a circuit pattern (second interlayer wiring portion) 45 </ b> A is formed on the other surface of the insulating base material 41. That is, in the second base material 3B with wiring, for example, a circuit pattern (first interlayer wiring portion) 42A is formed on one surface of an insulating base material 41 made of polyimide, and a circuit pattern (second wiring) is formed on the other surface. Interlayer wiring portion) 45A is formed, and via holes are formed in the portions where these circuit patterns (first interlayer wiring portions) 42A and circuit patterns 45A overlap with insulating base material 41 interposed therebetween, and conductive paste is printed in the via holes. The through electrode 44 is formed by filling. Then, the through electrode 38 of the first base material 3A with wiring and the circuit pattern (first interlayer wiring portion) 42A of the second base material 3B with wiring are electrically connected.

さらに、図４（ｂ）に示すように、配線付き第２基材３Ｂの回路パターン（第２層間配線部）４５Ａ側に、配線付き第３基材３Ｃを配置する。配線付き第３基材３Ｃは、配線付き第１基材３Ａと同様の方法によって製造され、絶縁基材５１の一方の面に回路パターン（第３配線部）５２Ａを形成すると共に、貫通電極５６を有し、絶縁基材５１の他方の面に接着層５３を形成する。そして、接着層５３を配線付き第２基材３Ｂの回路パターン（第２層間配線部）４５Ａ側に向け、この回路パターン（第２層間配線部）４５Ａと、配線付き第３基材３Ｃの貫通電極５６とを電気的に接続する。   Further, as shown in FIG. 4B, the third base material 3C with wiring is arranged on the circuit pattern (second interlayer wiring portion) 45A side of the second base material 3B with wiring. The 3rd base material 3C with wiring is manufactured by the same method as 3A of 1st base materials with wiring, and while forming the circuit pattern (3rd wiring part) 52A in one surface of the insulating base material 51, the penetration electrode 56 The adhesive layer 53 is formed on the other surface of the insulating base 51. Then, the adhesive layer 53 is directed toward the circuit pattern (second interlayer wiring portion) 45A side of the second base material 3B with wiring, and the circuit pattern (second interlayer wiring portion) 45A and the third base material 3C with wiring penetrate. The electrode 56 is electrically connected.

このように、配線付き第１基材３Ａの接着層３３側に、配線付き第２基材３Ｂ及び配線付き第３基材３Ｃを順次配置した後、位置合わせパターン（図示せず）を利用して位置合わせを行い、加熱することで仮留めする。
その後、図４（ｂ）に示すように、接着層３３，５３からなる層間接着材４は、加熱圧着時にフローして、配線付き第１基材３Ａと配線付き第２基材３Ｂとの間、配線付き第２基材３Ｂと配線付き第３基材３Ｃとの間、及び集積回路チップ２と配線付き第３基材３Ｃとの間にそれぞれ生じた隙間を充填する。これにより、集積回路チップ２は多層配線基板３内に固着・封入される。また、集積回路チップ２に接触する層間接着材４（３３，５３）の適度な弾性により、集積回路チップ２に対して周囲の材料から及ぼされる熱応力などを緩和する作用が生じる。 As described above, after the second base material 3B with wiring and the third base material 3C with wiring are sequentially arranged on the adhesive layer 33 side of the first base material 3A with wiring, an alignment pattern (not shown) is used. And then temporarily fix it by heating.
Thereafter, as shown in FIG. 4 (b), the interlayer adhesive 4 composed of the adhesive layers 33 and 53 flows during the thermocompression bonding, and between the first base material 3A with wiring and the second base material 3B with wiring. The gaps generated between the second substrate with wiring 3B and the third substrate with wiring 3C and between the integrated circuit chip 2 and the third substrate with wiring 3C are filled. As a result, the integrated circuit chip 2 is fixed and enclosed in the multilayer wiring board 3. In addition, the moderate elasticity of the interlayer adhesive 4 (33, 53) in contact with the integrated circuit chip 2 causes an effect of relaxing the thermal stress exerted on the integrated circuit chip 2 from surrounding materials.

そして、配線付き第３基材３Ｃの回路パターン（第３配線部）５２Ａ上に、半田ペーストをパターン印刷し、リフローすることによりボール状に形成した半田バンプ６を設けると共に、第１基材３Ａの開口部３９より露呈する集積回路チップ２の特定領域αに形成された第１配線部２５Ａに、半田バンプ５を介して半導体センサチップ１を実装することで、図１に示す半導体センサ装置１０を製造することができる。   Then, on the circuit pattern (third wiring portion) 52A of the third base material 3C with wiring, a solder paste 6 formed in a ball shape by pattern printing of solder paste and reflow is provided, and the first base material 3A. The semiconductor sensor device 10 shown in FIG. 1 is mounted by mounting the semiconductor sensor chip 1 via the solder bumps 5 on the first wiring portion 25A formed in the specific region α of the integrated circuit chip 2 exposed from the opening 39. Can be manufactured.

なお、本発明においては、半導体圧力センサといった半導体センサチップ以外の他のチップ部品の実装において同様に、配線基板との線膨張率差により特性が変動する場合に、この特性の悪化を防ぐことができる。   In the present invention, similarly to the mounting of other chip components other than the semiconductor sensor chip such as the semiconductor pressure sensor, when the characteristics fluctuate due to the difference in linear expansion coefficient with the wiring board, it is possible to prevent the deterioration of the characteristics. it can.

本発明に係る半導体センサ装置は、携帯電話機や、携帯用パーソナルコンピュータといった携帯電子機器など各種の電子機器の製造分野で利用することが可能である。   The semiconductor sensor device according to the present invention can be used in the field of manufacturing various electronic devices such as portable telephones and portable electronic devices such as portable personal computers.

α 特定領域、１ 半導体センサチップ、２ 集積回路チップ、３ 多層配線基板、３Ａ 配線付き第１基材、３Ｂ 配線付き第２基材、３Ｃ 配線付き第３基材、４ 層間接着材、５，６ 半田バンプ、１０ 半導体センサ装置、２１ 半導体基板、２２ パッド、２３ 絶縁層、２４ コンタクトホール、２５ 導電層、２５Ａ 第１配線部、２５Ｂ 他の第１配線部、３１ 絶縁基材、３２ 導電層、３２Ａ 第２配線部、３３ 接着層、３４ 樹脂フィルム、３５ ビアホール、３７ 貫通電極、３８ 他の貫通電極（層間第１貫通電極）、３９ 開口部、４１ 絶縁基材、４２Ａ 第１層間配線部、４４ 他の貫通電極（層間第２貫通電極）、４５Ａ 第２層間配線部、５１ 絶縁基材、５２Ａ 第３配線部、５３ 接着層、５６ 他の貫通電極（層間第３貫通電極）。   α specific region, 1 semiconductor sensor chip, 2 integrated circuit chip, 3 multilayer wiring board, 3A first substrate with wiring, 3B second substrate with wiring, 3C third substrate with wiring, 4 interlayer adhesive, 5, 6 Solder bump, 10 Semiconductor sensor device, 21 Semiconductor substrate, 22 Pad, 23 Insulating layer, 24 Contact hole, 25 Conductive layer, 25A First wiring part, 25B Other first wiring part, 31 Insulating substrate, 32 Conductive layer , 32A second wiring part, 33 adhesive layer, 34 resin film, 35 via hole, 37 through electrode, 38 other through electrode (interlayer first through electrode), 39 opening, 41 insulating substrate, 42A first interlayer wiring part , 44 Other through electrode (second interlayer through electrode), 45A Second interlayer wiring portion, 51 Insulating substrate, 52A Third wiring portion, 53 Adhesive layer, 56 Other through electrode (interlayer third) Through electrode).

Claims (4)

多層配線基板と、
前記多層配線基板の内部に埋設されると共に、該多層配線基板に設けた開口部により、特定領域が外部へ露呈された一面を有する集積回路チップと、
前記集積回路チップの特定領域内に配される第１配線部を介して電気的に接続され、かつ、該接続に要する部位により支持されている半導体センサチップと、
を少なくとも備えたことを特徴とする半導体センサ装置。 A multilayer wiring board;
An integrated circuit chip embedded in the multilayer wiring board and having a surface in which a specific region is exposed to the outside by an opening provided in the multilayer wiring board;
A semiconductor sensor chip that is electrically connected via a first wiring portion disposed in a specific region of the integrated circuit chip and supported by a portion required for the connection;
A semiconductor sensor device comprising: 前記接続に要する部位が半田バンプであることを特徴とする請求項１に記載の半導体センサ装置。   The semiconductor sensor device according to claim 1, wherein a part required for the connection is a solder bump. 前記多層配線基板は、前記半導体センサチップが配置された側に位置する一面に第２配線部、および、該第２配線部と前記第１配線部とを電気的に接続する貫通電極、を備えていることを特徴とする請求項１又は２に記載の半導体センサ装置。   The multilayer wiring board includes a second wiring portion on one surface located on the side where the semiconductor sensor chip is disposed, and a through electrode that electrically connects the second wiring portion and the first wiring portion. The semiconductor sensor device according to claim 1, wherein the semiconductor sensor device is provided. 前記多層配線基板は、前記一面の反対側に位置する他面に第３配線部、および、該第３配線部と前記第２配線部とを電気的に接続する他の貫通電極、を備えていることを特徴とする請求項１乃至３のいずれか１項に記載の半導体センサ装置。   The multilayer wiring board includes a third wiring portion and another through electrode that electrically connects the third wiring portion and the second wiring portion on the other surface located on the opposite side of the one surface. The semiconductor sensor device according to claim 1, wherein the semiconductor sensor device is a semiconductor sensor device.
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