JP2010282492A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a writing speed when writing information of a plurality of bits in a memory cell. <P>SOLUTION: A memory system 10 includes first and second channels each including non-volatile memories 21-0, 21-1 and memory interfaces 15-0, 15-1 for accessing the non-volatile memories 21-0, 21-1, respectively. Each of the non-volatile memories 21-0, 21-1 includes a plurality of pages each of which is composed of a plurality of memory cells, and each memory cell can store N bits (N is a natural number of ≥2). Further, the memory system 10 includes a control unit 12 which performs writing operation of N pages having different writing times, respectively, when writing N bits in each of the memory cells and switches the channels in each writing operation of N pages. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory system, for example, a memory system including an electrically rewritable flash memory.

  As a nonvolatile semiconductor memory, a NAND flash memory which is a kind of EEPROM (Electrically Erasable Programmable Read Only Memory) that electrically writes and erases data is known.

  A memory cell used in a NAND flash memory has a stacked gate structure in which a floating gate electrode, an intergate insulating film, and a control gate electrode are stacked in this order on a semiconductor substrate via a tunnel insulating film. is doing. Then, information is written into the memory cell by injecting electrons into the floating gate electrode or emitting electrons from the floating gate electrode. Furthermore, in order to realize large capacity and low cost, NAND flash memory (multi-value flash memory) using multi-value technology for storing data of 2 bits or more in one memory cell has been developed. Yes.

  In order to realize a multi-level flash memory, it is necessary to subdivide the threshold voltage distribution of the memory cells. For this reason, in data writing, since the control of the voltage applied to the memory cell becomes complicated, the writing time becomes long. For this reason, since the waiting time becomes long when data is written, the writing speed is lowered.

  When one page of data is recorded in the first flash memory and the writing wait state is entered, the next one page of data is immediately recorded in another second flash memory, thereby reducing the writing time. A technique for shortening is disclosed (see Patent Document 1).

JP 2002-366430 A

  The present invention provides a memory system capable of increasing the writing speed when writing multiple bits of information in a memory cell.

  The memory system according to an aspect of the present invention each includes a nonvolatile memory and a memory interface that accesses the nonvolatile memory, and the nonvolatile memory includes a plurality of pages each including a plurality of memory cells, Each memory cell can store N bits (N is a natural number greater than or equal to 2). The first and second channels perform a write operation of N pages with different write times when writing N bits to the memory cell. And a controller that switches channels for every N-page write operation.

  A memory system according to an aspect of the present invention includes a nonvolatile memory having first and second chips and a memory interface for accessing the nonvolatile memory, and each of the first and second chips. Includes a plurality of pages each consisting of a plurality of memory cells, each memory cell being capable of storing N bits (N is a natural number greater than or equal to 2), first and second channels, and N bits in the memory cells A controller that performs a write operation of N pages having different write times when writing, and switches a channel and a chip for each N page write operation.

  According to the present invention, it is possible to provide a memory system capable of increasing the writing speed when writing information of a plurality of bits into a memory cell.

1 is a block diagram showing a configuration of a memory system 10 according to an embodiment of the present invention. The block diagram which shows the structure of two channels. The circuit diagram which shows the structure of one block. The figure explaining the relationship between threshold distribution of memory cells and data. 5 is a flowchart showing a write operation of the memory system 10. 4 is a timing chart showing a write operation of the memory system 10.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  FIG. 1 is a block diagram showing a configuration of a memory system 10 according to an embodiment of the present invention. The memory system 10 includes a plurality of NAND flash memories 21 and a memory controller 11 that controls them. In the present embodiment, the case where the memory system 10 includes two NAND flash memories 21-0 and 21-1 will be described as an example. However, the number of NAND flash memories may be two or more. .

  The memory controller 11 includes a control unit (CPU: Central Processing Unit) 12, a ROM (Read Only Memory) 13, a RAM (Random Access Memory) 14, a plurality of NAND interfaces 15, a host interface 16, and a GPIO (General Purpose Input / These modules are connected via a system bus 18.

  The host interface 16 is composed of, for example, a USB (Universal Serial Bus) interface, and controls data transmission / reception with the host based on the USB standard which is a data transfer standard.

  The CPU 12 controls the overall operation of the memory system 10. For example, when the memory system 10 is supplied with power, the CPU 12 controls various operations of the memory system 10 using firmware (FW) stored in the ROM 13 or the NAND flash memory 21. In addition, the CPU 12 receives a write command, a read command, and an erase command from the host, and controls write, read, and erase operations on the NAND flash memory 21.

  The ROM 13 stores firmware (software) necessary for controlling various operations of the memory system 10. The RAM 14 is used as a work area for the CPU 12 and temporarily stores data and various tables. The GPIO 17 is an input / output port and performs input / output control of a module connected to the GPIO 17.

  The NAND interfaces 15 are arranged in the same number as the NAND flash memories 21. Therefore, in the present embodiment, the two NAND interfaces 15-0 corresponding to the two NAND flash memories 21-0 and 21-1. 15-1 are arranged. The NAND interface 15-0 executes interface processing with the NAND flash memory 21-0. Similarly, the NAND interface 15-1 executes interface processing with the NAND flash memory 21-1.

  FIG. 2 is a block diagram showing the configuration of two channels. The memory system 10 includes two channels (channel 0 and channel 1) for performing data transfer. A “channel” is a path for transferring data, and refers to a circuit portion having a function of transferring data by connecting a CPU and a storage device. In the present embodiment, the first channel 0 includes a NAND flash memory 21-0 and a NAND interface 15-0 that controls the NAND flash memory 21-0, and the second channel 1 includes a NAND flash memory 21-1, And a NAND interface 15-1 for controlling the same. The CPU 12 can write, read, and erase data independently for the two channels (channel 0 and channel 1).

  Next, the configuration of the NAND flash memory 21 will be described. Each NAND flash memory 21 includes two chips (chip 0 and chip 1). The number of chips included in one NAND flash memory 21 is not particularly limited, and may be one or two or more.

  Each chip includes a plurality of blocks which are data erasing units. Each block includes a plurality of memory cells arranged in a matrix and is composed of a plurality of pages which are units for data writing and reading.

  Each NAND flash memory 21 includes a peripheral circuit that performs data write, read, and erase processing on the memory cell array in addition to the memory cell array described above. Specifically, the NAND flash memory 21 holds a column decoder for selecting a column of the memory cell array, a row decoder for selecting a row of the memory cell array, a sense amplifier circuit for reading data from the memory cell, and read and write data. Including data cache.

  FIG. 3 is a circuit diagram showing the configuration of one block. Each block includes (n + 1) NAND strings corresponding to the number of bit lines BL0 to BLn. “N” is a natural number of 0 or more. The select transistors ST1 included in each of the plurality of NAND strings have their drains connected to the bit line BL and their gates commonly connected to the select gate line SGD. In addition, the selection transistors ST2 included in each of the plurality of NAND strings have their sources commonly connected to the source line SL and their gates commonly connected to the selection gate line SGS.

  In each NAND string, current paths of (m + 1) memory cells MC corresponding to the number of word lines WL0 to WLm are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. Are arranged as follows. That is, (m + 1) memory cells MC are connected in series in the column direction so that adjacent memory cells share a diffusion region (source region or drain region).

  The control gate electrodes are connected to the word lines WL0 to WLm in order from the memory cell MC located closest to the drain side. Therefore, the drain of the memory cell MC connected to the word line WL0 is connected to the source of the selection transistor ST1, and the source of the memory cell MC connected to the word line WLm is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLm connect the control gate electrodes of the memory cells MC in common between the NAND strings in the block. That is, the control gate electrodes of the memory cells MC in the same row in the block are connected to the same word line WL. The (n + 1) memory cells MC connected to the same word line WL are handled as a page.

  In addition, the bit line BL commonly connects the drains of the selection transistors ST1 between the blocks. That is, NAND strings in the same column in a plurality of blocks are connected to the same bit line BL.

  Each memory cell is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a P-type well. The stacked gate structure is configured by sequentially stacking a tunnel insulating film, a charge storage layer (floating gate electrode), an inter-gate insulating film, and a control gate electrode on a P-type well. In the memory cell, the threshold voltage changes according to the number of electrons accumulated in the floating gate electrode, and data is recorded according to the difference in threshold voltage. The memory cell subdivides the threshold voltage distribution and stores multi-value data of 2 bits or more. Therefore, in FIG. 3, one row connected to the common word line WL corresponds to two pages (lower page and upper page). In this embodiment, the case where the memory cell stores 2 bits is described as an example. However, the present invention is not limited to this, and the memory cell and its peripheral circuit are configured to store 3 bits or more. Also good.

  FIG. 4 is a diagram for explaining the relationship between the threshold distribution of memory cells and data. The horizontal axis of FIG. 4 indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (cell number). When writing 2-bit data to the memory cell, lower page writing for writing lower bit data and upper page writing for writing upper bits are performed.

  When data in the memory cell is erased, the memory cell is set to the “A” level (erased state) threshold voltage. For example, the “A” level in the erased state is set to the negative side.

  By performing the lower page write in the first stage, “1” data whose threshold voltage is “A” level (erased state) and “0” data whose “M” level is higher than “A” level. Either of them can be stored in the memory cell. In the case of “1” data, the threshold voltage of the memory cell is not shifted. In the case of “0” data, the threshold voltage of the memory cell is shifted to the positive side. “0” data is written using the verify voltage Vm.

  Subsequently, the upper page is written in the second stage, so that the memory cell stores any one of the four data of “11” data, “01” data, “00” data, and “10” data. Can do. “11” data has a threshold voltage “A” level (erased state), “01” data has a threshold voltage “B” level, “00” data has a threshold voltage “C” level, and “10” data has a threshold voltage. Is set to the “D” level. The relationship between the threshold voltages A to D is A <B <C <D <Vread. In the case of “11” data, the threshold voltage of the memory cell is not shifted. The “01” data is written using the verify voltage Vb. “00” data is written using a verify voltage Vc higher than Vb. "10" data is written using a verify voltage Vd higher than Vc. Note that the assignment between the threshold voltage and the data can be arbitrarily set.

  Here, in the multilevel memory, it is necessary to accurately control the threshold voltage of the memory cell in accordance with the write data. When writing to a memory cell, there is a concern of overprogramming exceeding the level, so there is a step-up writing method that repeats the write operation with the write voltage raised gradually and the verify operation to check the threshold voltage many times. Used.

  Specifically, in the lower page writing, first, the lower page data is input from the outside. Then, a write voltage is applied to the memory cell so that a threshold voltage corresponding to data is obtained. Thereafter, verification is performed to confirm whether the memory cell has a correct threshold voltage. As long as there are memory cells in the page that are not at the correct threshold voltage, the operation of applying the write voltage while gradually increasing the voltage and the verification to confirm whether the memory cell has the correct threshold voltage are repeated. Done.

  On the other hand, in the upper page write, before the upper page data is written, an internal data load for examining the lower page data stored in the memory cell is performed. Thereafter, similarly to the writing of the lower page, the operation of applying the writing voltage while gradually increasing the voltage and the verification for confirming whether the memory cell has the correct threshold voltage are repeatedly performed.

  As described above, the writing of the upper page is more complicated than the writing of the lower page, so that the writing time becomes longer. For example, the writing time of the upper page is about three times or more than the writing time of the lower page.

  Thus, in the memory system 10 in which two types of write operations having different write times, that is, a high-speed write operation (lower page write operation) and a low-speed write operation (upper page write operation) are mixed, Latency increases because busy time increases. Therefore, in this embodiment, the busy time is virtually reduced by adopting an interleaving method using a plurality of channels.

(Operation)
Hereinafter, a write operation of the memory system 10 configured as described above will be described. FIG. 5 is a flowchart showing a write operation of the memory system 10. In FIG. 5, the left box column shows the state of the NAND flash memory 21-0 of channel 0, and the right box column shows the state of the NAND flash memory 21-1 of channel 1. For example, four squares of chip 0 of channel 0 correspond to a first lower page, a first upper page, a second lower page, and a second upper page in order from the top. Steps progress toward the bottom of FIG. 5, and a total of five steps are shown. An arrow in the chip represents a page on which a write operation is performed in the step. Diagonal lines in the chip represent written pages.

  First, the CPU 12 performs a lower page and upper page write operation on channel 0 and chip 0 (step S100). Subsequently, the CPU 12 switches the channel and the chip, and executes the lower page and upper page write operations for the channel 1 and chip 0 (step S101). Subsequently, the CPU 12 switches the channel and the chip, and executes the lower page and upper page write operations for the channel 0 and the chip 1 (step S102). Subsequently, the CPU 12 switches the channel and the chip, and executes the lower page and upper page write operations for the channel 1 and chip 1 (step S103). Subsequently, the CPU 12 returns to the beginning and executes the lower page and upper page write operations for channel 0 and chip 0 (step S104).

  In this way, the CPU 12 writes the lower page and the upper page as a set, and writes in the order of channel 0, chip 0 → channel 1, chip 0 → channel 0, chip 1 → channel 1, chip 1 → channel 0, chip 0. Perform the action. That is, the CPU 12 sequentially switches channels and chips each time two pages of data are input from the host. When the channel and chip switching is completed, the write operation is executed in the same order as described above for the data of two pages input thereafter.

  FIG. 6 is a timing chart showing the write operation of the memory system 10. Data is sequentially input from the host to the memory system 10. First, the CPU 12 executes data input (Data In) and a lower page write operation for channel 0 and chip 0. Specifically, the CPU 12 selects channel 0 and chip 0 and inputs one page of data to chip 0 of channel 0. In response, the NAND flash memory 21-0 writes this data to the lower page of the chip 0. During data writing, the NAND flash memory 21-0 activates the busy signal. As shown in FIG. 6, the busy time “busy time (Lower)” due to the write operation of the lower page is shortened. When the writing of the lower page is completed, the NAND flash memory 21-0 releases the busy state.

  Subsequently, after waiting for the busy state to be released, the CPU 12 executes data input and upper page write operation for channel 0 and chip 0. Specifically, the CPU 12 selects channel 0 and chip 0, and inputs data for one page to chip 0 of channel 0. In response to this, the NAND flash memory 21-0 writes this data to the upper page of the chip 0. As shown in FIG. 6, the busy time “busy time (Upper)” due to the upper page write operation is longer than the busy time “busy time (Lower)”.

  During the busy period of channel 0 and chip 0 (during upper page writing), the CPU 12 executes data input and lower page write operation for channel 1 and chip 0. Subsequently, after waiting for the busy state to be released, the CPU 12 executes data input and upper page write operation for channel 1 and chip 0.

  During the busy period of channel 1 and chip 0 (during upper page writing), the CPU 12 performs data input and lower page write operation for channel 0 and chip 1. Subsequently, after waiting for the busy state to be released, the CPU 12 executes data input and upper page write operation for channel 0 and chip 1.

  During the busy period of channel 0 and chip 1 (during upper page writing), the CPU 12 executes data input and lower page write operation for channel 1 and chip 1. Subsequently, after waiting for the busy state to be released, the CPU 12 executes data input and upper page write operation for channel 1 and chip 1.

  Thereafter, since the busy of the channel 0 and the chip 0 is released by the NAND flash memory 21-0, the CPU 12 subsequently executes the lower page and upper page write operations for the channel 0 and the chip 0. . Thereafter, these interleaving operations are repeated.

  As described above in detail, in the present embodiment, the memory system 10 includes two channels (channel 0 and channel 1), and a write operation is performed on these two channels using an interleave method. At this time, the two channels are sequentially switched in units of write operations for the lower page and the upper page.

  Further, the NAND flash memory 21 included in each channel includes two chips, and a write operation is performed on these two chips using an interleave method. At this time, two channels and two chips are sequentially switched in units of write operations for the lower page and the upper page.

  Therefore, according to the present embodiment, the busy time can be virtually reduced by starting the write access to another channel during the upper page write operation with a long write time. As a result, the latency of the entire NAND flash memory can be shortened, and as a result, the writing speed can be improved.

  In this embodiment, a configuration example of the memory system 10 including two channels and two chips is shown, but the number of channels may be two or more, and the number of chips is one. It may be individual or two or more. By setting the number of channels and chips optimally according to the upper page write time, it becomes possible to further reduce the latency in the entire NAND flash memory.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the components without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

  BL ... bit line, WL ... word line, SL ... source line, SGD, SGS ... selection gate line, MC ... memory cell, ST ... select transistor, 10 ... memory system, 11 ... memory controller, 12 ... CPU, 13 ... ROM , 14 ... RAM, 15 ... NAND interface, 16 ... host interface, 17 ... GPIO, 18 ... system bus, 21 ... NAND flash memory.

Claims (5)

Each includes a non-volatile memory and a memory interface for accessing the non-volatile memory, the non-volatile memory including a plurality of pages each consisting of a plurality of memory cells, each memory cell having N bits (N is 2 or more) First and second channels capable of storing a natural number of
A controller that performs N page write operations with different write times when N bits are written to a memory cell, and switches the channel for each N page write operation;
A memory system comprising: Each includes a non-volatile memory having first and second chips and a memory interface for accessing the non-volatile memory, and each of the first and second chips includes a plurality of memory cells. A first channel and a second channel each including a page, each memory cell being capable of storing N bits (N is a natural number greater than or equal to 2);
A controller that performs N page write operations with different write times when N bits are written to a memory cell, and switches a channel and a chip for each N page write operation;
A memory system comprising: The N page includes first and second pages,
3. The memory system according to claim 1, wherein the N bits are 2 bits.   The memory system according to claim 3, wherein a write time of the second page is longer than that of the first page.   5. The memory system according to claim 1, wherein the nonvolatile memory is a NAND flash memory.

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