JP2010276374A - Power supply apparatus for device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply apparatus for device which can shorten a test time without increasing a mounting area at relatively low costs. <P>SOLUTION: In the power supply apparatus for device in a semiconductor test apparatus in which a digital circuit area and an analog circuit area are insulation coupled via an insulation coupling element and the analog circuit area supplies power to a test object on the basis of the control of the digital circuit area, and which includes the function of monitoring the variation of the power supplied to the test object, a cache buffer storing a command for controlling the analog circuit area is provided in a space to the insulation coupling element in the digital circuit area. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power supply device for a device used in a semiconductor test apparatus, and more particularly to shortening a test time.

  FIG. 4 is a configuration diagram illustrating an example of a conventional device power supply device. In the device power supply device shown in FIG. 4, the digital circuit area D and the analog circuit area A are separately formed. In the digital circuit area D and the analog circuit area A, noise in the digital circuit area D does not propagate to the analog circuit area A. In this way, the insulating coupling elements IR1 and IR2 such as a photocoupler and a GMR (Giant Magneto Resistance) isolator are insulatively coupled.

  The digital circuit area D has a function of controlling the analog circuit area A by outputting setting commands and measurement commands to the analog circuit area A, and is provided with a CPU 1 and a memory 2.

  The analog circuit area A has a function of supplying a predetermined power to the test target DUT based on the control of the digital circuit area D and monitoring fluctuations in voltage and current supplied to the test target DUT.

  A setting command buffer 3 and a measurement command buffer 4 are connected to the insulating coupling element IR1. A setting command control unit 5 is connected to the setting command buffer 3, and a DAC control unit 6, a relay control unit 7, and a timer 8 are connected to the setting command control unit 5.

  The DAC control unit 6 controls the D / A converter 9 so as to supply predetermined power to the test target DUT, and the relay control unit 7 selectively supplies the output signal of the D / A converter 9 to the test target DUT. Then, the relay 10 is controlled.

  A measurement command control unit 11 is connected to the measurement command buffer 4, and an ADC control unit 12 and a timer 13 are connected to the measurement command control unit 11. The measurement command control unit 11 and the setting command control unit 5 are connected so as to exchange signals with each other.

  The ADC control unit 12 controls the A / D converter 14 so as to monitor the power supplied from the D / A converter 9 via the relay 10 to the test DUT, and the output data of the A / D converter 14 Are sequentially stored in the measurement data buffer 15. The D / A converter 9, the relay 10, the test object DUT, and the A / D converter 14 constitute an analog circuit AC.

  The measurement data sequentially stored in the measurement data buffer 15 is transmitted to the digital circuit area D via the insulating coupling element IR2 and stored in the memory 2 via the CPU1.

A procedure for controlling the analog circuit AC in such a configuration will be described.
(1) Based on the operation procedure programmed by the user, various commands for controlling the analog circuit AC are stored in the memory 2 via the CPU 1.
(2) The CPU 1 reads the following commands from these commands stored in the memory 2 and stores them in the setting command buffer 3 via the insulating coupling element IR1.
1) DAC setting command: Outputs the voltage V1 from the D / A converter 9. 2) Wait command: Waits for time T1. 3) Relay setting command: Turns on the relay.

  Since the DAC setting command is a command to be executed first, a flag (trigger synchronization flag) indicating execution by a trigger input is added.

Since the transfer speed of the insulating coupling element IR1 is lower than the processing speed of the CPU 1, the CPU 1 cannot transfer the next command data until the data transfer to the command buffer (not shown) in the analog circuit AC is completed.
(3) When data is written to the setting command buffer 3, the setting command control unit 5 reads the command data from the setting command buffer 3, interprets the command data, and determines that it is a DAC setting command. In accordance with the trigger synchronization flag added to the DAC setting command, it waits for notification of a trigger.

(4) Next, the CPU 1 accesses an internal trigger output register (setting) (not shown) and outputs a trigger to the setting command control unit.
(5) When receiving the trigger, the setting command control unit 5 sequentially executes the commands stored in the setting command buffer 3 to change the state of the analog circuit AC.

  Patent Document 1 describes a power supply device for a device that can shorten measurement time and perform accurate calibration.

JP 2008-76104 A

  However, according to the conventional configuration, the operation speed of the insulating coupling element provided as an interface between the digital circuit area D and the analog circuit area A is slow, and a command is written from the digital circuit area D to the analog circuit area A. It takes a long time, and there is a problem that the test time becomes slow.

  In particular, in the case of a multi-channel measurement module configuration, since it is necessary to sequentially write to the command buffer, much more time is consumed.

  In addition, in order to shorten the processing time at the interface, a method of passing signals in parallel using a plurality of isolators can be considered, but there are new problems that the number of isolators increases, the cost increases and the mounting area increases. Come out.

  These problems cannot be overlooked in device power supply modules and DC source major modules that require multiple channels.

  The present invention solves these problems, and an object of the present invention is to provide a device power supply apparatus that can reduce test time without increasing the mounting area at a relatively low cost.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A digital circuit area and an analog circuit area are insulatively coupled via an insulative coupling element, and the analog circuit area supplies a predetermined power to the test object based on the control of the digital circuit area and also supplies the power to the test object In a device power supply device in a semiconductor test apparatus having a function of monitoring fluctuations in
A cache buffer for storing a command for controlling the analog circuit area is provided between the digital circuit area and the insulating coupling element.

The invention according to claim 2 is the device power supply device according to claim 1,
The cache buffer is composed of a FIFO.

The invention according to claim 3 is the device power supply device according to claim 1 or 2,
It is characterized in that an interrupt function for notifying the execution of the command from the analog circuit area to the digital circuit area by an interrupt via an insulating coupling element is added.

Invention of Claim 4 is the power supply device for devices in any one of Claims 1-3,
It is characterized in that an interrupt function for notifying the execution of the command from the analog circuit area to the digital circuit area by an interrupt via an insulating coupling element is added.

  According to the present invention, it is possible to realize a device power supply device in a semiconductor test apparatus that can reduce the test time at a relatively low cost without increasing the mounting area.

It is a block diagram which shows one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows an example of the conventional power supply device for devices.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals are given to portions common to FIG. The difference between FIG. 1 and FIG. 4 is that a cache buffer 16 composed of FIFO is provided between the CPU 1 and the insulating coupling element IR1 in the digital circuit area D in the configuration of FIG.

A procedure for controlling the analog circuit AC in the configuration of FIG. 1 will be described.
(1) Based on the operation procedure programmed by the user, various commands for controlling the analog circuit AC are stored in the memory 2 via the CPU 1.
(2) The CPU 1 reads the following commands from these commands stored in the memory 2 and stores them in the cache buffer 16.
1) DAC setting command: Outputs the voltage V1 from the D / A converter 9. 2) Wait command: Waits for time T1. 3) Relay setting command: Turns on the relay.

  Also in the configuration of FIG. 1, since the DAC setting command is the command to be executed first, a flag (trigger synchronization flag) indicating execution by a trigger input is added.

(3) The cache buffer 16 has a FIFO structure, and sequentially reads stored commands and stores them in the setting command buffer 3 via the insulating coupling element IR1.
(4) When data is written to the setting command buffer 3, the setting command control unit 5 reads the command data from the setting command buffer 3, interprets the command data, and determines that it is a DAC setting command. It waits for notification of a trigger in accordance with the trigger synchronization flag added to the DAC setting command.

(5) Next, the CPU 1 accesses an internal trigger output register (setting) (not shown) and outputs a trigger to the setting command control unit.
(6) When receiving the trigger, the setting command control unit 5 sequentially executes the commands stored in the setting command buffer 3 to change the state of the analog circuit AC.

  With this configuration, even when the operation speed of the insulating coupling element IR1 that insulates and couples the digital circuit area D and the analog circuit area A is low, the command read from the CPU 1 can be written to the setting command buffer 3 at high speed. .

  Even in a measurement module with a multi-channel configuration, the write data for each channel is temporarily stored in the cache buffer 16, so that multiple channels can be simultaneously written to the command buffer, substantially reducing the command write time. As a result, the test time can be greatly reduced.

  In addition, since it is not necessary to use a plurality of isolators for the purpose of shortening the processing time in the interface, the number of isolators is not increased, the cost can be reduced, and an increase in mounting area can be suppressed.

  In particular, a great effect can be expected in improving the test time in a device power supply module or a DC source major module that requires multiple channels.

  FIG. 2 is a block diagram showing another embodiment of the present invention. In the digital circuit area D, a plurality of N-channel analog circuit areas A1 to AN having the same configuration are respectively provided with insulating coupling elements IR11 to IR1N, IR21 to IR. Insulatingly coupled via IR2N.

  A plurality of N-channel cache buffers 161 to 16N are provided between the CPU 1 in the digital circuit area D and the insulating coupling elements IR11 to IR1N so as to correspond to the plurality of N-channel analog circuit areas A1 to AN.

  In FIG. 2, when one CPU 1 executes the same processing for the analog circuits AC1 to ACN of a plurality of N channels, by performing broadcast writing that simultaneously performs write access to the cache buffers 161 to 16N of each channel, Commands can be stored in the command buffers of AC1 to ACN in the analog circuit in parallel in the analog circuit areas A1 to AN of a plurality of N channels.

  On the other hand, when different processing is executed for the analog circuits AC1 to ACN of a plurality of N channels by one CPU 1, commands are sequentially written into the cache buffers 161 to 16N of the respective channels at the speed of the CPU 1.

  Specifically, while all the commands are stored in the cache buffer of the previous channel and the commands are stored in the cache buffer of the subsequent channel, the cache buffer of the previous channel is transferred to the command buffer via the insulating coupling element. Transfer data.

  Here, since the command data write speed to the cache buffer of the CPU is faster than the command data transfer speed of the insulation coupling element, the CPU can write the command without worrying about the transfer speed of the insulation coupling element. It is also possible to store commands and to perform other processing.

  FIG. 3 is a block diagram showing another embodiment of the present invention. The difference between FIG. 3 and FIG. 1 is that the command is executed from the setting command control unit 5 and the measurement command control unit 11 and the insulation coupling element IR1. This is the addition of an interrupt function for notifying the CPU 1 by means of an interrupt.

  This interrupt function allows the CPU 1 to know the command execution state without monitoring the full empty state of the cache buffer 16 and the full empty state of the command buffer by polling. By omitting the CPU 1 polling process, the CPU 1 Can be moved faster. Such an additional configuration of the interrupt function is also effective when a plurality of N-channel analog circuits AC1 to ACN are controlled by one CPU 1 as shown in FIG.

  As described above, according to the present invention, it is possible to realize a device power supply device in a semiconductor test apparatus that can reduce the test time at a relatively low cost without increasing the mounting area, and is effective in improving the test efficiency of the DUT. It is.

1 CPU
2 Memory 3 Setting Command Buffer 4 Measurement Command Buffer 5 Setting Command Control Unit 6 DAC Control Unit 7 Relay Control Unit 8, 13 Timer 9 D / A Converter 10 Relay 11 Measurement Command Control Unit 12 ADC Control Unit 14 A / D Converter 15 Measurement data buffer 16 Cache buffer A Analog circuit area D Digital circuit area AC Analog circuit DUT Measurement target IR Insulation coupling element

Claims (4)

A digital circuit area and an analog circuit area are insulatively coupled via an insulative coupling element, and the analog circuit area supplies a predetermined power to the test object based on the control of the digital circuit area, and also supplies power to the test object. In a device power supply device in a semiconductor test apparatus having a function of monitoring fluctuations in
A power supply device for a device, wherein a cache buffer for storing a command for controlling the analog circuit area is provided between the digital circuit area and an insulating coupling element.   2. The device power supply device according to claim 1, wherein the cache buffer is configured by a FIFO.   3. The device power supply apparatus according to claim 1, further comprising an interrupt function for notifying the digital circuit area that the command has been executed by an interrupt from the analog circuit area via an insulating coupling element.   4. The device according to claim 1, wherein a plurality of N-channel analog circuit areas having the same configuration are insulatively coupled to the digital circuit area via insulative coupling elements. 5. Power supply.

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