JP2010273215A - High frequency module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a harmonic signal radiated from a switch to the outside without increasing the insertion loss of a path of the output signal of a power amplifier. <P>SOLUTION: The high frequency module 2 includes the power amplifier 4 and the switch 6 to which the output signal of the power amplifier 4 is input. A power supply voltage input terminal 4VC of the power amplifier 4 and a power supply voltage input terminal 6VD of the switch 6 are both connected to a power supply terminal Vcc to form a harmonic signal transmission path 80 for transmitting a harmonic signal generated by the power amplifier 4 and leaking to the power supply voltage input terminal 4VC to the power supply voltage input terminal 6VD. The length of the harmonic signal transmission line 80 is adjusted to make the intensity of a harmonic signal, generated by putting together the harmonic signal transmitted to the power supply voltage input terminal 6VD through the harmonic signal transmission line 80 and the harmonic signal generated by the switch 6, smaller than the intensity of the harmonic signal generated by the switch 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a high frequency module including a power amplifier that amplifies a high frequency signal and a switch to which an output signal of the power amplifier is input.

  In recent years, wireless communication devices such as mobile phones that can support a plurality of frequency bands (multi-band) and a plurality of systems (multi-mode) and a communication device for a wireless LAN (local area network) that can support a plurality of frequency bands. It has been put into practical use. In a high-frequency circuit unit of a wireless communication device, a switch is widely used in order to share one antenna for a plurality of signals such as a transmission signal and a reception signal, or signals in a plurality of frequency bands. As a configuration for sharing one antenna with a plurality of signals, there is a configuration using a diplexer or a duplexer instead of a switch. Compared to a configuration using such a diplexer or duplexer, a configuration using a switch has an advantage that it can easily cope with an increase in the number of frequency bands by increasing the number of ports of the switch. As the switch, a switch composed of a semiconductor integrated circuit (hereinafter referred to as a semiconductor IC) including a field effect transistor (hereinafter referred to as an FET) is often used.

  In addition, in the high-frequency circuit unit, in a transmission circuit that processes a transmission signal, a power amplifier that amplifies the transmission signal is an essential component. As this power amplifier, one constituted by a semiconductor IC including a plurality of cascade-connected amplifiers is often used.

  For example, Patent Document 1 (particularly, FIG. 12) and Patent Document 2 (particularly, FIG. 6) are disclosed in, for example, Patent Document 1 (particularly FIG. 12) and Patent Document 2 (particularly FIG. 6). And Patent Document 3 (particularly FIG. 13). In a high-frequency circuit unit including such a switch and a power amplifier, the switch includes an antenna port connected to the antenna directly or via another circuit, and a plurality of selectively connected to the antenna port. Input / output ports. The output terminal of the power amplifier that amplifies the transmission signal is connected to one input / output port of the switch directly or through another circuit. Generally, as shown in Patent Documents 1 to 3, a low-pass filter or a band-pass filter is provided between the output terminal of the power amplifier and one input / output port of the switch.

  By the way, it is known that a power amplifier or a switch constituted by a semiconductor IC generates a harmonic signal when processing a high-power signal such as a transmission signal. The harmonic signal is a signal having a frequency that is an integer multiple of 2 or more of the frequency of the signal to be processed. In the wireless communication device, a means for attenuating the harmonic signal is required to prevent a large harmonic signal from being emitted from the antenna.

  As shown in Patent Documents 1 to 3, by providing a low-pass filter or a band-pass filter between the output terminal of the power amplifier and one input / output port of the switch, a harmonic signal generated by the power amplifier at the time of transmission is provided. Can be attenuated.

  On the other hand, the harmonic signal generated by the switch is output to each port of the switch. For this reason, in the configuration in which the antenna port of the switch is directly connected to the antenna, the harmonic signal generated by the switch and directed to the antenna cannot be attenuated unless any countermeasure is taken. Therefore, various techniques for attenuating the harmonic signal generated by the switch have been conventionally proposed as described below.

  In Patent Document 4, a filter circuit that passes a fundamental wave and reflects a harmonic component is provided between a switch and a transmission circuit, and a signal transmission line is provided between the switch and the filter circuit. Describes a technique that cancels the harmonic signal that is generated in the switch, reflected by the filter circuit, passes through the switch, and goes to the antenna, and the harmonic signal that goes directly from the switch to the antenna by controlling the length of the switch. ing.

  In Patent Document 5, between the transmission input port of the switch and the low-pass filter connected to the transmission input port, the harmonic impedance when the low-pass filter side is viewed from the transmission input port changes in a direction approaching zero. There is described a technique for suppressing harmonics directed to an antenna by providing a phase setting element to be generated and suppressing harmonics generated in a switch, reflected by a low-pass filter, and returning to the switch.

  Cited Document 6 describes a technique in which a filter that attenuates an unnecessary high-frequency signal is provided between a switch and an antenna.

JP 2003-243994 A JP-A-2005-64732 JP 2005-101893 A JP 2001-86026 A JP 2009-5399 A JP 2001-345729 A

  The technique described in Patent Document 4 has a problem that the insertion loss of the transmission signal path increases depending on the length of the signal transmission line provided between the switch and the filter circuit. Similarly, the technique described in Patent Document 5 has a problem in that the insertion loss of the transmission signal path increases depending on the length of the phase setting element.

  The technique described in Patent Document 6 can be used in a high-frequency circuit unit that supports only one frequency band, but cannot be used in a high-frequency circuit unit that can handle a plurality of frequency bands. is there.

  The present invention has been made in view of such a problem, and an object thereof is a high-frequency module including a power amplifier that amplifies a high-frequency signal and a switch to which an output signal of the power amplifier is input. It is an object of the present invention to provide a high frequency module capable of reducing harmonic signals emitted from a switch to the outside without increasing the insertion loss of the output signal path.

  The high-frequency module of the present invention includes a power supply terminal to which a power supply voltage is input, a power amplifier, and a switch. The power amplifier has a signal input terminal, a signal output terminal, and an amplifier power supply voltage input terminal connected to the power supply terminal, and operates by being supplied with the power supply voltage through the power supply terminal and the amplifier power supply voltage input terminal. The high frequency signal input to the signal input terminal is amplified and output from the signal output terminal. The switch includes three or more ports including a port to which a high frequency signal output from the signal output terminal of the power amplifier is input, a switch power supply voltage input terminal connected to the power supply terminal, and a control signal to which a control signal is input. Two input ports connected to each other in accordance with a control signal input to the control signal input terminal, which operates by supplying a power supply voltage via the power supply terminal and the switch power supply voltage input terminal. Switch. The high-frequency module further includes a transmission path formed between the amplifier power supply voltage input terminal and the switch power supply voltage input terminal by connecting both the amplifier power supply voltage input terminal and the switch power supply voltage input terminal to the power supply terminal. ing.

  In the high frequency module of the present invention, the transmission path may transmit a harmonic signal generated by the power amplifier and leaking to the amplifier power supply voltage input terminal to the switch power supply voltage input terminal.

  In the high-frequency module of the present invention, the switch further includes a logic circuit that operates when a power supply voltage is supplied and generates a plurality of signals for determining two ports to be connected based on a control signal. You may do it.

  In the high-frequency module of the present invention, the three or more ports of the switch include a first port and two or more second ports selectively connected to the first port, and a power amplifier The port to which the high-frequency signal output from the signal output terminal is input may be one of two or more second ports. In this case, the harmonic signal generated by the power amplifier and leaked to the amplifier power supply voltage input terminal and transmitted to the switch power supply voltage input terminal via the transmission path leaks to the first port and appears at the first port. The phase of the harmonic signal may be 180 ° different from the phase of the harmonic signal generated by the switch and appearing at the first port.

  The high frequency module of the present invention is further provided between the power amplifier and the switch in the path of the high frequency signal output from the signal output terminal of the power amplifier, and the high frequency module output from the signal output terminal of the power amplifier. A filter for attenuating the superimposed harmonic signal may be provided.

  The high-frequency module of the present invention further includes a laminated substrate including a plurality of laminated dielectric layers, the power amplifier and the switch are mounted on the laminated substrate, and the transmission path is disposed inside the laminated substrate. Good. In this case, the high-frequency module further includes a circuit disposed inside the multilayer substrate, and the multilayer substrate includes a first conductor layer constituting a part of the transmission path, and a circuit disposed inside the multilayer substrate. And a second conductor layer disposed between the first conductor layer and connected to the ground.

  The high frequency module of the present invention may further include a second power amplifier. The second power amplifier has a second signal input terminal, a second signal output terminal, and a second amplifier power supply voltage input terminal connected to the power supply terminal, and includes a power supply terminal and a second power supply. The power supply voltage is supplied through the voltage input terminal, and the second high-frequency signal input to the second signal input terminal is amplified and output from the second signal output terminal. In this case, the three or more ports of the switch include a port to which a high frequency signal output from the second signal output terminal of the second power amplifier is input. In this case, the high-frequency module further includes the second amplifier power supply voltage input terminal and the switch power supply voltage input terminal by connecting both the second amplifier power supply voltage input terminal and the switch power supply voltage input terminal to the power supply terminal. And a second transmission path formed between the two.

  The second transmission path may transmit a harmonic signal generated by the second power amplifier and leaking to the second amplifier power supply voltage input terminal to the switch power supply voltage input terminal. The three or more ports of the switch include a first port and two or more second ports selectively connected to the first port, and are output from the signal output terminal of the power amplifier. A port to which a high-frequency signal is input and a port to which a high-frequency signal output from the second signal output terminal of the second power amplifier is input may be included in two or more second ports. In this case, the harmonic signal generated by the power amplifier and leaked to the amplifier power supply voltage input terminal and transmitted to the switch power supply voltage input terminal via the transmission path leaks to the first port and appears at the first port. The phase of the harmonic signal may be 180 ° different from the phase of the harmonic signal generated by the switch and appearing at the first port when the high frequency signal output from the signal output terminal of the power amplifier is input to the switch. Good. Further, the harmonic signal generated by the second power amplifier and leaked to the second amplifier power supply voltage input terminal, and transmitted to the switch power supply voltage input terminal via the second transmission path leaks to the first port. Thus, the phase of the harmonic signal appearing at the first port is generated by the switch when the high frequency signal output from the second signal output terminal of the second power amplifier is input to the switch, and the first port May be 180 ° different from the phase of the harmonic signal appearing at.

  When the high-frequency module includes the second power amplifier, the high-frequency module is further provided in the path of the high-frequency signal output from the signal output terminal of the power amplifier between the power amplifier and the switch. From the second signal output terminal of the second power amplifier between the first filter for attenuating the harmonic signal superimposed on the high-frequency signal output from the signal output terminal and the second power amplifier and the switch. A second filter for attenuating a harmonic signal superimposed on the high-frequency signal output from the second signal output terminal of the second power amplifier, provided in the path of the output high-frequency signal; .

  In the high-frequency module of the present invention, the amplifier power supply voltage input terminal and the switch power supply voltage input terminal are both connected to the power supply terminal, whereby a transmission path formed between the amplifier power supply voltage input terminal and the switch power supply voltage input terminal is provided. With the provision, the harmonic signal generated by the power amplifier and leaking to the amplifier power supply voltage input terminal can be transmitted to the switch power supply voltage input terminal via the transmission path. Thus, according to the present invention, the harmonic signal transmitted to the switch power supply voltage input terminal via the transmission path and the harmonic signal generated by the switch are synthesized by adjusting the length of the transmission path. Thus, the intensity of the formed harmonic signal can be made smaller than the intensity of the harmonic signal generated by the switch. In the present invention, it is not necessary to provide an extra line for adjusting the phase of the harmonic signal in the path of the output signal of the power amplifier. From the above, according to the present invention, it is possible to reduce the harmonic signal emitted from the switch to the outside without increasing the insertion loss of the output signal path of the power amplifier. In addition, according to the present invention, since the amplifier power supply voltage input terminal and the switch power supply voltage input terminal are both connected to the power supply terminal, the power amplifier power supply terminal and the switch power supply terminal are provided in the high frequency module. As compared with the above, there is an effect that the number of power supply terminals can be reduced.

It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the high frequency module which concerns on the 1st Embodiment of this invention. It is a top view of the high frequency module concerning a 1st embodiment of the present invention. It is explanatory drawing which shows the upper surface of the 1st layer and the 2nd dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 3rd layer and the 4th dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 5th layer and the 6th dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 7th layer and the 8th dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 9th layer and 10th dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 11th layer and 12th dielectric material layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 13th layer and 14th dielectric material layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 15th and 16th dielectric material layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 17th and 18th dielectric material layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the upper surface of the 19th layer and 20th dielectric layer in the laminated substrate shown in FIG. It is explanatory drawing which shows the conductor layer under the 20th dielectric layer in the laminated substrate shown in FIG. It is a block diagram which shows the circuit structure of the high frequency module of a comparative example. It is explanatory drawing for demonstrating the principle of the harmonic signal reduction in the high frequency module which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 6th Embodiment of this invention. It is a block diagram which shows the circuit structure of the high frequency module which concerns on the 7th Embodiment of this invention.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the circuit configuration of the high-frequency module according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a circuit configuration of the high-frequency module according to the present embodiment. FIG. 2 is a circuit diagram showing a circuit configuration of the high-frequency module according to the present embodiment. FIG. 1 shows a simplified circuit configuration of the high-frequency module.

  The high-frequency module 2 according to the present embodiment constitutes a part of a high-frequency circuit unit in a wireless communication device such as a mobile phone or a wireless LAN communication device. The high-frequency module 2 is applied to a time division duplex (TDD) wireless communication apparatus.

  As shown in FIGS. 1 and 2, the high-frequency module 2 includes an antenna terminal ANT connected to the antenna 1, a pair of transmission signal terminals Tx1 and Tx2 to which transmission signals in the form of balanced signals are input, and an unbalanced state. A reception signal terminal Rx that outputs a reception signal in the form of a signal, a power supply terminal Vcc to which a power supply voltage is input, and a switch control terminal V1 to which a switch control signal is input are provided. As shown in FIG. 2, the high frequency module 2 further includes an amplifier control terminal Ve to which a power amplifier control signal is input and an output power detection terminal Vdet. Although not shown in FIGS. 1 and 2, the high-frequency module 2 further includes a plurality of ground terminals.

  Although not shown, an integrated circuit (hereinafter referred to as RFIC) that modulates and demodulates a high-frequency signal is connected to the high-frequency module 2. The RFIC is connected to transmission signal terminals Tx1, Tx2, reception signal terminal Rx, switch control terminal V1, amplifier control terminal Ve, and output power detection terminal Vdet. The RFIC generates a transmission signal, outputs it to the transmission signal terminals Tx1 and Tx2, and receives the reception signal from the reception signal terminal Rx. The RFIC also generates a switch control signal, outputs it to the switch control terminal V1, generates a power amplifier control signal, outputs it to the amplifier control terminal Ve, and is output from the output power detection terminal Vdet. Receive a detection signal.

  The high-frequency module 2 further includes a band-pass filter (hereinafter referred to as BPF) 3, a power amplifier 4, a low-pass filter (hereinafter referred to as LPF) 5, a switch 6, a transmission line 71, and a phase adjustment line 81. And. As shown in FIG. 2, the BPF 3 has a pair of input ports 3a and 3b and an output port 3c. The input ports 3a and 3b are connected to transmission signal output terminals Tx1 and Tx2, respectively. The BPF 3 has a pass band corresponding to the frequency band of the transmission signal, and selectively passes a signal having a frequency within the pass band. The configuration of the BPF 3 will be described in detail later.

  The power amplifier 4 has a signal input terminal 4a, a signal output terminal 4b, amplifier power supply voltage input terminals 4VC1 and 4VC2, terminals 4VE and 4VT, and a ground electrode 4G. In FIG. 1, amplifier power supply voltage input terminals 4VC1 and 4VC2 are collectively shown as amplifier power supply voltage input terminal 4VC. The signal input terminal 4a is connected to the output port 3c of the BPF 3 via the transmission line 71. The signal output terminal 4b is connected to the input end of the LPF 5. The amplifier power supply voltage input terminals 4VC1 and 4VC2 (4VC) are connected to the power supply terminal Vcc. The terminal 4VE is connected to the amplifier control terminal Ve. The terminal 4VT is connected to the output power detection terminal Vdet. The ground electrode 4G is connected to the ground. The power amplifier 4 amplifies the high-frequency signal input to the signal input terminal 4a, that is, the output signal of the BPF 3. The LPF 5 attenuates the harmonic signal generated by the power amplifier 4 and superimposed on the high frequency signal output from the signal output terminal 4 b of the power amplifier 4. A BPF may be provided instead of the LPF 5. This BPF attenuates unnecessary signals having a frequency lower than the frequency band of the transmission signal in addition to the harmonic signal. The configurations of the power amplifier 4 and the LPF 5 will be described in detail later.

  The switch 6 includes terminals 6a, 6b, 6c, a switch power supply voltage input terminal 6VD, a switch control signal input terminal 6V1, a decoder 13, a single pole double throw switch circuit 14, and capacitors C61, C62, C63. have. The terminal 6a is connected to the output terminal of the LPF 5. The terminal 6b is connected to the reception signal terminal Rx. The terminal 6c is connected to the antenna terminal ANT. The terminal 6VD is connected to the power supply terminal Vcc via the phase adjustment line 81. The terminal 6V1 is connected to the switch control terminal V1.

  The switch circuit 14 includes ports 14a, 14b, and 14c, and selectively connects the port 14c to one of the ports 14a and 14b. The port 14a is connected to the terminal 6a via the capacitor C61. The port 14b is connected to the terminal 6b via the capacitor C62. The port 14c is connected to the terminal 6c through the capacitor C63. The switch circuit 14 further has control terminals 14V1 and 14V2. The switch circuit 14 determines two ports to be connected according to signals input to the control terminals 14V1 and 14V2.

  The decoder 13 is composed of a logic circuit. Therefore, the decoder 13 corresponds to the logic circuit in the present invention. The decoder 13 is connected to terminals 6VD and 6V1 and control terminals 14V1 and 14V2. The decoder 13 operates by being supplied with the power supply voltage via the power supply terminal Vcc, the phase adjustment line 81 and the terminal 6VD, and based on the switch control signal input via the switch control terminal V1 and the terminal 6V1. Then, two signals for determining two ports connected in the switch circuit 14 are generated and output to the control terminals 14V1 and 14V2 of the switch circuit 14. Specifically, the decoder 13 has an inverter 64. The terminal 6V1 is connected to the input terminal of the inverter 64 and the control terminal 14V1. The terminal 6VD is connected to the power supply voltage input terminal of the inverter 64. The output terminal of the inverter 64 is connected to the control terminal 14V2. When the switch control signal input to the switch control terminal V1 is at a high level, the signal input to the control terminal 14V1 is at a high level, and the signal input to the control terminal 14V2 is at a low level. When the switch control signal input to the switch control terminal V1 is low level, the signal input to the control terminal 14V1 is low level, and the signal input to the control terminal 14V2 is high level (the power supply voltage input terminal of the inverter 64). The level of the power supply voltage input to the input.

  The switch circuit 14 is configured using an FET. The switch 6 is composed of a semiconductor IC, particularly a monolithic microwave integrated circuit (hereinafter referred to as MMIC).

  As shown in FIG. 2, the high-frequency module 2 further includes a capacitor C23 provided between the terminal 6VD and the ground. The capacitor C23 functions as a bypass capacitor that releases noise from the power supply connected to the power supply terminal Vcc to the ground.

  Here, an example of the configuration of the BPF 3 will be described with reference to FIG. The configuration of BPF 3 is not limited to the configuration shown in FIG. The BPF 3 shown in FIG. 2 includes resonators L31, L32, L33, and L34, and capacitors C31, C32, C33, C34, C71, C72, C73, and C74. Resonators L31, L32, L33, and L34 each include an open end and a short-circuit end. The input port 3a is connected to the resonator L31. One end of each of the capacitors C31, C71, C74 is connected to the open end of the resonator L31. The short-circuit end of the resonator L31 and the other end of the capacitor C31 are grounded. The open end of the resonator L32 and one end of each of the capacitors C32 and C72 are connected to the other end of the capacitor C71. The short-circuit end of the resonator L32 and the other end of the capacitor C32 are grounded. The open end of the resonator L33 and one ends of the capacitors C33 and C73 are connected to the other end of the capacitor C72. The short-circuit end of the resonator L33 and the other end of the capacitor C33 are grounded. The open end of the resonator L34, one end of the capacitor C34, and the other end of the capacitor C74 are connected to the other end of the capacitor C73. The short-circuit end of the resonator L34 and the other end of the capacitor C34 are grounded. The output port 3c is connected to the resonator L34. In FIG. 2, for the sake of convenience, the input port 3a is depicted as being connected to the open end of the resonator L31. However, if the connection location of the input port 3a in the resonator L31 is a location other than the short-circuited end. Good. In FIG. 2, for the sake of convenience, the output port 3c is depicted as being connected to the open end of the resonator L34. However, if the connection location of the output port 3c in the resonator L34 is a location other than the short-circuited end. Good.

  A set of the resonator L31 and the capacitor C31, a set of the resonator L32 and the capacitor C32, a set of the resonator L33 and the capacitor C33, and a set of the resonator L34 and the capacitor C34 constitute a quarter wavelength resonator. Capacitors C31, C32, C33, and C34 have an effect of making the physical lengths of the resonators L31, L32, L33, and L34 shorter than a quarter wavelength of the signal that passes through the BPF 3, respectively. The resonator L31 and the resonator L32 are electromagnetically coupled to each other. That is, the resonator L31 and the resonator L32 are inductively coupled and capacitively coupled via the capacitor C71. Similarly, the resonator L32 and the resonator L33 are electromagnetically coupled to each other. That is, the resonator L32 and the resonator L33 are inductively coupled and capacitively coupled via the capacitor C72. Similarly, the resonator L33 and the resonator L34 are electromagnetically coupled to each other. That is, the resonator L33 and the resonator L34 are inductively coupled and capacitively coupled via the capacitor C73. The inductive coupling between the resonators L31 and L32, the inductive coupling between the resonators L32 and L33, and the inductive coupling between the resonators L33 and L34 all have the same positional relationship between the open end and the short-circuited end. Line connection. In the two resonators, the positional relationship between the open end and the short-circuit end is the same because the direction from the open end to the short-circuit end is the same or almost the same in the two resonators. is there.

  The BPF 3 further includes resonators L35, L36, L37, and L38 and capacitors C35, C36, C37, C38, C75, C76, C77, and C78. Resonators L35, L36, L37, and L38 each include an open end and a short-circuit end. The input port 3b is connected to the resonator L35. One end of each of the capacitors C35, C75, C78 is connected to the open end of the resonator L35. The short-circuit end of the resonator L35 and the other end of the capacitor C35 are grounded. The open end of the resonator L36 and one end of each of the capacitors C36 and C76 are connected to the other end of the capacitor C75. The short-circuit end of the resonator L36 and the other end of the capacitor C36 are grounded. The open end of the resonator L37 and one ends of the capacitors C37 and C77 are connected to the other end of the capacitor C76. The short-circuit end of the resonator L37 and the other end of the capacitor C37 are grounded. The open end of the resonator L38, one end of the capacitor C38, and the other end of the capacitor C78 are connected to the other end of the capacitor C77. The short-circuit end of the resonator L38 and the other end of the capacitor C38 are grounded. In FIG. 2, for the sake of convenience, the input port 3b is drawn so as to be connected to the open end of the resonator L35. However, if the connection location of the input port 3b in the resonator L35 is a location other than the short-circuited end. Good.

  The set of resonator L35 and capacitor C35, the set of resonator L36 and capacitor C36, the set of resonator L37 and capacitor C37, and the set of resonator L38 and capacitor C38 each constitute a quarter wavelength resonator. Capacitors C35, C36, C37, and C38 have a function of making the physical lengths of the resonators L35, L36, L37, and L38 shorter than a quarter wavelength of the signal passing through the BPF 3, respectively. The resonator L35 and the resonator L36 are electromagnetically coupled to each other. That is, the resonator L35 and the resonator L36 are inductively coupled and capacitively coupled via the capacitor C75. Similarly, the resonator L36 and the resonator L37 are also electromagnetically coupled to each other. That is, the resonator L36 and the resonator L37 are inductively coupled and capacitively coupled via the capacitor C76. Similarly, the resonator L37 and the resonator L38 are also electromagnetically coupled to each other. That is, the resonator L37 and the resonator L38 are inductively coupled and capacitively coupled via the capacitor C77. The inductive coupling between the resonators L35 and L36, the inductive coupling between the resonators L36 and L37, and the inductive coupling between the resonators L37 and L38 all have the same positional relationship between the open end and the short-circuited end. Line connection.

  In addition, the resonator L31 and the resonator L35, the resonator L32 and the resonator L36, the resonator L33 and the resonator L37, and the resonator L34 and the resonator L38 are interdigitally coupled. That is, the resonator L31 and the resonator L35 face each other so that the positional relationship between the open end and the short-circuited end is opposite to each other, and are electromagnetically coupled to each other. Further, the resonator L32 and the resonator L36 face each other so that the positional relationship between the open end and the short-circuited end is opposite to each other and are electromagnetically coupled to each other. Further, the resonator L33 and the resonator L37 face each other such that the positional relationship between the open end and the short-circuit end is opposite to each other, and are electromagnetically coupled to each other. The resonator L34 and the resonator L38 face each other so that the positional relationship between the open end and the short-circuited end is opposite to each other, and are electromagnetically coupled to each other.

  The resonators L31 to L38 are all distributed constant lines made of TEM lines. The TEM line is a transmission line that transmits a TEM wave (Transverse Electromagnetic Wave) that is an electromagnetic wave in which both an electric field and a magnetic field exist only in a cross section perpendicular to the traveling direction of the electromagnetic wave.

  In the BPF 3, balanced signals from the transmission signal terminals Tx1 and Tx2 are input to the resonators L31 and L35 connected to the input ports 3a and 3b, respectively, and from the output port 3c connected to the resonator L34, the passband of the BPF3. An unbalanced signal having a frequency within the range is output.

  Next, an example of the configuration of the power amplifier 4 will be described with reference to FIG. The configuration of the power amplifier 4 is not limited to the configuration shown in FIG. The power amplifier 4 shown in FIG. 2 includes two amplifiers 11 and 12 connected in cascade, capacitors C41 and C42, a bias circuit 43, and a diode 44. The power amplifier 4 is constituted by a semiconductor IC, particularly an MMIC.

  The amplifiers 11 and 12 each have an input end and an output end. The input end of the amplifier 11 is connected to the signal input terminal 4a via the capacitor C41. The output terminal of the amplifier 11 is connected to the input terminal of the amplifier 12. The output terminal of the amplifier 12 is connected to the signal output terminal 4b via the capacitor C42. The amplifier power supply voltage input terminal 4VC1 is connected to the output terminal of the amplifier 11, and the amplifier power supply voltage input terminal 4VC2 is connected to the output terminal of the amplifier 12.

  The bias circuit 43 is connected to the terminal 4VE and to the amplifiers 11 and 12. The bias circuit 43 supplies a bias voltage to the amplifiers 11 and 12 when the power amplifier control signal input via the amplifier control terminal Ve and the terminal 4VE instructs the operation of the amplifiers 11 and 12. The amplifiers 11 and 12 operate by being supplied with a power supply voltage via amplifier power supply voltage input terminals 4VC1 and 4VC2 and a bias voltage. The operational amplifiers 11 and 12 amplify the transmission signal input to the signal input terminal 4a and output the amplified signal to the signal output terminal 4b.

  Although not shown, the power amplifier 4 includes a coupler that extracts a part of the output power of the power amplifier 4 from the signal path between the output terminal of the amplifier 12 and the capacitor C42 as a power detection circuit. The anode of the diode 44 is connected to this coupler. The cathode of the diode 44 is connected to the terminal 4VT. A detection signal indicating the level of output power of the power amplifier 4 is output from the terminal 4VT. This detection signal is input to an automatic output control circuit provided in the RFIC via the output power detection terminal Vdet. This automatic output control circuit controls the level of the transmission signal supplied to the power amplifier 4 so that the level of the output power of the power amplifier 4 becomes substantially constant. Note that the high-frequency module 2 may include an automatic output control circuit, and the automatic output control circuit may adjust the gain of the power amplifier 4 so that the output power level of the power amplifier 4 is substantially constant.

  As shown in FIG. 2, the high frequency module 2 further includes an inductor L21 and capacitors C21 and C22. One end of the inductor L21 is connected to the power supply terminal Vcc, and the other end of the inductor L21 is connected to the amplifier power supply voltage input terminal 4VC2. The capacitor C22 is provided between one end of the inductor L21 and the ground. The capacitor C21 is provided between the amplifier power supply voltage input terminal 4VC1 and the ground. The power supply terminal Vcc of the high frequency module 2 is directly connected to the terminal 4VC1, and is connected to the terminal 4VC2 via the inductor L21. The inductor L21 functions as a choke inductor. Capacitors C21 and C22 function as bypass capacitors that remove noise from the power supply connected to the power supply terminal Vcc by escaping to the ground.

  Next, an example of the configuration of the LPF 5 will be described with reference to FIG. Note that the configuration of the LPF 5 is not limited to the configuration shown in FIG. The LPF 5 shown in FIG. 2 includes inductors L51 and L52 and capacitors C51, C52, C53, C54, and C55. One end of each of the inductor L51 and the capacitors C51 and C54 is connected to the output terminal 4b of the power amplifier 4 via the input end of the LPF 5. The other end of the capacitor C51 is grounded. One end of each of the inductor L52 and the capacitors C52 and C55 and the other end of the capacitor C54 are connected to the other end of the inductor L51. The other end of the capacitor C52 is grounded. Each other end of the inductor L52 and the capacitor C55 and one end of the capacitor C53 are connected to the terminal 6a of the switch 6 via the output end of the LPF 5. The other end of the capacitor C53 is grounded.

  In the high frequency module 2 according to the present embodiment, the power amplifier 4 generates a harmonic signal for the transmission signal. The harmonic signal generated by the power amplifier 4 leaks to the amplifier power supply voltage input terminal 4VC2. The inductance of the inductor L21 and the capacitance of the capacitor C22 are set so that the attenuation between the power supply terminal Vcc and the terminal 4VC2 with respect to the frequency band of the transmission signal is sufficiently large so that the transmission signal is not transmitted to the power supply terminal Vcc side. . In this case, the attenuation between the power supply terminal Vcc and the terminal 4VC2 with respect to the harmonic signal can be made smaller than the attenuation between the power supply terminal Vcc and the terminal 4VC2 with respect to the frequency band of the transmission signal.

  In the high frequency module 2 according to the present embodiment, the amplifier power supply voltage input terminal 4VC2 and the switch power supply voltage input terminal 6VD are both connected to the power supply terminal Vcc. Here, as shown in FIG. 2, a branch point between a line extending from the power supply terminal Vcc to the terminal 4VC2 and a line extending from the power supply terminal Vcc to the terminal 6VD is represented by a symbol ND. In the high frequency module 2 according to the present embodiment, the amplifier power supply voltage input terminal 4VC2 and the switch power supply voltage input terminal 6VD are connected to each other by connecting the amplifier power supply voltage input terminal 4VC2 and the switch power supply voltage input terminal 6VD to the power supply terminal Vcc. The harmonic signal transmission path 80 formed between the two is provided. The harmonic signal transmission path 80 transmits the harmonic signal generated by the power amplifier 4 and leaking to the amplifier power supply voltage input terminal 4VC2 to the switch power supply voltage input terminal 6VD. The harmonic signal transmission path 80 corresponds to the transmission path in the present invention. The harmonic signal transmission path 80 is a path from the amplifier power supply voltage input terminal 4VC2 to the switch power supply voltage input terminal 6VD via the inductor L21, the branch point ND, and the phase adjustment line 81. In order to prevent the harmonic signal flowing from the amplifier power supply voltage input terminal 4VC2 to the harmonic signal transmission path 80 from being reflected at the starting point of the harmonic signal transmission path 80, the characteristic impedance of the harmonic signal transmission path 80 is high frequency. The characteristic impedance of the main transmission line in the module 2 is preferably equal to or close to the characteristic impedance. For example, when the characteristic impedance of the main transmission line in the high-frequency module 2 is 50Ω, the characteristic impedance of the harmonic signal transmission path 80 is preferably 50Ω or a value close to 50Ω.

  Next, main operations of the high-frequency module 2 according to the present embodiment will be described. When transmitting a transmission signal, the port 14c of the switch circuit 14 is connected to the port 14a. In this case, the transmission signal in the form of a balanced signal output from the RFIC passes through the pair of transmission signal terminals Tx1 and Tx2, is input to the BPF 3, and is converted into a transmission signal in the form of an unbalanced signal by the BPF 3. The transmission signal in the form of this unbalanced signal passes through the transmission line 71, is amplified by the power amplifier 4, passes through the LPF 5, the switch 6 and the antenna terminal ANT in this order, and is supplied to the antenna 1, and is transmitted from the antenna 1. The

  When receiving a reception signal, the port 14c of the switch circuit 14 is connected to the port 14b. In this case, the reception signal received by the antenna 1 passes through the antenna terminal ANT, the switch 6 and the reception signal terminal Rx in this order and is input to the RFIC.

  Next, the structure of the high frequency module 2 corresponding to the circuit configuration shown in FIG. 2 will be described. FIG. 3 is a plan view of the high-frequency module 2. As shown in FIG. 3, the high-frequency module 2 includes a laminated substrate 20 that integrates the elements of the high-frequency module 2. As will be described in detail later, the laminated substrate 20 includes a plurality of laminated dielectric layers. The laminated substrate 20 has an upper surface 20a, a bottom surface, and four side surfaces, and has a rectangular parallelepiped shape.

  The circuit in the high-frequency module 2 is configured using a conductor layer provided in the multilayer substrate 20, the dielectric layer, and an element mounted on the upper surface 20 a of the multilayer substrate 20. The power amplifier 4, the switch 6, the capacitors C21, C22, C23 and the inductor L21 are mounted on the upper surface 20a. The power amplifier 4 and the switch 6 are each a semiconductor IC in the form of a bare chip. As will be described later, a plurality of terminals of the high-frequency module 2 are arranged on the bottom surface of the multilayer substrate 20.

  The power amplifier 4 has a bottom surface facing the top surface 20a of the multilayer substrate 20 and an upper surface on the opposite side. On the upper surface of the power amplifier 4, terminals 4a, 4b, 4VC1, 4VC2, 4VE, and 4VT are arranged. On the bottom surface of the power amplifier 4, a ground electrode 4G is disposed.

  The switch 6 has a bottom surface facing the top surface 20a of the multilayer substrate 20 and an upper surface on the opposite side. Terminals 6 a, 6 b, 6 c, 6 VD, and 6 V 1 are disposed on the upper surface of the switch 6.

  Each terminal of the power amplifier 4 and the switch 6 is connected to a corresponding conductor layer formed on the upper surface 20a of the multilayer substrate 20 by wire bonding. Although not shown, the upper surface 20a of the multilayer substrate 20 and all the elements mounted on the upper surface 20a are molded with resin.

  Next, with reference to FIGS. 4 to 14, the dielectric layer and the conductor layer in the multilayer substrate 20 will be described in detail. 4A and 4B show the top surfaces of the first and second dielectric layers from the top, respectively. 5A and 5B respectively show the top surfaces of the third and fourth dielectric layers from the top. 6A and 6B respectively show the top surfaces of the fifth and sixth dielectric layers from the top. 7A and 7B respectively show the top surfaces of the seventh and eighth dielectric layers from the top. 8A and 8B respectively show the top surfaces of the ninth and tenth dielectric layers from the top. 9A and 9B respectively show the top surfaces of the eleventh and twelfth dielectric layers from the top. 10A and 10B respectively show the top surfaces of the thirteenth and fourteenth dielectric layers from the top. 11A and 11B show the top surfaces of the 15th and 16th dielectric layers from the top, respectively. 12A and 12B respectively show the top surfaces of the 17th and 18th dielectric layers from the top. 13A and 13B show the top surfaces of the 19th and 20th dielectric layers from the top, respectively. FIG. 14 shows the twentieth dielectric layer from the top and the conductor layer therebelow as seen from above. 4 to 14, circles represent through holes.

  On the upper surface of the first dielectric layer 21 shown in FIG. 4A, conductor layers 212A and 212B to which the inductor L21 is connected, conductor layers 212C and 212D to which the capacitor C21 is connected, and a capacitor C22 are provided. Conductive layers 212E and 212F to be connected and conductive layers 212H and 212I to which the capacitor C23 is connected are formed. Further, conductor layers 214A, 214B, 21VC1, 21VC2, 21VE, and 21VT to which the terminals 4a, 4b, 4VC1, 4VC2, 4VE, and 4VT of the power amplifier 4 are connected are respectively formed on the upper surface of the dielectric layer 21 by wire bonding. Is formed. Conductive layers 216A, 216B, 216C, 21VD, and 21V1 to which the terminals 6a, 6b, 6c, 6VD, and 6V1 of the switch 6 are connected are further formed on the upper surface of the dielectric layer 21 by wire bonding. Conductive layers 21G1 and 21G2 connected to the ground are further formed on the upper surface of the dielectric layer 21. The power amplifier 4 is joined to the conductor layer 21G1, and the switch 6 is joined to the conductor layer 21G2. The ground electrode 4G of the power amplifier 4 is connected to the conductor layer 21G1. The dielectric layer 21 has a plurality of through holes connected to each conductor layer.

  Conductor layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are formed on the upper surface of the second dielectric layer 22 shown in FIG. Conductive layers 21VD and 212I are connected to the conductive layer 221 through two through holes formed in the dielectric layer 21. The conductor layer 216 </ b> A is connected to the conductor layer 222 via a through hole formed in the dielectric layer 21. The conductor layer 214 </ b> B is connected to the conductor layer 223 through a through hole formed in the dielectric layer 21. The conductor layers 212A and 212F are connected to the conductor layer 224 through two through holes formed in the dielectric layer 21. Conductive layers 21VC2 and 212B are connected to the conductive layer 225 through two through holes formed in the dielectric layer 21. The conductor layers 21VC1 and 212C are connected to the conductor layer 226 through two through holes formed in the dielectric layer 21. The conductor layer 227 is connected to the conductor layer 227 through a through hole formed in the dielectric layer 21. A conductor layer 214A is connected to the conductor layer 228 through a through hole formed in the dielectric layer 21. A conductor layer 216 </ b> B is connected to the conductor layer 229 through a through hole formed in the dielectric layer 21. The dielectric layer 22 is formed with eight through holes connected to the conductor layers 221, 222, 223, 224, 226, 227, 228, and 229 and a plurality of other through holes, respectively.

  Conductor layers 231, 232, and 233 are formed on the top surface of the third dielectric layer 23 shown in FIG. The conductor layer 231 is connected to the conductor layer 231 through through holes formed in the dielectric layers 21 and 22. Conductor layers 212C and 226 are connected to the conductor layer 232 through through holes formed in the dielectric layers 21 and 22, and the conductor layer 224 is formed through the through holes formed in the dielectric layer 22. It is connected. A conductor layer 21VE is connected to the conductor layer 233 through through holes formed in the dielectric layers 21 and 22. The dielectric layer 23 is formed with three through holes connected to the conductor layers 231, 232, and 233, respectively, and a plurality of other through holes.

  On the top surface of the fourth dielectric layer 24 shown in FIG. 5B, a ground layer 241 is formed as a conductor layer. The dielectric layer 24 has a plurality of through holes connected to the ground layer 241 and a plurality of other through holes.

  BPF conductor layers 251 and 252 are formed on the upper surface of the fifth dielectric layer 25 shown in FIG. The dielectric layer 25 has two through holes connected to the conductor layers 251 and 252 and a plurality of other through holes.

  BPF conductor layers 261 and 262 are formed on the top surface of the sixth dielectric layer 26 shown in FIG. 6B. The dielectric layer 26 has two through holes connected to the conductor layer 261, a through hole connected to the conductor layer 262, and a plurality of other through holes.

  BPF conductor layers 271, 272, 273, 274 and a conductor layer 275 are formed on the top surface of the seventh dielectric layer 27 shown in FIG. The conductor layer 261 is connected to the conductor layer 271 through a through hole formed in the dielectric layer 26. A conductor layer 251 is connected to the conductor layer 272 through through holes formed in the dielectric layers 25 and 26. A conductor layer 252 is connected to the conductor layer 273 through through holes formed in the dielectric layers 25 and 26. A conductor layer 262 is connected to the conductor layer 274 through a through hole formed in the dielectric layer 26. A conductor layer 261 is connected to the conductor layer 275 via a through hole formed in the dielectric layer 26, and a conductor layer 228 is connected via a through hole formed in the dielectric layers 22 to 26. ing. In addition, the dielectric layer 27 is connected to the two through holes connected to the conductor layer 271, the through hole connected to the conductor layer 272, the through hole connected to the conductor layer 273, and the conductor layer 274. Two through holes and a plurality of other through holes are formed.

  BPF conductor layers 281 and 282 are formed on the top surface of the eighth dielectric layer 28 shown in FIG. 7B. The conductor layer 271 is connected to the conductor layer 281 through a through hole formed in the dielectric layer 27. A conductor layer 274 is connected to the conductor layer 282 through a through hole formed in the dielectric layer 27. The dielectric layer 28 has a plurality of through holes.

  BPF conductor layers 291, 292, 293, and 294 and LPF conductor layers 295 and 296 are formed on the top surface of the ninth dielectric layer 29 shown in FIG. Conductive layers 261 and 271 are connected to the conductive layer 291 through through holes formed in the dielectric layers 26 to 28. Conductive layers 251 and 272 are connected to the conductive layer 292 through through holes formed in the dielectric layers 25 to 28. Conductive layers 252 and 273 are connected to the conductive layer 293 through through holes formed in the dielectric layers 25 to 28. Conductive layers 262 and 274 are connected to the conductive layer 294 through through holes formed in the dielectric layers 26 to 28. The conductor layer 223 is connected to the conductor layer 295 through through holes formed in the dielectric layers 22 to 28. The dielectric layer 29 has four through holes connected to the conductor layers 291, 292, 293, 294, two through holes connected to the conductor layer 295, and 2 connected to the conductor layer 296. One through hole and a plurality of other through holes are formed.

  A BPF conductor layer 301, an LPF conductor layer 302, and a conductor layer 303 are formed on the top surface of the tenth dielectric layer 30 shown in FIG. 8B. A conductor layer 295 is connected to the conductor layer 302 through a through hole formed in the dielectric layer 29. A ground layer 241 is connected to the conductor layer 303 through through holes formed in the dielectric layers 24 to 29. The dielectric layer 30 is formed with through holes connected to the conductor layer 302, a plurality of through holes connected to the conductor layer 303, and a plurality of other through holes.

  In the eleventh dielectric layer 31 shown in FIG. 9A, resonators L31, L32, L33, and L34 and conductor layers 311 and 312 made of conductor layers are formed. The resonator L31 has an open end L31a and a short-circuited end L31b. The resonator L32 has an open end L32a and a short-circuited end L32b. The resonator L33 has an open end L33a and a short-circuited end L33b. The resonator L34 has an open end L34a and a short-circuited end L34b.

  The resonator L31 and the resonator L32 are adjacent so that the open ends L31a and L32a are close to each other and the short-circuited ends L31b and L32b are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L31 and L32 is the same, and the resonators L31 and L32 are comb-line coupled.

  The resonator L32 and the resonator L33 are adjacent so that the open ends L32a and L33a are close to each other and the short-circuited ends L32b and L33b are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L32 and L33 is the same, and the resonators L32 and L33 are comb-line coupled.

  The resonator L33 and the resonator L34 are adjacent so that the open ends L33a and L34a are close to each other and the short-circuited ends L33b and L34b are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L33 and L34 is the same, and the resonators L33 and L34 are comb-line coupled.

  Conductor layers 262 and 294 are connected to the open end L31a of the resonator L31 through through holes formed in the dielectric layers 26 to 30. Conductive layers 252 and 293 are connected to the open end L32a of the resonator L32 through through holes formed in the dielectric layers 25 to 30. Conductor layers 251 and 292 are connected to the open end L33a of the resonator L33 through through holes formed in the dielectric layers 25 to 30. Conductor layers 261 and 291 are connected to the open end L34a of the resonator L34 through through holes formed in the dielectric layers 26 to 30. A ground layer 241 is connected to the short-circuit ends L31b, L32b, L33b, and L34b of the resonators L31, L32, L33, and L34 through through holes formed in the dielectric layers 24-30. The conductor layer 311 connects the short-circuit end L32b of the resonator L32 and the short-circuit end L33b of the resonator L33. The conductor layer 312 is connected to the resonator L31. The conductor layer 312 corresponds to the input port 3a in FIG.

  The dielectric layer 31 includes four through holes connected to the short-circuit ends of the resonators L31, L32, L33, and L34, a through hole connected to the conductor layer 312 and a plurality of other through holes. Is formed.

  In the twelfth dielectric layer 32 shown in FIG. 9B, resonators L35, L36, L37, and L38 and conductor layers 321, 322, 323, 324, and 325 made of conductor layers are formed, respectively. Yes. The resonator L35 has an open end L35a and a short-circuited end L35b. The resonator L36 has an open end L36a and a short-circuited end L36b. The resonator L37 has an open end L37a and a short-circuited end L37b. The resonator L38 has an open end L38a and a short-circuited end L38b.

  The resonator L35 and the resonator L36 are adjacent so that the open ends L35a and L36a are close to each other and the short-circuited ends L35b and L36b are close to each other. Accordingly, the positional relationship between the open end and the short-circuited end in the resonators L35 and L36 is the same, and the resonators L35 and L36 are comb-line coupled.

  The resonator L36 and the resonator L37 are adjacent so that the open ends L36a and L37a are close to each other and the short-circuited ends L36b and L37b are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L36 and L37 is the same, and the resonators L36 and L37 are comb-line coupled.

  The resonator L37 and the resonator L38 are adjacent so that the open ends L37a and L38a are close to each other and the short-circuited ends L37b and L38b are close to each other. Therefore, the positional relationship between the open end and the short-circuit end in the resonators L37 and L38 is the same, and the resonators L37 and L38 are comb-line coupled.

  The resonator L31 and the resonator L35 are opposed to each other via the dielectric layer 31 so that the open end L31a and the short-circuit end L35b are close to each other and the short-circuit end L31b and the open end L35a are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L31 and L35 is opposite to each other, and the resonators L31 and L35 are interdigitally coupled.

  The resonator L32 and the resonator L36 are opposed to each other through the dielectric layer 31 so that the open end L32a and the short-circuit end L36b are close to each other and the short-circuit end L32b and the open end L36a are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L32 and L36 is opposite to each other, and the resonators L32 and L36 are interdigitally coupled.

  The resonator L33 and the resonator L37 are opposed to each other through the dielectric layer 31 so that the open end L33a and the short-circuit end L37b are close to each other and the short-circuit end L33b and the open end L37a are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L33 and L37 is opposite to each other, and the resonators L33 and L37 are interdigitally coupled.

  The resonator L34 and the resonator L38 face each other through the dielectric layer 31 so that the open end L34a and the short-circuited end L38b are close to each other, and the short-circuited end L34b and the open-ended L38a are close to each other. Therefore, the positional relationship between the open end and the short-circuited end in the resonators L34 and L38 is opposite to each other, and the resonators L34 and L38 are interdigitally coupled.

  The ground layer 241 and the conductor layer 303 are connected to the respective short-circuit ends L35b, L36b, L37b, and L38b of the resonators L35, L36, L37, and L38 through through holes formed in the dielectric layers 24-31. . The conductor layer 321 connects the short-circuit end L36b of the resonator L36 and the short-circuit end L37b of the resonator L37. The conductor layer 322 is connected to the resonator L35. The conductor layer 322 corresponds to the input port 3b in FIG.

  A conductor layer 216 </ b> C is connected to the conductor layer 323 through a through hole formed in the dielectric layers 21 to 31. A conductor layer 296 is connected to the conductor layer 324 through through holes formed in the dielectric layers 29 to 31. A conductor layer 296 is connected to the conductor layer 325 through through holes formed in the dielectric layers 29 to 31.

  In addition, the dielectric layer 32 is connected to eight through holes connected to the open ends and short-circuit ends of the resonators L35, L36, L37, and L38, and to the conductor layers 322, 323, 324, and 325, respectively. Four through holes and a plurality of other through holes are formed.

  A BPF conductor layer 331 is formed on the top surface of the thirteenth dielectric layer 33 shown in FIG. The dielectric layer 33 has a plurality of through holes.

  BPF conductor layers 341, 342, 343, and 344 are formed on the upper surface of the fourteenth dielectric layer 34 shown in FIG. An open end L38a of the resonator L38 is connected to the conductor layer 341 through through holes formed in the dielectric layers 32 and 33. An open end L37a of a resonator L37 is connected to the conductor layer 342 through through holes formed in the dielectric layers 32 and 33. An open end L36a of the resonator L36 is connected to the conductor layer 343 through through holes formed in the dielectric layers 32 and 33. An open end L35a of a resonator L35 is connected to the conductor layer 344 through through holes formed in the dielectric layers 32 and 33. The dielectric layer 34 has four through holes connected to the conductor layers 341, 342, 343, and 344, and a plurality of other through holes, respectively.

  BPF conductor layers 351 and 352 are formed on the top surface of the fifteenth dielectric layer 35 shown in FIG. The dielectric layer 35 is formed with two through holes connected to the conductor layers 351 and 352 and a plurality of other through holes.

On the top surface of the sixteenth dielectric layer 36 shown in FIG.
62, 363, 364 and LPF conductor layers 365, 366 are formed. The conductor layer 361 is connected to the open end L38a of the resonator L38 and the conductor layer 341 via through holes formed in the dielectric layers 32 to 35, and has through holes formed in the dielectric layer 35. The conductor layer 351 is connected via the via. An open end L37a of the resonator L37 and the conductor layer 342 are connected to the conductor layer 362 through through holes formed in the dielectric layers 32 to 35. An open end L36a of the resonator L36 and the conductor layer 343 are connected to the conductor layer 363 through through holes formed in the dielectric layers 32 to 35. The conductor layer 364 is connected to the open end L35a of the resonator L35 and the conductor layer 344 via through holes formed in the dielectric layers 32 to 35, and has through holes formed in the dielectric layer 35. The conductor layer 352 is connected via the via. A conductor layer 295 is connected to the conductor layer 365 via through holes formed in the dielectric layers 29 to 35. A conductor layer 325 is connected to the conductor layer 366 through through holes formed in the dielectric layers 32 to 35. The dielectric layer 35 has six through holes connected to the conductor layers 361, 362, 363, 364, 365, and 366, and a plurality of other through holes.

  BPF conductor layers 371 and 372 and an LPF conductor layer 373 are formed on the top surface of the seventeenth dielectric layer 37 shown in FIG. The conductor layer 371 is connected to the open end L38a of the resonator L38 and the conductor layers 341 and 361 through through holes formed in the dielectric layers 32 to 36. An open end L35a of the resonator L35 and the conductor layers 344 and 364 are connected to the conductor layer 372 through through holes formed in the dielectric layers 32 to 36. The conductor layer 373 is connected to the conductor layer 373 through through holes formed in the dielectric layers 30 to 36, and the conductor layer 324 is formed through the through holes formed in the dielectric layers 32 to 36. It is connected. The dielectric layer 37 has a plurality of through holes.

  BPF conductor layers 381, 382, LPF conductor layers 383, 384, and a conductor layer 385 are formed on the top surface of the eighteenth dielectric layer 38 shown in FIG. The conductor layer 381 is connected to the open end L37a of the resonator L37 and the conductor layers 342 and 362 through through holes formed in the dielectric layers 32 to 37. An open end L36a of the resonator L36 and the conductor layers 343 and 363 are connected to the conductor layer 382 through through holes formed in the dielectric layers 32 to 37. Conductive layers 295 and 365 are connected to the conductive layer 383 through through holes formed in the dielectric layers 29 to 37. A conductor layer 222 is connected to the conductor layer 384 through through holes formed in the dielectric layers 22 to 37, and the conductor layers 325 and 325 are connected through through holes formed in the dielectric layers 32 to 37. 366 is connected. A conductor layer 233 is connected to the conductor layer 385 through through holes formed in the dielectric layers 23 to 37. The dielectric layer 38 has a through hole connected to the conductor layer 385 and a plurality of other through holes.

  On the top surface of the nineteenth dielectric layer 39 shown in FIG. 13A, a ground layer 391 is formed as a conductor layer. The ground layer 391 is connected to the ground layer 241 through through holes formed in the dielectric layers 24 to 38 and the short-circuit ends L31b and L32b of the resonators L31, L32, L33, L34, L35, L36, L37, and L38. , L33b, L34b, L35b, L36b, L37b, L38b and the conductor layer 303 are connected. The dielectric layer 39 has a plurality of through holes connected to the ground layer 391 and a plurality of other through holes.

  Conductor layers 401, 402, and 403 are formed on the top surface of the twentieth dielectric layer 40 shown in FIG. 13B. In addition, the dielectric layer 40 includes a through hole 401H connected to the conductor layer 401, a through hole connected to the conductor layer 402, a through hole connected to the conductor layer 403, and a plurality of other through holes. Is formed.

  The conductor layer 401 has a meander-shaped phase adjustment portion 401a extending from a position connected to the through hole 401H to one end, and a line portion 401b extending from the position connected to the through hole 401H to the other end. is doing. Conductor layers 212I and 221 are connected to end portions 401a1 of the phase adjustment portion 401a opposite to the positions connected to the through holes 401H through through holes formed in the dielectric layers 21 to 39. Conductor layers 224 and 232 are connected to end portions 401b1 of the line portion 401b opposite to the positions connected to the through holes 401H through through holes formed in the dielectric layers 22 to 39.

  The conductor layer 231 is connected to the conductor layer 402 through through holes formed in the dielectric layers 23 to 39. A conductor layer 385 is connected to the conductor layer 403 through through holes formed in the dielectric layers 38 and 39.

  As shown in FIG. 14, the above-mentioned terminals ANT, Tx1, Tx2, Rx, Vcc, Ve, Vdet, V1 and eight ground terminals G1 are provided on the lower surface of the dielectric layer 40, that is, the bottom surface of the multilayer substrate 20. , G2, G3, G4, G5, G6, G7, G8, and a ground conductor layer G9. On the bottom surface of the multilayer substrate 20, the plurality of terminals are disposed in the vicinity of the side of the bottom surface. The ground conductor layer G9 is disposed in a wide area surrounded by a plurality of terminals on the bottom surface.

  The above-described first to twentieth dielectric layers 21 to 40 and conductor layers are laminated to form the laminated substrate 20 shown in FIG. On the upper surface 20a of the multilayer substrate 20, the power amplifier 4, the switch 6, the inductor L21, and the capacitors C21, C22, and C23 are mounted. Each terminal of the power amplifier 4 and the switch 6 is connected to a corresponding conductor layer formed on the upper surface 20a of the multilayer substrate 20 by wire bonding as follows. That is, terminals 4a, 4b, 4VC1, 4VC2, 4VE, and 4VT of power amplifier 4 are connected to conductor layers 214A, 214B, 21VC1, 21VC2, 21VE, and 21VT, respectively. Terminals 6a, 6b, 6c, 6VD, and 6V1 of the switch 6 are connected to the conductor layers 216A, 216B, 216C, 21VD, and 21V1, respectively. One end of the inductor L21 is connected to the conductor layer 212A, and the other end of the inductor L21 is connected to the conductor layer 212B. One end of the capacitor C21 is connected to the conductor layer 212C, and the other end of the capacitor C21 is connected to the conductor layer 212D. One end of the capacitor C22 is connected to the conductor layer 212E, and the other end of the capacitor C22 is connected to the conductor layer 212F. One end of the capacitor C23 is connected to the conductor layer 212H, and the other end of the capacitor C23 is connected to the conductor layer 212I. The upper surface 20a of the multilayer substrate 20 and all the elements mounted on the upper surface 20a are molded with resin.

  The BPF 3 and the LPF 5 are configured using a plurality of conductor layers provided in the multilayer substrate 20. In the present embodiment, as the laminated substrate 20, various materials such as a material using a resin, ceramic, or a composite material of both can be used as the material of the dielectric layer. However, as the laminated substrate 20, it is particularly preferable to use a low-temperature co-fired ceramic multilayer substrate having excellent high-frequency characteristics. The high frequency module 2 is mounted on the mounting substrate so that the bottom surface of the multilayer substrate 20 faces downward. At this time, the plurality of terminals and ground conductor layer G9 provided on the bottom surface are connected to the corresponding terminals and ground layer on the mounting substrate.

  A conductor layer 216 </ b> C is connected to the antenna terminal ANT via a through hole formed in the dielectric layers 21 to 40 and a conductor layer 323. A resonator L31 is connected to the transmission signal terminal Tx1 through a through hole formed in the dielectric layers 31 to 40 and a conductor layer 312. A resonator L35 is connected to the transmission signal terminal Tx2 through a through hole formed in the dielectric layers 32 to 40 and a conductor layer 322. The conductor layer 216 </ b> B is connected to the reception signal terminal Rx via a through hole formed in the dielectric layers 21 to 40 and the conductor layer 229.

  A conductor layer 401 is connected to the power supply terminal Vcc through a through hole 401H formed in the dielectric layer 40. The conductor layer 21VC1 is connected to the end portion 401b1 of the line portion 401b of the conductor layer 401 through through holes formed in the dielectric layers 21 to 39 and the conductor layers 226 and 232. The conductor layer 21VC2 is connected to one end of the inductor L21 through a through hole formed in the dielectric layer 21 and the conductor layers 212B and 225. The other end of the inductor L21 is connected to the end 401b1 of the line portion 401b of the conductor layer 401 through through holes formed in the dielectric layers 21 to 29 and the conductor layers 212A, 224, 232. The conductor layer 21VD is connected to the end 401a1 of the phase adjustment portion 401a of the conductor layer 401 through through holes formed in the dielectric layers 21 to 39 and the conductor layer 221.

  A conductor layer 21VE is connected to the control terminal Ve through through holes formed in the dielectric layers 21 to 40 and conductor layers 233, 385, and 403. The output power detection terminal Vdet is connected to the conductor layer 21VT through through holes formed in the dielectric layers 21 to 40 and conductor layers 231 and 402. A conductor layer 21V1 is connected to the control terminal V1 through through holes formed in the dielectric layers 21-40.

  A ground layer 391 is connected to the ground terminals G1 to G8 and the ground conductor layer G9 through a plurality of through holes formed in the dielectric layers 39 and 40. The ground terminals G1 to G8 and the ground conductor layer G9 are connected to the ground by being connected to the ground layer of the mounting substrate.

  The BPF 3 shown in FIG. 2 includes resonators L31, L32, L33, L34, L35, L36, L37, and L38, and conductor layers 251, 252, 261, 262, 271 to 274, 281, 282, 291 to 294 and 301. 311, 312, 321, 322, 331, 341 to 344, 351, 352, 361 to 364, 371, 372, 381, 382, ground layers 241 and 391, dielectric layers 24 to 38, and dielectric layers And a plurality of through holes formed in 24-38.

  The conductor layer 262, the ground layer 241 and the dielectric layers 24 and 25 disposed therebetween constitute a capacitor C31. The conductor layer 252, the ground layer 241, and the dielectric layer 24 disposed therebetween constitute a capacitor C <b> 32. The conductor layer 251, the ground layer 241, and the dielectric layer 24 disposed therebetween constitute a capacitor C <b> 33. The conductor layer 261, the ground layer 241 and the dielectric layers 24 and 25 disposed therebetween constitute a capacitor C34.

  The conductor layers 273 and 282 and the dielectric layer 27 disposed therebetween, and the conductor layers 282 and 293 and the dielectric layer 28 disposed therebetween constitute the capacitor C71. The conductor layers 292, 293, 301 and the dielectric layer 29 disposed therebetween constitute a capacitor C72. The conductor layers 272 and 281 and the dielectric layer 27 disposed therebetween, and the conductor layers 281 and 292 and the dielectric layer 28 disposed therebetween constitute the capacitor C73. The conductor layers 291, 294, 301 and the dielectric layer 29 disposed therebetween constitute a capacitor C 74.

  The conductor layer 372, the ground layer 391, and the dielectric layers 37 and 38 disposed therebetween constitute a capacitor C35. The conductor layer 382, the ground layer 391, and the dielectric layer 38 disposed therebetween constitute a capacitor C36. The conductor layer 381, the ground layer 391, and the dielectric layer 38 disposed therebetween constitute a capacitor C37. The conductor layer 371, the ground layer 391, and the dielectric layers 37 and 38 disposed therebetween constitute a capacitor C38.

  The conductor layers 343 and 352 and the dielectric layer 34 disposed therebetween, and the conductor layers 352 and 363 and the dielectric layer 35 disposed therebetween constitute the capacitor C75. The conductor layers 331, 342, and 343 and the dielectric layer 33 disposed therebetween constitute a capacitor C76. The conductor layers 342 and 351 and the dielectric layer 34 disposed therebetween, and the conductor layers 351 and 362 and the dielectric layer 35 disposed therebetween constitute the capacitor C77. The conductor layers 331, 341, 344 and the dielectric layer 33 arranged therebetween constitute a capacitor C78.

  The LPF 5 shown in FIG. 2 includes conductor layers 295, 296, 302, 324, 325, 365, 366, 373, 383, 384, a ground layer 391, dielectric layers 29 to 38, and dielectric layers 29 to 38. And a plurality of through-holes.

  The conductor layers 295 and 302 and the through holes connecting them form an inductor L51. The conductor layer 296 forms the inductor L52. The conductor layer 383, the ground layer 391, and the dielectric layer 38 disposed therebetween constitute the capacitor C51. The conductor layer 373, the ground layer 391, and the dielectric layers 37 and 38 disposed therebetween constitute a capacitor C52. The conductor layer 384, the ground layer 391, and the dielectric layer 38 disposed therebetween constitute a capacitor C53. The conductor layers 365 and 373 and the dielectric layer 36 disposed therebetween constitute a capacitor C54. The conductor layers 366 and 373 and the dielectric layer 36 disposed therebetween constitute a capacitor C55.

  The transmission line 71 shown in FIG. 2 is composed of a conductor layer 275. One end of the conductor layer 275 includes an open end L34a of the resonator L34, a conductor layer 261 that forms part of the capacitor C34, a conductor layer 281 that forms part of the capacitor C73, and the capacitor C74 via a plurality of through holes. It is connected to the constituent conductor layer 291. The other end of the conductor layer 275 is connected to the conductor layer 214A via the conductor layer 228 and a plurality of through holes.

  The conductor layer 401 constitutes a part of the harmonic signal transmission path 80 shown in FIGS. The phase adjustment portion 401a of the conductor layer 401 constitutes the phase adjustment line 81 shown in FIG. The end 401b1 of the line portion 401b of the conductor layer 401 is connected to the conductor layer 21VC1 through the conductor layers 226 and 232 and a plurality of through holes, and to the inductor L21 through the conductor layers 212A and 224 and the through holes. It is connected. An end 401a1 of the phase adjustment portion 401a of the conductor layer 401 is connected to the conductor layer 21VD via the conductor layer 221 and a plurality of through holes. The conductor layer 401 is further connected to the terminal Vcc through a through hole 401H formed in the dielectric layer 40. The through hole 401H corresponds to the branch point ND shown in FIGS.

  Next, the operation and effect of the high frequency module 2 related to the harmonic signal transmission path 80 will be described in detail while comparing with the high frequency module of the comparative example. First, a high-frequency module of a comparative example will be described with reference to FIG. The high-frequency module of the comparative example does not include the harmonic signal transmission path 80 but includes a power supply terminal Vdd to which a power supply voltage is input separately from the power supply terminal Vcc. In the high-frequency module of this comparative example, the amplifier power supply voltage input terminals 4VC1 and 4VC2 (4VC) of the power amplifier 4 are connected to the power supply terminal Vcc, and the switch power supply voltage input terminal 6VD of the switch 6 is connected to the power supply terminal Vdd. Other configurations of the high-frequency module of the comparative example are the same as those of the high-frequency module 2 according to the present embodiment.

  In the high frequency module of the comparative example, at the time of transmission, the power amplifier 4 and the switch circuit 14 each generate a harmonic signal for the transmission signal. The harmonic signal generated by the power amplifier 4 and directed to the LPF 5 can be attenuated by the LPF 5. However, in the high frequency module of the comparative example, the harmonic signal generated by the switch circuit 14 and directed to the antenna 1 cannot be attenuated.

  Next, the principle of harmonic signal reduction in the high frequency module 2 according to the present embodiment will be described with reference to FIG. Similarly to the high-frequency module of the comparative example, also in the high-frequency module 2 according to the present embodiment, the power amplifier 4 and the switch circuit 14 each generate a harmonic signal for the transmission signal during transmission. In FIG. 16, symbol Hp represents a harmonic signal generated by the power amplifier 4, and symbol Hs represents a harmonic signal generated by the switch circuit 14. In the high frequency module 2, the harmonic signal generated by the power amplifier 4 and directed to the LPF 5 can be attenuated by the LPF 5. In the present embodiment, the harmonic signal generated by the switch circuit 14 and directed to the antenna 1 can be further attenuated based on the following principle. As a result, according to the present embodiment, it is possible to reduce the harmonic signal emitted from the switch 6 to the outside, and as a result, it is possible to reduce the harmonic signal emitted from the antenna 1. Become.

  In the present embodiment, the harmonic signal generated by the power amplifier 4 leaks from the signal output terminal 4b of the power amplifier 4 to the amplifier power supply voltage input terminal 4VC2. The harmonic signal leaking to the amplifier power supply voltage input terminal 4VC2 is transmitted to the switch power supply voltage input terminal 6VD of the switch 6 through the harmonic signal transmission path 80. The harmonic signal transmitted to the switch power supply voltage input terminal 6VD passes through the semiconductor element constituting the decoder 13 and the semiconductor element constituting the switch circuit 14, and leaks to each port 14a, 14b, 14c of the switch circuit 14. . Here, the harmonic signal that appears at the port 14c when the harmonic signal transmitted to the switch power supply voltage input terminal 6VD via the harmonic signal transmission path 80 leaks to the port 14c is referred to as a harmonic signal caused by the power amplifier. .

  On the other hand, the harmonic signal generated by the switch circuit 14 appears at each port 14a, 14b, 14c of the switch circuit 14. Here, the harmonic signal generated by the switch circuit 14 and appearing at the port 14c is referred to as a switch-induced harmonic signal. From the port 14c, a harmonic signal (hereinafter referred to as a synthesized harmonic signal) formed by synthesizing the harmonic signal derived from the power amplifier and the harmonic signal derived from the switch is output.

  According to the present embodiment, it is possible to make the intensity of the synthesized harmonic signal smaller than the intensity of the harmonic signal caused by the switch by adjusting the phase and intensity of the harmonic signal caused by the power amplifier. Especially when the phase of the harmonic signal from the power amplifier is 180 ° different from the phase of the harmonic signal from the switch, and the intensity of the harmonic signal from the power amplifier is equal to the intensity of the harmonic signal from the switch. The intensity of the harmonic signal becomes zero. When the intensity of the harmonic signal from the power amplifier is different from the intensity of the harmonic signal from the switch, the synthesis is performed when the phase of the harmonic signal from the power amplifier is 180 ° different from the phase of the harmonic signal from the switch. The intensity of the harmonic signal is the smallest. In the present embodiment, the length of the harmonic signal transmission path 80 can be adjusted by adjusting the length of the phase adjustment line 81, and thereby the phase of the harmonic signal originating from the power amplifier can be adjusted. In the present embodiment, it is preferable to adjust the length of the phase adjustment line 81 so that the phase of the harmonic signal caused by the power amplifier differs from the phase of the harmonic signal caused by the switch by 180 °. Note that the phase difference between the harmonic signal caused by the power amplifier and the harmonic signal caused by the switch is ideally 180 °, but may be a value close to 180 °. When the frequency of the transmission signal can take a plurality of values within a predetermined frequency band, the phase of the harmonic signal due to the power amplifier is caused by switching with respect to the harmonic signal with respect to the signal of one frequency within the predetermined frequency band. The phase of the higher harmonic signal may be different by 180 °.

  When the phase difference between the harmonic signal caused by the power amplifier and the harmonic signal caused by the switch is 180 °, the combined harmonic becomes stronger as the intensity of the harmonic signal caused by the power amplifier is closer to the intensity of the harmonic signal caused by the switch. The signal strength is reduced. The intensity of the harmonic signal derived from the power amplifier can be adjusted by adjusting the values of the inductor L21 and the capacitors C21, C22, and C23. Therefore, in the present embodiment, by adjusting the values of the inductor L21 and the capacitors C21, C22, and C23 within a range where the operation of the power amplifier 4 does not become unstable, the intensity of the harmonic signal caused by the power amplifier is switched. It is preferable to approximate the intensity of the resulting harmonic signal.

  As described above, according to the present embodiment, the harmonic signal generated by the switch circuit 14 and directed to the antenna 1 can be attenuated. In the present embodiment, it is not necessary to provide an extra line for adjusting the phase of the harmonic signal in the path of the output signal of the power amplifier 4. Therefore, according to the present embodiment, it is possible to reduce the harmonic signal emitted from the switch 6 to the outside without increasing the insertion loss of the path of the output signal of the power amplifier 4, and as a result, The harmonic signal emitted from the antenna 1 can be reduced.

  Further, according to the present embodiment, the amplifier power supply voltage input terminal 4VC and the switch power supply voltage input terminal 6VD are both connected to the power supply terminal Vcc, so that the power supply terminal for the power amplifier 4 and the switch 6 are connected to the high frequency module 2. The number of power supply terminals can be reduced as compared with the case where a power supply terminal is provided. Thereby, according to this Embodiment, the high frequency module 2 can be reduced in size.

  In the high-frequency module 2 according to the present embodiment, the power amplifier 4 and the switch 6 are mounted on the multilayer substrate 20, and the harmonic signal transmission path 80 is disposed inside the multilayer substrate 20. The high frequency module 2 includes a BPF 3 and an LPF 5 as circuits arranged inside the laminated substrate 20. The multilayer substrate 20 is disposed between the circuit (BPF 3 and LPF 5) disposed inside the multilayer substrate 20 and the conductor layer 401 constituting a part of the harmonic signal transmission path 80 and is connected to the ground. The ground layer 391 is included. According to the present embodiment, the circuit (BPF 3 and LPF 5) arranged in the laminated substrate 20 and the conductor layer 401 can be separated at high frequency by the ground layer 391. This prevents the harmonic signal transmitted by the conductor layer 401 from affecting the circuit disposed inside the multilayer substrate 20 and degrading the characteristics of the circuit disposed inside the multilayer substrate 20. Can do.

  In this embodiment, when the intensity of the harmonic signal caused by the switch is too large compared to the intensity of the harmonic signal caused by the power amplifier, the harmonic signal transmission path 80 in the present embodiment is used. The harmonic signal emitted from the antenna 1 may be reduced by using a method for reducing the harmonic signal in combination with another method. As another method that can be used in combination, for example, by adjusting the length of the signal transmission line between the output terminal of the LPF 5 and the terminal 6a of the switch 6, the signal is generated in the switch circuit 14, reflected by the LPF 5, Method for reducing the intensity of a harmonic signal originating from a switch formed by synthesizing a harmonic signal that passes through the circuit 14 toward the antenna 1 and a harmonic signal generated by the switch circuit 14 and directly toward the antenna 1 There is. When trying to reduce the harmonic signal emitted from the antenna 1 only by this method, the length of the signal transmission line between the output end of the LPF 5 and the terminal 6a of the switch 6 is limited to a predetermined length, As a result, there is a risk of increasing the insertion loss of the transmission signal path. However, when the harmonic signal reduction method of the present embodiment and the method of adjusting the length of the signal transmission line between the output end of the LPF 5 and the terminal 6a of the switch 6 are used together, Since the intensity of the harmonic signal caused by the switch may be reduced to some extent by adjusting the length, the degree of freedom in setting the length of the signal transmission line is increased. Therefore, in this case, it is possible to reduce the harmonic signal emitted from the antenna 1 while suppressing an increase in insertion loss of the transmission signal path.

[Second Embodiment]
Next, a high frequency module according to a second embodiment of the present invention will be described with reference to FIG. FIG. 17 is a block diagram showing a circuit configuration of the high-frequency module 102 according to the present embodiment. The high-frequency module 102 according to the present embodiment includes phase adjustment lines 82 and 83 instead of the phase adjustment line 81 in the first embodiment. The phase adjustment line 82 is inserted in a portion of the harmonic signal transmission path 80 between the connection point of the inductor 21 and the capacitors C21 and C22 and the branch point ND shown in FIG. The phase adjustment line 83 is inserted in a portion of the harmonic signal transmission path 80 between the branch point ND and the switch power supply voltage input terminal 6VD. Similarly to the phase adjustment line 81 in the first embodiment, each of the phase adjustment lines 82 and 83 can be configured using a conductor layer provided in the multilayer substrate 20. Further, the phase adjustment lines 82 and 83 can be formed in a meander shape like the phase adjustment line 81, for example.

  In the present embodiment, the length of the harmonic signal transmission path 80 can be adjusted by adjusting the lengths of the phase adjustment lines 82 and 83, thereby adjusting the phase of the harmonic signal caused by the power amplifier. it can. According to the present embodiment, it is easier to adjust the phase of the harmonic signal caused by the power amplifier than in the first embodiment. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

[Third Embodiment]
Next, a high frequency module according to a third embodiment of the present invention will be described with reference to FIG. FIG. 18 is a block diagram showing a circuit configuration of the high-frequency module 112 according to the present embodiment. The high-frequency module 112 according to the present embodiment constitutes a part of a high-frequency circuit unit in a time-division duplex wireless communication apparatus, and processes first and second transmission signals having different frequency bands. .

  The high-frequency module 112 according to the present embodiment includes an antenna terminal ANT, a pair of transmission signal terminals Tx11 and Tx12 to which a first transmission signal in the form of a balanced signal is input, and a second transmission signal in the form of a balanced signal. Is provided with a pair of transmission signal terminals Tx21 and Tx22, a power supply terminal Vcc, and a switch control terminal V1.

  The high-frequency module 112 further includes two BPFs 3A and 3B, two power amplifiers 4A and 4B, two LPFs 5A and 5B, and three phase adjustment lines 84A, 84B, and 85. The phase adjustment lines 84A, 84B, 85 can be configured using a conductor layer provided in the multilayer substrate 20, similarly to the phase adjustment line 81 in the first embodiment. Further, the phase adjustment lines 84A, 84B, and 85 can be formed in a meander shape like the phase adjustment line 81, for example.

  The BPF 3A has a pair of input ports and an output port. A pair of input ports of the BPF 3A are connected to transmission signal output terminals Tx11 and Tx12, respectively. The BPF 3A has a pass band corresponding to the frequency band of the first transmission signal, and selectively passes a signal having a frequency within the pass band. The power amplifier 4A has a signal input terminal 4Aa, a signal output terminal 4Ab, and an amplifier power supply voltage input terminal 4AVC. The signal input terminal 4Aa is connected to the output port of the BPF 3A. The signal output terminal 4Ab is connected to the terminal 6a of the switch 6 through the LPF 5A. The amplifier power supply voltage input terminal 4AVC is connected to the power supply terminal Vcc via the phase adjustment line 84A.

  The BPF 3B has a pair of input ports and an output port. A pair of input ports of the BPF 3B are connected to transmission signal output terminals Tx21 and Tx22, respectively. The BPF 3B has a pass band corresponding to the frequency band of the second transmission signal, and selectively passes a signal having a frequency within the pass band. The power amplifier 4B has a signal input terminal 4Ba, a signal output terminal 4Bb, and an amplifier power supply voltage input terminal 4BVC. The signal input terminal 4Ba is connected to the output port of the BPF 3B. The signal output terminal 4Bb is connected to the terminal 6b of the switch 6 through the LPF 5B. The amplifier power supply voltage input terminal 4BVC is connected to the power supply terminal Vcc via the phase adjustment line 84B.

  The configurations of the BPFs 3A and 3B are the same as the BPF 3 in the first embodiment, for example. The configuration of the power amplifiers 4A and 4B is the same as that of the power amplifier 4 in the first embodiment, for example. The power amplifier 4A corresponds to the power amplifier in the present invention, and the power amplifier 4B corresponds to the second power amplifier in the present invention. The amplifier power supply voltage input terminal 4AVC corresponds to the amplifier power supply voltage input terminal in the present invention, and the amplifier power supply voltage input terminal 4BVC corresponds to the second amplifier power supply voltage input terminal in the present invention. The configuration of the LPFs 5A and 5B is the same as that of the LPF 5 in the first embodiment, for example. Instead of the LPFs 5A and 5B, BPFs may be provided.

  In the present embodiment, the switch power supply voltage input terminal 6VD of the switch 6 is connected to the power supply terminal Vcc via the phase adjustment line 85. Here, a branch point between the line extending from the power supply terminal Vcc to the terminal 4AVC and the line extending from the power supply terminal Vcc to the terminal 6VD is represented by the symbol ND1. A branch point between a line extending from the power supply terminal Vcc to the terminal 4BVC and a line extending from the power supply terminal Vcc to the terminal 6VD is represented by a symbol ND2.

  In the high-frequency module 112 according to the present embodiment, the amplifier power supply voltage input terminal 4AVC and the switch power supply voltage input terminal 6VD are connected to the power supply terminal Vcc. And a first harmonic signal transmission path for transmitting a harmonic signal generated by the power amplifier 4A and leaking to the amplifier power supply voltage input terminal 4AVC to the switch power supply voltage input terminal 6VD. The first harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4AVC to the switch power supply voltage input terminal 6VD via the phase adjustment line 84A, the branch point ND1, and the phase adjustment line 85. In order to prevent the harmonic signal flowing from the amplifier power supply voltage input terminal 4AVC to the first harmonic signal transmission path from being reflected at the start point of the first harmonic signal transmission path, the first harmonic signal transmission path The characteristic impedance of the high-frequency module 112 is preferably equal to or close to the characteristic impedance of the main transmission line. For example, when the characteristic impedance of the main transmission line in the high-frequency module 112 is 50Ω, the characteristic impedance of the first harmonic signal transmission path is preferably 50Ω or a value close to 50Ω. The first harmonic signal transmission path corresponds to the transmission path in the present invention.

  Further, the high frequency module 112 according to the present embodiment includes the amplifier power supply voltage input terminal 4BVC and the switch power supply voltage input terminal by connecting the amplifier power supply voltage input terminal 4BVC and the switch power supply voltage input terminal 6VD to the power supply terminal Vcc. And a second harmonic signal transmission path for transmitting a harmonic signal generated by the power amplifier 4B and leaking to the amplifier power supply voltage input terminal 4BVC to the switch power supply voltage input terminal 6VD. The second harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4BVC to the switch power supply voltage input terminal 6VD via the phase adjustment line 84B, the branch point ND2, and the phase adjustment line 85. In order to prevent the harmonic signal flowing from the amplifier power supply voltage input terminal 4BVC to the second harmonic signal transmission path from being reflected at the starting point of the second harmonic signal transmission path, the second harmonic signal transmission path The characteristic impedance of the high-frequency module 112 is preferably equal to or close to the characteristic impedance of the main transmission line. For example, when the characteristic impedance of the main transmission line in the high-frequency module 112 is 50Ω, the characteristic impedance of the second harmonic signal transmission path is preferably 50Ω or a value close to 50Ω. The second harmonic signal transmission path corresponds to the second transmission path in the present invention.

  Next, the operation and effect of the high frequency module 112 according to the present embodiment will be described. When the first transmission signal is transmitted, the port 14c of the switch circuit 14 is connected to the port 14a. In this case, the first transmission signal in the form of a balanced signal output from the RFIC passes through the pair of first transmission signal terminals Tx11 and Tx12 and is input to the BPF 3A. The first transmission signal in the form of an unbalanced signal is output by the BPF 3A. Is converted into a transmission signal. The first transmission signal in the form of this unbalanced signal is amplified by the power amplifier 4A, passes through the LPF 5A, the switch 6 and the antenna terminal ANT in order, is supplied to the antenna 1, and is transmitted from the antenna 1.

  At the time of transmitting the first transmission signal, the power amplifier 4A and the switch circuit 14 each generate a harmonic signal for the first transmission signal. The harmonic signal generated by the power amplifier 4A and directed to the LPF 5A can be attenuated by the LPF 5A. The harmonic signal generated by the power amplifier 4A leaks from the signal output terminal 4Ab of the power amplifier 4A to the amplifier power supply voltage input terminal 4AVC. The harmonic signal leaking to the amplifier power supply voltage input terminal 4AVC is transmitted to the switch power supply voltage input terminal 6VD of the switch 6 through the first harmonic signal transmission path. The harmonic signal transmitted to the switch power supply voltage input terminal 6VD passes through the semiconductor element constituting the decoder 13 and the semiconductor element constituting the switch circuit 14, and leaks to each port 14a, 14b, 14c of the switch circuit 14. . Here, when the harmonic signal transmitted to the switch power supply voltage input terminal 6VD via the first harmonic signal transmission path leaks to the port 14c, the harmonic signal appearing at the port 14c is attributed to the first power amplifier. Called harmonic signal.

  The harmonic signal generated by the switch circuit 14 at the time of transmission of the first transmission signal appears at each port 14a, 14b, 14c of the switch circuit 14. Here, the harmonic signal generated by the switch circuit 14 and appearing at the port 14c is referred to as a harmonic signal derived from the first switch. From the port 14c, a harmonic signal formed by synthesizing a harmonic signal derived from the first power amplifier and a harmonic signal derived from the first switch (hereinafter referred to as a first synthesized harmonic signal). Is output.

  In the present embodiment, the first synthesized harmonic signal is adjusted by adjusting the phase and intensity of the harmonic signal derived from the first power amplifier in accordance with the principle of harmonic signal reduction described in the first embodiment. Can be made smaller than the intensity of the harmonic signal caused by the first switch. In the present embodiment, the length of the first harmonic signal transmission path can be adjusted by adjusting the lengths of the phase adjustment lines 84A and 85, and thereby the phase of the harmonic signal caused by the first power amplifier. Can be adjusted. In the present embodiment, by adjusting the lengths of the phase adjustment lines 84A and 85, the phase of the harmonic signal caused by the first power amplifier is made 180 ° different from the phase of the harmonic signal caused by the first switch. It is preferable.

  Further, when transmitting the second transmission signal, the port 14c of the switch circuit 14 is connected to the port 14b. In this case, the second transmission signal in the form of a balanced signal output from the RFIC passes through the pair of second transmission signal terminals Tx21 and Tx22 and is input to the BPF 3B, and the second transmission signal in the form of an unbalanced signal is output by the BPF 3B. Is converted into a transmission signal. The second transmission signal in the form of this unbalanced signal is amplified by the power amplifier 4B, supplied to the antenna 1 through the LPF 5B, the switch 6 and the antenna terminal ANT in order, and transmitted from the antenna 1.

  At the time of transmission of the second transmission signal, the power amplifier 4B and the switch circuit 14 each generate a harmonic signal for the second transmission signal. The harmonic signal generated by the power amplifier 4B and directed to the LPF 5B can be attenuated by the LPF 5B. The harmonic signal generated by the power amplifier 4B leaks from the signal output terminal 4Bb of the power amplifier 4B to the amplifier power supply voltage input terminal 4BVC. The harmonic signal leaking to the amplifier power supply voltage input terminal 4BVC is transmitted to the switch power supply voltage input terminal 6VD of the switch 6 through the second harmonic signal transmission path. The harmonic signal transmitted to the switch power supply voltage input terminal 6VD passes through the semiconductor element constituting the decoder 13 and the semiconductor element constituting the switch circuit 14, and leaks to each port 14a, 14b, 14c of the switch circuit 14. . Here, when the harmonic signal transmitted to the switch power supply voltage input terminal 6VD via the second harmonic signal transmission path leaks to the port 14c, the harmonic signal appearing at the port 14c is attributed to the second power amplifier. Called harmonic signal.

  The harmonic signal generated by the switch circuit 14 at the time of transmission of the second transmission signal appears at each port 14a, 14b, 14c of the switch circuit 14. Here, the harmonic signal generated by the switch circuit 14 and appearing at the port 14c is referred to as a harmonic signal derived from the second switch. From the port 14c, a harmonic signal formed by synthesizing the harmonic signal derived from the second power amplifier and the harmonic signal derived from the second switch (hereinafter referred to as a second synthesized harmonic signal). Is output.

  In the present embodiment, the second synthesized harmonic signal is obtained by adjusting the phase and intensity of the harmonic signal derived from the second power amplifier in accordance with the principle of harmonic signal reduction described in the first embodiment. Can be made smaller than the intensity of the harmonic signal caused by the second switch. In the present embodiment, the length of the second harmonic signal transmission path can be adjusted by adjusting the lengths of the phase adjustment lines 84B and 85, and thereby the phase of the harmonic signal caused by the second power amplifier. Can be adjusted. In the present embodiment, by adjusting the lengths of the phase adjustment lines 84B and 85, the phase of the harmonic signal caused by the second power amplifier is made 180 ° different from the phase of the harmonic signal caused by the second switch. It is preferable.

  In the present embodiment, the lengths of the phase adjustment lines 84A and 84B can be adjusted independently of each other, thereby adjusting the lengths of the first and second harmonic signal transmission paths independently of each other. be able to. Therefore, according to the present embodiment, it is possible to reduce the harmonic signal emitted from antenna 1 both when the first transmission signal is transmitted and when the second transmission signal is transmitted. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

[Fourth Embodiment]
Next, with reference to FIG. 19, the high frequency module which concerns on the 4th Embodiment of this invention is demonstrated. FIG. 19 is a block diagram showing a circuit configuration of the high-frequency module 122 according to the present embodiment. The high-frequency module 122 according to the present embodiment constitutes a part of a high-frequency circuit unit in a time-division duplex wireless communication apparatus, and the first and second transmission signals having different frequency bands and the frequency bands of each other. Different first and second received signals are processed.

  The high-frequency module 122 according to the present embodiment includes a switch 9 instead of the switch 6 in the third embodiment. Further, the high frequency module 122 according to the present embodiment outputs a first reception signal in the form of an unbalanced signal in addition to the components of the component 112 of the high frequency module according to the third embodiment. Reception signal terminal Rx1, a second reception signal terminal Rx2 that outputs a second reception signal in the form of an unbalanced signal, and a switch control terminal V2.

  The switch 9 includes terminals 9a, 9b, 9c, 9d, and 9e, a switch power supply voltage input terminal 9VD, switch control signal input terminals 9V1 and 9V2, a decoder 15, and a single-pole four-throw switch circuit 16. is doing. The terminal 9a is connected to the signal output terminal 4Ab of the power amplifier 4A via the LPF 5A. The terminal 9b is connected to the signal output terminal 4Bb of the power amplifier 4B through the LPF 5B. The terminal 9c is connected to the first reception signal terminal Rx1. The terminal 9d is connected to the second reception signal terminal Rx2. The terminal 9e is connected to the antenna terminal ANT. The switch power supply voltage input terminal 9VD is connected to the power supply terminal Vcc via the phase adjustment line 85. The first switch control signal is input to the switch control signal input terminal 9V1, and the second switch control signal is input to the switch control signal input terminal 9V2.

  The switch circuit 16 includes ports 16a, 16b, 16c, 16d, and 16e, and selectively connects the port 16e to any of the ports 16a, 16b, 16c, and 16d. The port 16a is connected to the terminal 9a. The port 16b is connected to the terminal 9b. The port 16c is connected to the terminal 9c. The port 16d is connected to the terminal 9d. The port 16e is connected to the terminal 9e.

  The decoder 15 is configured by a logic circuit. Accordingly, the decoder 15 corresponds to the logic circuit in the present invention. The decoder 15 is connected to the terminals 9VD, 9V1, and 9V2 and to the switch circuit 16. The decoder 15 operates by being supplied with the power supply voltage via the power supply terminal Vcc, the phase adjustment line 85 and the terminal 9VD, and the first switch control signal input via the terminals V1 and 9V1 and the terminal V2. , 9V2 is used to generate four signals for determining two ports to be connected in the switch circuit 16 based on the second switch control signal inputted via 9V2 and output to the switch circuit 16.

  The switch circuit 16 is configured using an FET. The switch 9 is composed of a semiconductor IC, particularly an MMIC.

  The high frequency module 122 according to the present embodiment includes first and second harmonic signal transmission paths, as in the third embodiment. The first harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4AVC to the switch power supply voltage input terminal 9VD via the phase adjustment line 84A, the branch point ND1, and the phase adjustment line 85. The second harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4BVC to the switch power supply voltage input terminal 9VD via the phase adjustment line 84B, the branch point ND2, and the phase adjustment line 85.

  Next, main operations of the high-frequency module 122 according to the present embodiment will be described. When transmitting the first transmission signal, the port 16e of the switch circuit 16 is connected to the port 16a. When transmitting the second transmission signal, the port 16e of the switch circuit 16 is connected to the port 16b. The operation at the time of transmitting the first transmission signal and at the time of transmitting the second transmission signal is the same as that of the third embodiment.

  When receiving the first reception signal, the port 16e of the switch circuit 16 is connected to the port 16c. In this case, the first reception signal received by the antenna 1 passes through the antenna terminal ANT, the switch 9 and the first reception signal terminal Rx1 in order and is input to the RFIC. When receiving the second received signal, the port 16e of the switch circuit 16 is connected to the port 16d. In this case, the second received signal received by the antenna 1 passes through the antenna terminal ANT, the switch 9 and the second received signal terminal Rx2 in order and is input to the RFIC.

  The configuration in which the paths of a plurality of transmission signals and a plurality of reception signals are switched by a switch as in this embodiment can easily cope with an increase in the frequency band processed by the high-frequency module by increasing the number of switch ports. There is an advantage that you can. Other configurations, operations, and effects in the present embodiment are the same as those in the third embodiment.

[Fifth Embodiment]
Next, with reference to FIG. 20, the high frequency module which concerns on the 5th Embodiment of this invention is demonstrated. FIG. 20 is a block diagram showing a circuit configuration of the high frequency module 132 according to the present embodiment. Similarly to the fourth embodiment, the high-frequency module 132 according to the present embodiment constitutes a part of the high-frequency circuit unit in the time-division duplex wireless communication apparatus, and the first and second frequency bands differing from each other. 2 transmission signals and first and second reception signals having different frequency bands are processed. In the present embodiment, the frequency band of the second transmission signal is higher than the frequency band of the first transmission signal, and the frequency band of the second reception signal is higher than the frequency band of the first reception signal.

  The high-frequency module 132 according to the present embodiment includes diplexers 51 and 52 and the switch 6 according to the first embodiment, instead of the LPF 5A and LPF 5B and the switch 9 according to the fourth embodiment.

  The diplexer 51 includes first to third ports, an LPF 51A, and a high-pass filter (hereinafter referred to as HPF) 51B. The first port is connected to the signal output terminal 4Ab of the power amplifier 4A. The LPF 51A is provided between the first port and the third port. The second port is connected to the signal output terminal 4Bb of the power amplifier 4B. The HPF 51B is provided between the second port and the third port. The third port is connected to the terminal 6 a of the switch 6.

  The diplexer 52 has first to third ports, an LPF 52A, and an HPF 52B. The first port is connected to the first reception signal terminal Rx1. The LPF 52A is provided between the first port and the third port. The second port is connected to the second reception signal terminal Rx2. The HPF 52B is provided between the second port and the third port. The third port is connected to the terminal 6 b of the switch 6.

  The high-frequency module 132 according to the present embodiment includes first and second harmonic signal transmission paths as in the third embodiment.

  Next, main operations of the high-frequency module 132 according to the present embodiment will be described. During transmission of the first transmission signal and transmission of the second transmission signal, the port 14c of the switch circuit 14 is connected to the port 14a. In this case, the first transmission signal in the form of a balanced signal output from the RFIC passes through the pair of first transmission signal terminals Tx11 and Tx12 and is input to the BPF 3A. The first transmission signal in the form of an unbalanced signal is output by the BPF 3A. Is converted into a transmission signal. The first transmission signal in the form of an unbalanced signal is supplied to the antenna 1 through the power amplifier 4A, the LPF 51A of the diplexer 51, the switch 6 and the antenna terminal ANT in this order, and is transmitted from the antenna 1.

  The second transmission signal in the form of a balanced signal output from the RFIC passes through the pair of second transmission signal terminals Tx21 and Tx21 and is input to the BPF 3B, and the second transmission signal in the form of an unbalanced signal is output by the BPF 3B. It is converted into a transmission signal. The second transmission signal in the form of this unbalanced signal is supplied to the antenna 1 through the power amplifier 4B, the HPF 51B of the diplexer 51, the switch 6 and the antenna terminal ANT in this order, and is transmitted from the antenna 1.

  When receiving the first received signal and when receiving the second received signal, the port 14c of the switch circuit 14 is connected to the port 14b. In this case, the first received signal received by the antenna 1 passes through the antenna terminal ANT, the switch 6, the LPF 52A of the diplexer 52, and the first received signal terminal Rx1 in order, and is input to the RFIC. The second received signal received by the antenna 1 passes through the antenna terminal ANT, the switch 6, the HPF 52B of the diplexer 52, and the second received signal terminal Rx2 in this order and is input to the RFIC.

  In the above description, the diplexers 51 and 52 have been described as being configured by LPF and HPF, but the diplexers 51 and 52 may be configured as follows. First, in the diplexer 51, the HPF 51B cannot attenuate the harmonic signal generated by the power amplifier 4B. Therefore, when it is desired to attenuate the harmonic signal generated by the power amplifier 4B in the diplexer 51, the BPF is used instead of the HPF 51B. Accordingly, in this case, the diplexer 51 is configured by the LPF 51A and the BPF. Further, in the diplexer 51, when it is desired to attenuate an unnecessary signal having a frequency lower than the frequency band of the transmission signal, the BPF is used instead of the LPF 51A. Accordingly, in this case, the diplexer 51 is configured by two BPFs. Further, in order to prevent deterioration in reception sensitivity of a reception circuit (for example, a low noise amplifier in the RFIC) to which the first and second reception signals output from the reception signal terminals Rx1 and Rx2 are input, the diplexer 52 is provided with two BPFs. You may comprise by.

  Further, in the high-frequency module 132 according to the present embodiment, when a triplexer is provided in place of the diplexers 51 and 52, it is possible to deal with three frequency bands. Other configurations, operations, and effects in the present embodiment are the same as those in the third embodiment.

[Sixth Embodiment]
Next, a high frequency module according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 21 is a block diagram showing a circuit configuration of the high-frequency module 142 according to the present embodiment. High-frequency module 142 according to the present embodiment constitutes a part of a high-frequency circuit unit in a frequency division duplex (FDD) type wireless communication apparatus, and the first and second transmissions having different frequency bands from each other. The signal and the first and second received signals having different frequency bands are processed. In the present embodiment, the first frequency band includes the frequency band of the first transmission signal and the frequency band of the first reception signal, and the second transmission is performed in a second frequency band different from the first frequency band. The frequency band of the signal and the frequency band of the second received signal are included. The frequency band of the first reception signal is higher than the frequency band of the first transmission signal, and the frequency band of the second reception signal is higher than the frequency band of the second transmission signal.

  The high-frequency module 142 according to the present embodiment includes duplexers 53A and 53B instead of the diplexers 51 and 52 in the fifth embodiment. The duplexer 53A includes first to third ports, an LPF 53A1, and an HPF 53A2. The first port is connected to the signal output terminal 4Ab of the power amplifier 4A. The LPF 53A1 is provided between the first port and the third port. The second port is connected to the first reception signal terminal Rx1. The HPF 53A2 is provided between the second port and the third port. The third port is connected to the terminal 6 a of the switch 6.

  The duplexer 53B has first to third ports, an LPF 53B1, and an HPF 53B2. The first port is connected to the signal output terminal 4Bb of the power amplifier 4B. The LPF 53B1 is provided between the first port and the third port. The second port is connected to the second reception signal terminal Rx2. The HPF 53B2 is provided between the second port and the third port. The third port is connected to the terminal 6 b of the switch 6.

  Next, main operations of the high-frequency module 142 according to the present embodiment will be described. During transmission of the first transmission signal and reception of the first reception signal, the port 14c of the switch circuit 14 is connected to the port 14a. In this case, the first transmission signal in the form of a balanced signal output from the RFIC passes through the pair of first transmission signal terminals Tx11 and Tx12 and is input to the BPF 3A. The first transmission signal in the form of an unbalanced signal is output by the BPF 3A. Is converted into a transmission signal. The first transmission signal in the form of an unbalanced signal is supplied to the antenna 1 through the power amplifier 4A, the LPF 53A1 of the duplexer 53A, the switch 6 and the antenna terminal ANT in this order, and is transmitted from the antenna 1. The first received signal received by the antenna 1 passes through the antenna terminal ANT, the switch 6, the HPF 53A2 of the duplexer 53A, and the first received signal terminal Rx1 in order, and is input to the RFIC.

  When transmitting the second transmission signal and receiving the second reception signal, the port 14c of the switch circuit 14 is connected to the port 14b. In this case, the second transmission signal in the form of a balanced signal output from the RFIC passes through the pair of second transmission signal terminals Tx21 and Tx22 and is input to the BPF 3B, and the second transmission signal in the form of an unbalanced signal is output by the BPF 3B. Is converted into a transmission signal. The second transmission signal in the form of this unbalanced signal is supplied to the antenna 1 through the power amplifier 4B, the LPF 53B1 of the duplexer 53B, the switch 6 and the antenna terminal ANT in this order, and is transmitted from the antenna 1. The second received signal received by the antenna 1 passes through the antenna terminal ANT, the switch 6, the HPF 53B2 of the duplexer 53B, and the second received signal terminal Rx2 in order, and is input to the RFIC.

  In the present embodiment, transmission of the first transmission signal and reception of the first reception signal can be performed simultaneously, and transmission of the second transmission signal and reception of the second reception signal can be performed simultaneously. it can. In the high frequency module 142 according to the present embodiment, it is possible to easily cope with an increase in the frequency band processed by the high frequency module 142 by increasing the number of ports of the switch 6.

  In the above description, the duplexers 53A and 53B have been described as being configured by LPF and HPF, but the duplexers 53A and 53B may be configured as follows. The duplexer separates a transmission signal and a reception signal, and is used in a frequency division duplex system such as a W-CDMA (Wideband-Code Division Multiple Access) system. Since the frequency band of the transmission signal and the frequency band of the reception signal are very close, the duplexer has two BPFs composed of surface acoustic wave filters whose insertion loss characteristics change from the pass band to the outside of the pass band very steeply. Many are used. Each of the duplexers 53A and 53B in the present embodiment may also be configured by two BPFs each formed of a surface acoustic wave filter, for example. Other configurations, operations, and effects in the present embodiment are the same as those in the fifth embodiment.

[Seventh Embodiment]
Next, with reference to FIG. 22, the high frequency module which concerns on the 7th Embodiment of this invention is demonstrated. FIG. 22 is a block diagram showing a circuit configuration of the high-frequency module 152 according to the present embodiment. High-frequency module 152 according to the present embodiment constitutes a part of a high-frequency circuit unit in a time-division duplex wireless communication device, and includes first and second transmission signals having different frequency bands, Different first and second received signals are processed. In the present embodiment, the first frequency band includes the frequency band of the first transmission signal and the frequency band of the first reception signal, and the second frequency band higher than the first frequency band includes the second frequency band. The frequency band of the transmission signal and the frequency band of the second reception signal are included.

  The high-frequency module 152 according to the present embodiment includes two power supply terminals VCA and VCB, two switch control terminals V1A and V1B, instead of the power supply terminal Vcc, the switch control terminal V1, and the switch 6 in the sixth embodiment. Two switches 6A and 6B are provided. The high-frequency module 152 includes a diplexer 54 and phase adjustment lines 86A, 86B, 87A, and 87B instead of the duplexers 53A and 53B and the phase adjustment lines 84A, 84B, and 85 in the sixth embodiment.

  The terminal 4AVC of the power amplifier 4A is connected to the power supply terminal VCA via the phase adjustment line 86A. The terminal 4BVC of the power amplifier 4B is connected to the power supply terminal VCB via the phase adjustment line 86B.

  The switch 6A includes terminals 6Aa, 6Ab, and 6Ac, a switch power supply voltage input terminal 6AVD, a switch control signal input terminal 6AV1, a decoder 13A, and a single-pole double-throw switch circuit 14A. The terminal 6Aa is connected to the signal output terminal 4Ab of the power amplifier 4A. The terminal 6Ab is connected to the first reception signal terminal Rx1. The terminal 6Ac is connected to the diplexer 54. The terminal 6AVD is connected to the power supply terminal VCA via the phase adjustment line 87A. The terminal 6AV1 is connected to the switch control terminal V1A.

  The switch circuit 14A includes ports 14Aa, 14Ab, and 14Ac, and selectively connects the port 14Ac to one of the ports 14Aa and 14Ab. The port 14Aa is connected to the terminal 6Aa. The port 14Ab is connected to the terminal 6Ab. The port 14Ac is connected to the terminal 6Ac.

  The decoder 13A is configured by a logic circuit. Therefore, the decoder 13A corresponds to the logic circuit in the present invention. The decoder 13A is connected to terminals 6AVD and 6AV1 and to the switch circuit 14A. The decoder 13A operates when a power supply voltage is supplied through the power supply terminal VCA, the phase adjustment line 87A, and the terminal 6AVD, and based on the switch control signal input through the terminals V1A and 6AV1. Two signals for determining two ports connected in 14A are generated and output to switch circuit 14A.

  The switch 6B has terminals 6Ba, 6Bb, 6Bc, a switch power supply voltage input terminal 6BVD, a switch control signal input terminal 6BV1, a decoder 13B, and a single-pole double-throw switch circuit 14B. The terminal 6Ba is connected to the signal output terminal 4Bb of the power amplifier 4B. The terminal 6Bb is connected to the second reception signal terminal Rx2. The terminal 6Bc is connected to the diplexer 54. The terminal 6BVD is connected to the power supply terminal VCB via the phase adjustment line 87B. The terminal 6BV1 is connected to the switch control terminal V1B.

  The switch circuit 14B includes ports 14Ba, 14Bb, and 14Bc, and selectively connects the port 14Bc to one of the ports 14Ba and 14Bb. The port 14Ba is connected to the terminal 6Ba. The port 14Bb is connected to the terminal 6Bb. The port 14Bc is connected to the terminal 6Bc.

  The decoder 13B is configured by a logic circuit. Therefore, the decoder 13B corresponds to the logic circuit in the present invention. The decoder 13B is connected to terminals 6BVD and 6BV1 and to the switch circuit 14B. The decoder 13B operates by being supplied with the power supply voltage via the power supply terminal VCB, the phase adjustment line 87B and the terminal 6BVD, and based on the switch control signal input via the terminals V1B and 6BV1. Two signals for determining two ports connected in 14B are generated and output to the switch circuit 14B.

  The configuration of the switches 6A and 6B is the same as that of the switch 6 in the first embodiment. The switch circuits 14A and 14B are configured using FETs. The switches 6A and 6B are constituted by a semiconductor IC, particularly an MMIC.

  In the present embodiment, both the amplifier power supply voltage input terminal 4AVC and the switch power supply voltage input terminal 6AVD are connected to the power supply terminal VCA, and both the amplifier power supply voltage input terminal 4BVC and the switch power supply voltage input terminal 6BVD are connected to the power supply terminal VCB. Yes. Here, a branch point between a line extending from the power supply terminal VCA to the terminal 4AVC and a line extending from the power supply terminal VCA to the terminal 6AVD is represented by a symbol ND1. A branch point between the line extending from the power supply terminal VCB to the terminal 4BVC and the line extending from the power supply terminal VCB to the terminal 6BVD is represented by the symbol ND2.

  In the high-frequency module 152 according to the present embodiment, the amplifier power supply voltage input terminal 4AVC and the switch power supply voltage input terminal 6AVD are connected to the power supply terminal VCA. And a first harmonic signal transmission path for transmitting a harmonic signal generated by the power amplifier 4A and leaking to the amplifier power supply voltage input terminal 4AVC to the switch power supply voltage input terminal 6AVD. The first harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4AVC to the switch power supply voltage input terminal 6AVD via the phase adjustment line 86A, the branch point ND1, and the phase adjustment line 87A. In order to prevent the harmonic signal flowing from the amplifier power supply voltage input terminal 4AVC to the first harmonic signal transmission path from being reflected at the start point of the first harmonic signal transmission path, the first harmonic signal transmission path Is preferably equal to or close to the characteristic impedance of the main transmission line in the high-frequency module 152. For example, when the characteristic impedance of the main transmission line in the high-frequency module 152 is 50Ω, the characteristic impedance of the first harmonic signal transmission path is preferably 50Ω or a value close to 50Ω.

  Further, the high frequency module 152 according to the present embodiment is configured such that the amplifier power supply voltage input terminal 4BVC and the switch power supply voltage input terminal are connected by connecting the amplifier power supply voltage input terminal 4BVC and the switch power supply voltage input terminal 6BVD to the power supply terminal VCB. The second harmonic signal transmission path is formed between the 6BVD and the harmonic signal generated by the power amplifier 4B and leaking to the amplifier power supply voltage input terminal 4BVC to the switch power supply voltage input terminal 6BVD. The second harmonic signal transmission path is a path from the amplifier power supply voltage input terminal 4BVC to the switch power supply voltage input terminal 6BVD via the phase adjustment line 86B, the branch point ND2, and the phase adjustment line 87B. In order to prevent the harmonic signal flowing from the amplifier power supply voltage input terminal 4BVC to the second harmonic signal transmission path from being reflected at the starting point of the second harmonic signal transmission path, the second harmonic signal transmission path Is preferably equal to or close to the characteristic impedance of the main transmission line in the high-frequency module 152. For example, when the characteristic impedance of the main transmission line in the high-frequency module 152 is 50Ω, the characteristic impedance of the second harmonic signal transmission path is preferably 50Ω or a value close to 50Ω.

  The diplexer 54 includes first to third ports, an LPF 54A, and an HPF 54B. The first port is connected to the terminal 6Ac of the switch 6A. The LPF 54A is provided between the first port and the third port. The second port is connected to the terminal 6Bc of the switch 6B. The HPF 54B is provided between the second port and the third port. The third port is connected to the antenna terminal ANT.

  The phase adjustment lines 86A, 86B, 87A, and 87B can be configured using a conductor layer provided in the multilayer substrate 20, similarly to the phase adjustment line 81 in the first embodiment. Further, the phase adjustment lines 86A, 86B, 87A, 87B can be formed in a meander shape like the phase adjustment line 81, for example.

  Next, the operation and effect of the high-frequency module 152 according to the present embodiment will be described. When transmitting the first transmission signal, the port 14Ac of the switch circuit 14A is connected to the port 14Aa. In this case, the first transmission signal in the form of a balanced signal output from the RFIC passes through the pair of first transmission signal terminals Tx11 and Tx12 and is input to the BPF 3A. The first transmission signal in the form of an unbalanced signal is output by the BPF 3A. Is converted into a transmission signal. The first transmission signal in the form of this unbalanced signal is supplied to the antenna 1 through the power amplifier 4A, the switch 6A, the LPF 54A of the diplexer 54 and the antenna terminal ANT in this order, and is transmitted from the antenna 1.

  When receiving the first received signal, the port 14Ac of the switch circuit 14A is connected to the port 14Ab. In this case, the first reception signal received by the antenna 1 passes through the antenna terminal ANT, the LPF 54A of the diplexer 54, the switch 6A, and the first reception signal terminal Rx1 in order, and is input to the RFIC.

  When transmitting the second transmission signal, the port 14Bc of the switch circuit 14B is connected to the port 14Ba. In this case, the second transmission signal in the form of a balanced signal output from the RFIC passes through the pair of second transmission signal terminals Tx21 and Tx22 and is input to the BPF 3B, and the second transmission signal in the form of an unbalanced signal is output by the BPF 3B. Is converted into a transmission signal. The second transmission signal in the form of this unbalanced signal is supplied to the antenna 1 through the power amplifier 4B, the switch 6B, the HPF 54B of the diplexer 54 and the antenna terminal ANT in this order, and is transmitted from the antenna 1.

  When receiving the second reception signal, the port 14Bc of the switch circuit 14B is connected to the port 14Bb. In this case, the second received signal received by the antenna 1 passes through the antenna terminal ANT, the HPF 54B of the diplexer 54, the switch 6B, and the second received signal terminal Rx2 in order, and is input to the RFIC.

  When transmitting the first transmission signal, the power amplifier 4A and the switch circuit 14A each generate a harmonic signal for the first transmission signal. The harmonic signal generated by the power amplifier 4A leaks from the signal output terminal 4Ab of the power amplifier 4A to the amplifier power supply voltage input terminal 4AVC. The harmonic signal leaking to the amplifier power supply voltage input terminal 4AVC is transmitted to the switch power supply voltage input terminal 6AVD of the switch 6A through the first harmonic signal transmission path. The harmonic signal transmitted to the switch power supply voltage input terminal 6AVD passes through the semiconductor element constituting the decoder 13A and the semiconductor element constituting the switch circuit 14A, and leaks to each port 14Aa, 14Ab, 14Ac of the switch circuit 14A. . Here, when the harmonic signal transmitted to the switch power supply voltage input terminal 6AVD via the first harmonic signal transmission path leaks to the port 14Ac, the harmonic signal appearing at the port 14Ac is attributed to the first power amplifier. Called harmonic signal.

  The harmonic signal generated by the switch circuit 14A when the first transmission signal is transmitted appears at the ports 14Aa, 14Ab, and 14Ac of the switch circuit 14A. Here, the harmonic signal generated by the switch circuit 14A and appearing at the port 14Ac is referred to as a first switch-derived harmonic signal. The port 14Ac outputs a first synthesized harmonic signal formed by synthesizing the harmonic signal caused by the first power amplifier and the harmonic signal caused by the first switch.

  In the present embodiment, the first synthesized harmonic signal is adjusted by adjusting the phase and intensity of the harmonic signal derived from the first power amplifier in accordance with the principle of harmonic signal reduction described in the first embodiment. Can be made smaller than the intensity of the harmonic signal caused by the first switch. In the present embodiment, the length of the first harmonic signal transmission path can be adjusted by adjusting the lengths of the phase adjustment lines 86A and 87A, and thereby the phase of the harmonic signal caused by the first power amplifier. Can be adjusted. In the present embodiment, by adjusting the lengths of the phase adjustment lines 86A and 87A, the phase of the harmonic signal caused by the first power amplifier is made 180 ° different from the phase of the harmonic signal caused by the first switch. It is preferable.

  When transmitting the second transmission signal, the power amplifier 4B and the switch circuit 14B each generate a harmonic signal for the second transmission signal. The harmonic signal generated by the power amplifier 4B leaks from the signal output terminal 4Bb of the power amplifier 4B to the amplifier power supply voltage input terminal 4BVC. The harmonic signal leaking to the amplifier power supply voltage input terminal 4BVC is transmitted to the switch power supply voltage input terminal 6BVD of the switch 6B through the second harmonic signal transmission path. The harmonic signal transmitted to the switch power supply voltage input terminal 6BVD passes through the semiconductor element constituting the decoder 13B and the semiconductor element constituting the switch circuit 14B, and leaks to each port 14Ba, 14Bb, 14Bc of the switch circuit 14B. . Here, when the harmonic signal transmitted to the switch power supply voltage input terminal 6BVD via the second harmonic signal transmission path leaks to the port 14Bc, the harmonic signal appearing at the port 14Bc is attributed to the second power amplifier. Called harmonic signal.

  The harmonic signal generated by the switch circuit 14B when the second transmission signal is transmitted appears at the ports 14Ba, 14Bb, 14Bc of the switch circuit 14B. Here, the harmonic signal generated by the switch circuit 14B and appearing at the port 14Bc is referred to as a second switch-derived harmonic signal. The port 14Bc outputs a second synthesized harmonic signal formed by synthesizing the harmonic signal caused by the second power amplifier and the harmonic signal caused by the second switch.

  In the present embodiment, the second synthesized harmonic signal is obtained by adjusting the phase and intensity of the harmonic signal derived from the second power amplifier in accordance with the principle of harmonic signal reduction described in the first embodiment. Can be made smaller than the intensity of the harmonic signal caused by the second switch. In the present embodiment, the length of the second harmonic signal transmission path can be adjusted by adjusting the lengths of the phase adjustment lines 86B and 87B, and thereby the phase of the harmonic signal caused by the second power amplifier. Can be adjusted. In the present embodiment, by adjusting the lengths of the phase adjustment lines 86B and 87B, the phase of the harmonic signal caused by the second power amplifier is made 180 ° different from the phase of the harmonic signal caused by the second switch. It is preferable.

  In the present embodiment, a diplexer 54 is provided between the switches 6A and 6B and the antenna terminal ANT. Therefore, according to the present embodiment, the diplexer 54 can further attenuate the harmonic signal from the switches 6A and 6B toward the antenna 1. By using the harmonic signal reduction method in the present embodiment using the first and second harmonic signal transmission paths in combination with the harmonic signal reduction method by the diplexer 54, the harmonic signal is generated only by the diplexer 54. Compared with the case where it reduces, the performance requested | required of the diplexer 54 regarding reduction of a harmonic signal can be eased.

  In the above description, the diplexer 54 has been described as being configured by the LPF 54A and the HPF 54B. However, the diplexer 54 may have the following configuration. When transmitting the second transmission signal, the HPF 54B cannot attenuate the harmonic signal generated by the power amplifier 4B. Therefore, when the harmonic signal generated by the power amplifier 4B is to be attenuated by the diplexer 54, the BPF is used instead of the HPF 54B. Accordingly, in this case, the diplexer 54 is configured by the LPF 54A and the BPF. Further, when the diplexer 54 wants to attenuate an unnecessary signal having a frequency lower than the frequency band of the transmission signal, a BPF is used instead of the LPF 54A. Therefore, in this case, the diplexer 54 is constituted by two BPFs.

  Further, in the high-frequency module 152 according to the present embodiment, when a triplexer is provided instead of the diplexer 54 and one switch similar to the switches 6A and 6B is added, it is possible to cope with three frequency bands. become. Other configurations, operations, and effects in the present embodiment are the same as those in the sixth embodiment.

  In addition, this invention is not limited to said each embodiment, A various change is possible. For example, the high-frequency module of the present invention may include elements other than the components of the high-frequency module shown in each embodiment, such as an amplifier that amplifies a received signal.

  Further, the present invention can be applied to all high frequency modules including a power amplifier that amplifies a high frequency signal and a switch to which an output signal of the power amplifier is input.

  DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... High frequency module, 3 ... BPF, 4 ... Power amplifier, 5 ... LPF, 6 ... Switch, 13 ... Decoder, 14 ... Switch circuit, 80 ... Harmonic signal transmission path, 81 ... Phase adjustment line, Vcc: power supply terminal, 4VC: amplifier power supply voltage input terminal, 6VD: switch power supply voltage input terminal.

Claims (12)

A high-frequency module including a power supply terminal to which a power supply voltage is input, a power amplifier, and a switch,
The power amplifier has a signal input terminal, a signal output terminal, and an amplifier power supply voltage input terminal connected to the power supply terminal, and the power supply voltage is supplied via the power supply terminal and the amplifier power supply voltage input terminal. And amplifies a high-frequency signal input to the signal input terminal and outputs from the signal output terminal,
The switch receives three or more ports including a port to which a high frequency signal output from the signal output terminal of the power amplifier is input, a switch power supply voltage input terminal connected to the power supply terminal, and a control signal. A control signal input terminal, and operates by being supplied with the power supply voltage via the power supply terminal and the switch power supply voltage input terminal, and according to the control signal input to the control signal input terminal, Switch between two connected ports,
The high-frequency module further includes a transmission formed between the amplifier power supply voltage input terminal and the switch power supply voltage input terminal by connecting both the amplifier power supply voltage input terminal and the switch power supply voltage input terminal to the power supply terminal. A high frequency module comprising a path.   The high-frequency module according to claim 1, wherein the transmission path transmits a harmonic signal generated by the power amplifier and leaking to the amplifier power supply voltage input terminal to the switch power supply voltage input terminal.   The switch further includes a logic circuit that operates when the power supply voltage is supplied and generates a plurality of signals for determining two connected ports based on the control signal. The high frequency module according to claim 1 or 2.   The three or more ports of the switch include a first port and two or more second ports selectively connected to the first port, and are output from a signal output terminal of the power amplifier. 4. The high-frequency module according to claim 1, wherein a port to which a high-frequency signal is input is one of the two or more second ports. 5.   The harmonic signal generated by the power amplifier and leaked to the amplifier power supply voltage input terminal and transmitted to the switch power supply voltage input terminal via the transmission path leaks to the first port. 5. The high-frequency module according to claim 4, wherein the phase of the harmonic signal appearing at the port is 180 ° different from the phase of the harmonic signal generated by the switch and appearing at the first port.   Further, between the power amplifier and the switch, a harmonic signal is provided in a path of a high frequency signal output from the signal output terminal of the power amplifier, and is superimposed on the high frequency signal output from the signal output terminal of the power amplifier. The high-frequency module according to claim 1, further comprising a filter that attenuates noise. Furthermore, a laminated substrate including a plurality of laminated dielectric layers is provided,
The power amplifier and the switch are mounted on the multilayer substrate,
The high-frequency module according to claim 1, wherein the transmission path is disposed inside the multilayer substrate. Furthermore, a circuit disposed inside the laminated substrate is provided,
The multilayer substrate is disposed between a first conductor layer constituting a part of the transmission path, a circuit disposed inside the multilayer substrate, and the first conductor layer, and is connected to the ground. The high frequency module according to claim 7, further comprising a second conductor layer. The power amplifier further includes a second power amplifier, the second power amplifier including a second signal input terminal, a second signal output terminal, and a second amplifier power supply voltage input terminal connected to the power supply terminal. And operates by being supplied with the power supply voltage via the power supply terminal and the second power supply voltage input terminal, and amplifies the second high-frequency signal input to the second signal input terminal. Output from the second signal output terminal;
The three or more ports of the switch include a port to which a high-frequency signal output from a second signal output terminal of the second power amplifier is input,
In the high-frequency module, the second amplifier power supply voltage input terminal and the switch power supply voltage input terminal are connected to each other by connecting the second amplifier power supply voltage input terminal and the switch power supply voltage input terminal to the power supply terminal. The high-frequency module according to claim 1, further comprising a second transmission path formed therebetween.   10. The second transmission path transmits a harmonic signal generated by the second power amplifier and leaking to the second amplifier power supply voltage input terminal to the switch power supply voltage input terminal. The high-frequency module described. The three or more ports of the switch include a first port and two or more second ports selectively connected to the first port, and are output from a signal output terminal of the power amplifier. A port to which a high-frequency signal is input and a port to which a high-frequency signal output from the second signal output terminal of the second power amplifier is input are included in the two or more second ports,
The harmonic signal generated by the power amplifier and leaked to the amplifier power supply voltage input terminal and transmitted to the switch power supply voltage input terminal via the transmission path leaks to the first port. The phase of the harmonic signal that appears at the port is the phase of the harmonic signal that is generated by the switch and appears at the first port when a high-frequency signal output from the signal output terminal of the power amplifier is input to the switch. And 180 °
A harmonic signal generated by the second power amplifier and leaking to the second amplifier power supply voltage input terminal and transmitted to the switch power supply voltage input terminal via the second transmission path is the first power supply. The phase of the harmonic signal that appears at the first port by leaking to the port is determined by the switch when a high-frequency signal output from the second signal output terminal of the second power amplifier is input to the switch. 11. The high-frequency module according to claim 10, wherein a phase of a harmonic signal generated and appearing at the first port is 180 degrees different from that of the harmonic signal.   Further, between the power amplifier and the switch, a harmonic signal is provided in a path of a high frequency signal output from the signal output terminal of the power amplifier, and is superimposed on the high frequency signal output from the signal output terminal of the power amplifier. Between the first filter for attenuating the signal, the second power amplifier and the switch, and provided in a path of a high-frequency signal output from a second signal output terminal of the second power amplifier. The high frequency device according to claim 9, further comprising: a second filter that attenuates a harmonic signal superimposed on the high frequency signal output from the second signal output terminal of the power amplifier. module.

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