JP2010272811A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure a sufficient underfill sealing strength by canceling a creep-up lack of an underfill to a side face of each corner of semiconductor electronic parts in a semiconductor device formed by carrying out sealing of an underfill to the semiconductor electronic parts in the shape of almost rectangular plane. <P>SOLUTION: This invention relates to a semiconductor device 1a formed by carrying out sealing of the underfill 5 to semiconductor electronic parts 10 in the shape of almost rectangular plane on a substrate 2 with a solder resist film layer 3. In the solder resist film layer 3, there is formed a groove 30 around a packaging region of the semiconductor electronic parts, while making a contour in the shape of almost rectangular plane mostly along a contour shape of the semiconductor electronic parts. While an electrode pat 40 is formed inside almost rectangular corner in the shape of the groove over the substrate 2, a solder resist on the electrode pat is opened, and a solder projection 50 is formed on the electrode pat. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor electronic component having a substantially rectangular planar shape mounted on a substrate having a solder resist film layer is underfill sealed. Specifically, the present invention relates to an improvement in an underfill sealing technique for improving the reliability of a semiconductor device.

  In a semiconductor device in which a semiconductor electronic component such as a LGA (Land Grid Array), a BGA (Ball Grid Array), or a CSP (Chip Size Package) or a semiconductor electronic component having a bare chip mounted on an interposer is mounted on a substrate, A semiconductor electronic component is mounted by using a fine bump as a terminal and connecting the terminal to a conductor portion (terminal pad) in a printed wiring on a substrate by soldering or the like. In this semiconductor device, when the substrate is heated in a reflow process or the like, or placed in an environment with a temperature cycle with a difference in height, the difference in thermal expansion between the substrate and the resin constituting the package of the semiconductor electronic component causes Stress is generated at the connection between the terminal and the terminal pad. This stress causes the fine connection part to be disconnected. And the technique for preventing such a disconnection is the underfill sealing technique which is the object of the present invention. As is well known, underfill sealing technology fills a gap between a semiconductor electronic component and a substrate with underfill (for example, a thermosetting liquid resin) using a capillary phenomenon, and then hardens it by hardening. This ensures connection reliability.

  10 (A) and 10 (B) are schematic views showing a conventional underfill sealing technique. (A) is a sectional side view of the semiconductor electronic component 10, and (B) is a sectional side view of the semiconductor device 1 c in which the semiconductor electronic component 10 shown in (A) is mounted on the substrate 2. The semiconductor electronic component 10 has a structure in which a passivation layer (12, 13) made of glass, an insulating resin layer (rewiring layer) 14 made of epoxy resin, and the like are laminated below a silicon layer 11 constituting a semiconductor circuit. . Printed wiring is formed on the surface of the substrate 2, and a solder resist 3 is formed on the surface of the substrate 2 to protect the wiring. Further, by opening a part of the solder resist 3 by a known photolithography technique, the terminal pads 4 corresponding to various electronic components mounted on the substrate 2 are exposed on the surface of the substrate 2. After the semiconductor electronic component 10 is mounted, the underfill 5 is filled in the gap d between the semiconductor electronic component 10 and the substrate 2 and cured.

  However, in the conventional underfill sealing technology, as shown in FIG. 5B, the underfill 5 does not sufficiently crawl on the side surface of the semiconductor electronic component 10, and the side surface of the component cannot be sufficiently fixed by the underfill 5. There was a case. If the underfill 5 is insufficient to creep up to the side surface of the semiconductor electronic component 10, only the lower layer of the semiconductor electronic component 10 having a laminated structure is fixed by the underfill 5. Naturally, a stress due to a difference in thermal expansion is also generated in each layer inside the semiconductor electronic component 10. For this reason, if only the lower layer is fixed with the underfill 5, the stress applied to the interface with the upper layer cannot be relieved. For example, the passivation layer 12 is cracked or the passivation layer 12 and the rewiring layer 14. Peeling occurs at the interface (12-14). In a semiconductor electronic component in which a bare chip is mounted on an interposer, the bare chip is peeled off at the interface with the interposer.

  The present inventor considered the cause of insufficient underfill scooping, and formed a groove around the mounting area of the semiconductor electronic component, so that the supplied underfill was dammed up by the groove, and was formed on the side surface of the semiconductor electronic component. A semiconductor device configured to crawl up underfill has been invented first (Japanese Patent Application No. 2008-115700). In the present invention, when the hydrophilicity is improved by modifying the surface of the semiconductor electronic component together with the substrate so that the underfill easily rises, the underfill flows out over a wide area, and the electrons that are not sealed In order to prevent the part from being contaminated, the shape of the corner of the substantially rectangular outline inside the double outline bordering the groove is optimized.

  However, in the previous invention, in the case where a conductor electronic component having a rectangular planar shape is mounted, there has been a case where creeping up is insufficient at the corners of the rectangle. Specifically, although it was an acceptable product, fine cracks occurred with very little probability. However, since long-term reliability is unknown, a repair process such as manually re-applying underfill on the side surface of the corner of the semiconductor electronic component has been added during the manufacturing process of the semiconductor device. As a matter of course, this repair process increases the manufacturing cost.

  Accordingly, the present invention eliminates the shortage of underfill creeping particularly on the side surfaces of the corners of the rectangular shape of the semiconductor electronic component in a semiconductor device in which a semiconductor electronic component having a substantially rectangular planar shape is underfilled. And it aims at ensuring sufficient underfill sealing strength.

The present invention for achieving the above object is a semiconductor device in which a semiconductor electronic component having a substantially rectangular planar shape mounted on a substrate having a solder resist film layer is underfill sealed,
In the solder resist film layer, a groove having a substantially rectangular planar shape substantially along the outer shape of the semiconductor electronic component is defined around the mounting area of the semiconductor electronic component,
On the substrate, an electrode pad is formed inside the substantially rectangular corner forming the outer shape of the groove, and a solder resist on the electrode pad is opened,
In the semiconductor device, a solder protrusion is formed on the electrode pad.

  The electrode device may be a saddle type that bends along the shape of the corner of the groove. Also, an R portion that swells in an arc shape is formed inside the bent portion of the electrode pad, and the R portion may be a semiconductor device that faces a lower surface of a corner of the semiconductor electronic component having the substantially rectangular planar shape.

  In the semiconductor device including the electrode pad in which the R portion is formed, the solder protrusion formed in the electrode pad shape has a height greater than or equal to the gap between the lower surface of the semiconductor electronic component and the substrate. In the semiconductor device, it is more preferable that the substantially rectangular planar groove is formed so as to be continuous with the opening of the solder resist for exposing the electrode pad.

  According to the semiconductor device of the present invention, since the underfill is sufficiently fixed to the side surface of the corner of the semiconductor electronic component having a rectangular planar shape, it has high sealing strength, and can be used during heating. A highly reliable structure in which a semiconductor electronic component is not easily destroyed under a temperature cycle environment can be obtained.

1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention. (A) is a top view, (B) is the principal part enlarged view in (A). It is principal part sectional drawing of the semiconductor device in the said 1st Example. FIG. 6 is a structural diagram of a groove formed in the semiconductor device of the first embodiment. It is a figure which shows the example of a change of the semiconductor device of the said 1st Example. It is a principal part enlarged view of the semiconductor device in the 2nd Example of this invention. It is principal part sectional drawing of the semiconductor device in the said 2nd Example. It is a figure for demonstrating the arrangement | positioning relationship of each site | part which comprises the principal part in the semiconductor device of the said 2nd Example. (A) is a plan view and (B) is a cross-sectional view. It is a figure which shows the relationship between the height of a solder bank and the height of an underfill in the semiconductor device of the said 2nd Example. In the semiconductor device of the said 2nd Example, it is a figure which shows the relationship between the height of a solder bank and the sealing state of an underfill. (A) is a figure which shows the sealing state when a solder bank is high, (B) is a figure which shows the sealing state when a solder bank is low. It is explanatory drawing about an underfill sealing technique. (A) is a cross-sectional structure diagram of a general semiconductor electronic component, and (B) is a diagram showing a state in which the semiconductor electronic component is sealed with an underfill.

=== First Embodiment ===
FIG. 1 shows a schematic structure of a semiconductor device 1a according to the first embodiment of the present invention. (A) is the top view, (B) is an enlarged view of the principal part 100 in (A). FIG. 2 shows a cross section taken along the line aa in FIG. The semiconductor device 1a of the present embodiment has a basic structure in which a semiconductor electronic component 10 to be sealed by an underfill 5 is mounted on a substrate 2 formed by printing printed wiring on the surface of a glass epoxy substrate. . In this embodiment, the semiconductor electronic component 10 is mounted almost at the center of the substrate 2, and peripheral components 20 such as other ICs and chip components are mounted around the semiconductor electronic component 10. A solder resist film 3 for protecting the printed wiring is formed on the surface layer of the substrate 2.

  The solder resist film 3 is formed by patterning using a lithography technique, and the film 3 is opened at a portion of the terminal pad 4 that makes terminal connection with the mounting component (10, 20). That is, the portion of the terminal pad 4 is exposed on the surface layer of the substrate 2. The semiconductor electronic component 10 includes a large number of terminals (not shown) on a substantially rectangular planar lower surface, and a gap d between the substrate 2 and the lower surface of the semiconductor component 10 is filled with an underfill 5. It is cured. In the semiconductor device 1 of this embodiment, the solder resist 3 is opened so as to form a groove 30 around the mounting region of the semiconductor electronic component 10 in addition to the terminal pad 4.

  In addition, electrode pads 40a that are not connected to any wiring path are formed at the corners of the groove 30, that is, at the four corners of the semiconductor electronic component 10 having a substantially rectangular planar shape. The resist 3 is also opened in accordance with the shape of the electrode pad 40a. In this example, the electrode pad 40a has a saddle shape that bends along the corner shape of the corner, and a solder protrusion 50 is formed on the pad 40a by reflow soldering.

=== Structure of groove ===
As described above, in the semiconductor device 1a of this embodiment, the groove 30 is formed by opening the solder resist film 3 around the mounting region of the semiconductor electronic component 10 to be sealed with the underfill 5. FIG. 3 specifically shows the shape of the groove 30 in the first embodiment. The groove 30 has a substantially rectangular planar shape that substantially conforms to the outer shape of the substantially rectangular planar semiconductor electronic component 10 having left and right and upper and lower widths Lw and Lh, respectively. A double contour line (31, 32) having the width w of the groove is formed.

  Moreover, the external shape of the groove | channel 30 is not a complete rectangle, but is a shape provided with the convex part 33 which becomes convex in the outer side of one side of a rectangle. The underfill 5 is filled into the lower surface of the semiconductor electronic component 10 from the convex portion 33 side. The inner contour line 31 is separated from each side 15 of the substantially rectangular semiconductor electronic component 10 except for the convex portion 33 by a distance td, and the inner contour line 34 in the convex portion 33 is adjacent to the semiconductor electronic component 10. It is separated from the side 16 by a distance T (> td). The length Ls of the inner contour line 34 in the convex portion 33 is shorter than the length Lw of the sides (15, 16) of the semiconductor electronic component 10, and both ends 35 of the inner contour line 31 in the convex portion 33 are made of semiconductor. In the electronic component 10, it is located inside the both ends 17 of the side 16 parallel to this.

  In this embodiment, the underfill 5 is filled from the convex portion 33 side toward the gap d between the semiconductor electronic component 10 and the substrate 2. That is, in order to mount components on the substrate 2 including the peripheral component 20 at a high density, it is necessary to narrow the sealing region by the underfill 5 and widen the interval td between the groove 30 and the semiconductor electronic component 10. I can't take it. Moreover, in order to prevent the underfill 5 from adhering to the outside of the groove 30 on the surface of the substrate 2, the underfill 5 is filled between the contour line 31 inside the groove 30 and the semiconductor electronic component 10. Need to start from position. Therefore, a convex portion 33 is provided on one side of the groove 30 so that the interval td between the semiconductor electronic component 10 and the groove 30 is partially expanded to T, and the underfill 5 is filled from this portion 33, thereby minimizing the necessary area. The underfill 5 is reliably filled.

=== About surface modification treatment and groove function ===
The conventional semiconductor electronic component 10 improves the hydrophilicity of the package surface so that the underfill 5 can easily climb to the side surface of the semiconductor electronic component 10. In the semiconductor device 1a in the second embodiment, which will be described later, as well as the semiconductor device 1a in the first embodiment, the substrate 2 and the semiconductor electronic component 10 have been subjected to surface modification treatment. The hydrophilicity of the package surface of the electronic component 10 is improved. As a result, the underfill 5 is uniformly filled in the gap d between the semiconductor electronic component 10 and the substrate 2, and is sufficiently raised to the upper layer on the side surface of the semiconductor electronic component 10. In the present embodiment, surface modification processing by plasma cleaning is performed in a state where the semiconductor electronic component 10 is mounted.

  In the first embodiment, the groove 30 functions as a “dam” for preventing the underfill 5 from flowing and diffusing outside the mounting region of the semiconductor electronic component 10 due to the surface modification process. When the underfill 5 filled in the gap d between the substrate 2 and the semiconductor electronic component 10 tries to flow and diffuse toward the outside of the mounting area of the semiconductor electronic component 10, the edge at the contour line 31 inside the groove 30. The diffusion is blocked by the effect, and the underfill 5 is pushed up in the direction of the semiconductor electronic component 10 so that the underfill 5 rises more reliably on the side surface of the semiconductor electronic component 10. However, there have been a few cases where the side surface of the four corners 18 of the semiconductor electronic component 10 is insufficiently crawled.

=== Dyke structure with solder projections ===
The semiconductor device 1a according to the first embodiment has a configuration for eliminating the shortage of the underfill 5 at the corner 18 of the semiconductor electronic component 10 having a substantially rectangular planar shape. As shown in FIG. 1B, independent electrode pads 40a that are not connected to any wiring path are formed on the substrate 2 at positions corresponding to the four corners of the mounting area of the semiconductor electronic component 10. Yes. At the position where the electrode pad 40a is formed, the solder resist 3 is opened and the electrode pad 40a is exposed. Further, solder protrusions 50 are formed on the electrode pads 40a by reflow soldering.

  Since the underfill 5 is blocked by the solder protrusions 50 before flowing into the grooves 30, the underfill 5 flows toward the side surfaces of the four corners 18 of the semiconductor electronic component 10. As a result, at the four corners 18 of the semiconductor electronic component 10, Climb up enough to the top. That is, the solder protrusion 50 functions as a dike for the underfill 5, and the electrode pad 40a functions as a base for the dike.

  Since this electrode pad (hereinafter referred to as a dike electrode) 40 a is required to function as a base of a dike (hereinafter referred to as a solder dike) 50 by a solder protrusion, the position of the electrode pad (hereinafter referred to as a dike electrode) is determined from the inner contour line 31 of the groove 30. It is formed on the mounting area side of the semiconductor electronic component 10. In the first embodiment, as shown in FIG. 1B, the opening 41 of the solder resist 3 on the bank electrode 40a and the opening of the solder resist 3 forming the groove 30 are integrated. That is, the contour line 31 inside the groove coincides with the contour of the opening 41 for exposing the bank electrode 40a. Of course, as shown in FIG. 4, an opening 41 for exposing the bank electrode 40 a may be provided separately from the groove 30. However, if the opening for the groove 30 and the opening 41 for the dike electrode 40a are individually provided, the interval td between the periphery of the semiconductor electronic component 10 and the inner contour line 31 of the groove 30 needs to be separated to some extent. Therefore, the mounting area of other electronic components 20 is narrowed, and the mounting density of the semiconductor device 1a is reduced. Therefore, as in the first embodiment, it is desirable that the opening of the dike electrode 40a and the opening of the groove 30 in the solder resist 3 are integrated.

The dike electrode 40a may have any shape as long as it can prevent the flow of the underfill 5 by the solder dike 50 formed on the dike electrode 40a. The function of reliably damming is required, and the planar shape of the solder dyke 50 is substantially in line with the planar shape of the dyke electrode 40a. Therefore, like the dike electrode 40a in the first embodiment, the corner 18 of the semiconductor electronic component 10 is formed. It is preferable to use a saddle shape that conforms to the shape. By using the saddle-shaped dike electrode 40a, the solder bank 50 formed thereon also has a planar shape that bends in a saddle shape, and the underfill 5 that flows radially toward the outside of the mounting region of the semiconductor electronic component 10 is provided. The dam is surely stopped, and the underfill 5 is pushed back toward the corner 18 of the semiconductor electronic component 10. As a result, the underfill 5 can be reliably crawled up on the side surface of the corner 18 of the semiconductor electronic component 10.

=== Second Embodiment ===
As is well known, WL (Wafer Level) -CSP is a CSP formed by a method of forming a terminal, wiring, etc. before cutting out a silicon wafer on which a semiconductor element is formed, and then cutting out the wafer. This WL-CSP has a two-layer structure in which the package size and the IC chip size are substantially the same, and the resin interposer and the IC chip made of silicon having a heat contraction rate greatly different from that of the resin are almost in contact with each other. Become. Therefore, compared with other semiconductor electronic components, peeling at the interface between the interposer and the lower surface of the chip is likely to occur.

  The second embodiment is a semiconductor device in which a semiconductor electronic component, such as WL-CSP, which has a structure that easily peels between layers, is sealed with an underfill. FIG. 5 shows the shape and arrangement of the dike electrode 40b in the second embodiment. In this example, the dike electrode 40 b is formed with an R portion in which the inside of the saddle-shaped bent portion is expanded in an arc shape, and a part of the R portion 42 is located in the mounting region of the semiconductor electronic component 10. Are arranged as follows. That is, at the four corners 18 of the semiconductor electronic component 10, the lower surfaces thereof face the bank electrodes 40b.

  FIG. 6 shows a cross section taken along line bb in FIG. FIG. 6 shows a state in which the solder bank 50 is formed on the bank electrode 40b and the underfill 5 is filled. Since the bank electrode 40b is formed so as to be embedded in the lower surface of the semiconductor electronic component 10, the solder bank 50 on the bank electrode 40b is close to the corner 18 of the semiconductor electronic component 10, and the underfill 5 is inserted into the semiconductor electronic component 10. Concentrate around the corner 18. As a result, the underfill 5 rises high.

=== About the height of the solder bank ===
The second embodiment is configured to crawl up the underfill 5 at the four corners 18 of the semiconductor electronic component 10. By the way, as shown in FIG. 6, the vicinity 5 p of the underfill 5 creeping up is a portion where there is substantially no additive (filler) having a sealing action, and this portion is transparent by visual observation. It can be discriminated by being resinous. Therefore, even if the appearance of the underfill 5 looks high and crawls up, the substantial underfill 5e to which the actual sealing effect is applied does not reach the crest 5p. Accordingly, the conditions for more reliably applying underfill 5 sealing to a semiconductor electronic component having a structure such as WL-CSP were examined. It was found to be related to a height of 50.

  FIG. 7 is a schematic diagram for explaining the relationship between the height of the solder dyke 50 and the height of the substantial underfill 5e, and each of the semiconductor electronic component 10, the dyke electrode 40b, and the solder dyke 50 or their mutual arrangement. The relationship and dimensions are shown. (A) is a top view, (B) is a cc arrow cross section in (A) in the state which formed the solder bank 50 and was filled with the underfill 5. FIG. The semiconductor electronic component 10 shown here is a WL-CSP, and at the four corners of the package, substantial underfill portions (hereinafter referred to as effective underfill: shaded portions in the figure) 5e including a filler are provided on the top surface. It is necessary to crawl up above the interface (hereinafter referred to as SI boundary) between the interposer 14i on which the rewiring layer is formed and the silicon layer 11.

  The dimensions of each part in the semiconductor device 1b are as follows: the width Wd of the groove 30 = 0.1 mm, the line width Wp = 0.15 mm of the saddle-shaped portion of the dike electrode 40b, and the length Lp = 0. The radius Rp of the R portion 42 in the dike electrode 40b is 5 mm and is 0.15 mm. Furthermore, the contour line of the solder resist opening 41 for exposing the levee electrode 40b is integrated with the inner contour line 31 of the groove 30, the width of the step-like straight line portion is to = 0.17 mm, and the levee electrode 40b. The radius Ro of the portion corresponding to the R portion 42 is 0.15 mm.

  First, in the reflow soldering process, the amount of solder supplied onto the terminal pads connected to the terminals such as bumps of the semiconductor electronic component 10 and the electrode pads such as the bank electrode 40b is changed, and the height corresponding to the amount of solder is changed. Solder protrusions were formed. The amount of solder supplied was adjusted according to the opening area of the solder mask. As is well known, in reflow soldering, solder is supplied onto each electrode pad by printing paste solder using a solder mask having openings corresponding to the electrode pads. Therefore, the height of the solder protrusion can be adjusted by adjusting the opening area of the solder mask.

Note that the amount of solder supplied to the terminal pads corresponding to the bumps and the like is such that the larger the corresponding solder mask area, the more solder is applied onto the pads, and thus the height of the gap d on the lower surface of the semiconductor electronic component 10. (Mounting gap) Hc tends to increase. That is, it was also evaluated whether the mounting gap Hc affects the underfill sealing effect by changing the pad opening. Here, the diameter of the solder mask opening (terminal pad opening diameter) was set to either 0.19 mm or 0.20 mm, whereas the opening diameter of the solder resist corresponding to the terminal pad was 0.13 mm.

  The solder mask opening size (bank electrode opening size) relative to the bank electrode 40b was either +25 μm or +50 μm with respect to the outer shape of the bank electrode 40b. Then, the relationship between the height Hs of the solder bank 50 and the rising height of the effective underfill 5e when the terminal pad opening diameter and the bank electrode opening size are the conditions was evaluated. In the evaluation, the semiconductor device 1b manufactured under various conditions was used as a sample, and three samples manufactured under the same conditions were manufactured. The mounting gap Hc is a distance from the film surface of the solder resist 3 to the lower surface of the semiconductor electronic component 10, and the film thickness of the solder resist 3 and the thickness of the electrode pad such as the bank electrode 40 are substantially the same.

Table 1 shows the evaluation results.

  In Table 1, the semiconductor device 1b manufactured as a sample is divided into a to d categories for each same manufacturing condition, and three samples belonging to each category are a1 to a3, b1 to b3, c1 to c3, d1. ˜d3, the height Hs of the solder bank and the height Hf of the effective underfill 5e in each sample are shown as relative values when the mounting gap of the semiconductor electronic component 10 is 1. From the evaluation results shown in Table 1 above, the correlation between the terminal pad opening diameter and the height Hf of the effective underfill 5e cannot be found, but the height Hs of the solder bank 50 and the height Hf of the effective underfill 5e are not found. It can be said that there is a correlation.

  FIG. 8 is a graph showing the relationship between the height Hs of the solder bank 50 and the height Hf of the effective underfill 5e in each sample. If the height Hf of the effective underfill 5e is 1.6 or more relative to the mounting gap Hc, it is determined that the effective underfill 5e has surely climbed up to the SI boundary. For example, it can be said that the relationship between the height Hs of the solder bank 50 and the mounting gap Hc is more preferably Hs ≧ Hc. It was also confirmed that it is effective to increase the opening area of the solder mask in order to surely increase the solder levee 50.

  FIG. 9 shows the fillet shape of the effective underfill 5e. (A) is a fillet shape of a sample having a high height Hf of the effective underfill 5e, and (B) is a fillet shape of a sample having a low Hf. In (A), the effective underfill 5e having a sealing effect crawls up above the SI boundary, and the underfill 5 has a fillet shape in which the ridge line 5c rises linearly and vertically. . At the SI boundary, the effective underfill 5e was sufficiently thick. Further, it was confirmed that the flange portion 5f of the ridge line 5c is closer to the semiconductor electronic component 10 than the apex 50p of the solder bank 50, and the flow of the underfill 5 is reliably blocked.

  On the other hand, in (B), the underfill 5 has a fillet shape that gently draws an arcuate ridgeline 5c that protrudes downward, and the thickness of the effective underfill 5e at the SI boundary portion is considerably insufficient. In some samples, the effective underfill 5e does not reach the SI boundary. Further, the ridge portion 5f of the ridge line 5c exceeds the apex 50p of the solder bank 50, and some of the samples flowed to the groove 30 side.

=== Underfill sealing test ===
Next, the sealing test by the underfill 5 was performed about the sample produced on the conditions of ad shown in the said Table 1, and the reliability of sealing was evaluated. The test contents are a test specified by JEDEC (Joint Electron Device Engineering Councils) (a test combining a weather resistance test and a reflow process), a reliability test by a temperature cycle (a temperature resistance cycle test), and did. The JEDEC regulation test was performed by leaving the sample at -30 hours and 60% for 192 hours and then repeating the reflow process at a peak temperature of 260 ° C. three times. The temperature resistance cycle test was performed at −40 ° C. to 80 ° C. The temperature difference up to 120 ° C. was increased over 30 minutes, and then the cycle of decreasing the temperature at the same rate was repeated 200 times.

  In the JEDEC regulation test, the solder bank 50 was deformed in two of the five samples of the condition c. In the sample in which the solder bank 50 was deformed, the solder bank 50 did not have a sufficient height, and the underfill 5 flowed around the outer periphery of the solder bank 50. From this, it is presumed that there was some abnormality such as the solder dike 50 spouting to the outside of the underfill 5. In other words, by making the solder bank 50 higher, the contact area between the underfill 5 and the solder bank 50 can be suppressed to a necessary minimum, the deformation of the solder bank 50 is prevented, and the underfill 5 is reliably dammed. Can be stopped.

  In addition, cracks and peeling did not occur even after the temperature resistance cycle test in all samples including the two samples of the condition c where the abnormality was present. In other words, in this test, even a semiconductor device mounted with WL-CSP, which requires the most stringent reliability, is contaminated by underfill that does not require peripheral components on the substrate while ensuring sealing strength by underfill. It was proved that it was extremely reliable. On the other hand, in applications where semiconductor electronic components having a structure that is easily peeled off, such as WL-CSP, are taken into account for long-term reliability, a higher solder bank is formed as in conditions b and d. Recognized that it is necessary to do.

DESCRIPTION OF SYMBOLS 1a-1c Semiconductor device 2 Board | substrate 3 Solder resist layer 4 Terminal pad 5 Underfill 5e Effective underfill part 10 Semiconductor electronic component 14 Redistribution layer 14i Interposer 30 Groove 31 Inner outline 32 Outer outline 40 Levee electrode 50 Solder dike

Claims (5)

A semiconductor device in which a semiconductor electronic component having a substantially rectangular planar shape mounted on a substrate having a solder resist film layer is underfill sealed,
In the solder resist film layer, a groove having a substantially rectangular planar shape substantially along the outer shape of the semiconductor electronic component is defined around the mounting area of the semiconductor electronic component,
On the substrate, an electrode pad is formed inside the substantially rectangular corner forming the outer shape of the groove, and a solder resist on the electrode pad is opened,
A semiconductor device, wherein a solder protrusion is formed on the electrode pad.   2. The semiconductor device according to claim 1, wherein the electrode pad is a saddle type that is bent along the shape of the corner of the groove.   3. An R portion that swells in an arc shape is formed inside the bent portion of the electrode pad, and the R portion faces a lower surface of a corner of the semiconductor electronic component having the substantially rectangular planar shape. Semiconductor device.   4. The semiconductor device according to claim 3, wherein the solder protrusion formed in the electrode pad shape has a height equal to or greater than a gap between the lower surface of the semiconductor electronic component and the substrate.   5. The semiconductor device according to claim 1, wherein the substantially rectangular planar groove is formed so as to be continuous with an opening of a solder resist for exposing the electrode pad.