JP2010272553A - Defect inspection device and defect inspection method for mask blank, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a defect inspection device and a defect inspection method for a mask blank that can accurately and easily inspect the presence and type of a defect of the mask blank. <P>SOLUTION: A predetermined region to be inspected of the mask blank MB is irradiated with EUV (Extremely Ultraviolet) light BM emitted by a light source 1, and reflected light scattered from the region to be inspected is captured to detect a dark visual field detection image. Then the dark visual field detection image is converted into a two-dimensional detection signal and input to a two-dimensional array sensor SE. A part of the EUV light BM emitted by the light source 1 is branched and the light intensity of the EUV light BM emitted by the light source 1 is measured to thereby calculate a threshold from the light intensity of the EUV light BM emitted by the light source 1. The detection signal is compared with the threshold to determine whether the mask blank MB has a defect. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a defect inspection apparatus and defect inspection method for a mask blank for EUVL (Extreme UltraViolet Lithography) using ultrashort wavelength light, and a semiconductor device manufacturing technique using them, and in particular, a defect corresponding to a fine pattern. The present invention relates to a technique effective when applied to defect inspection of a multilayer mask blank having high detection sensitivity.

  Semiconductor devices are mass-produced by irradiating exposure light onto a mask, which is an original plate on which a circuit pattern is drawn, and repeatedly performing a photolithographic process of transferring the circuit pattern onto a semiconductor substrate via a reduction optical system. ing.

  In recent years, the miniaturization of semiconductor devices has progressed, and methods for increasing the resolution by shortening the exposure wavelength of photolithography have been studied. Up to now, ArF lithography using an argon fluoride (ArF) excimer laser with a wavelength of 193 nm has been developed, but development of optical lithography using a much shorter exposure wavelength, for example, a wavelength of 13.5 nm, has advanced. Yes.

  In this wavelength range, a transmission mask cannot be used because of the light absorption of the substance. Therefore, a multilayer film reflective substrate using reflection (Bragg reflection) by a multilayer film of molybdenum (Mo) and silicon (Si) is an EUVL mask. Used as a blank. Multilayer reflection is a kind of reflection utilizing interference. In the EUVL mask, an absorber pattern is formed on a mask blank in which a multilayer film of Mo and Si or the like is deposited on a quartz glass substrate or a low thermal expansion glass substrate.

  In EUVL, since the exposure wavelength is extremely short at 13.5 nm, even if a slight height abnormality occurs on the EUVL mask, it reaches about one-fifth of the exposure wavelength and is caused by the height abnormality. As a result, a local difference in reflectivity occurs, and a defect occurs during transfer. Therefore, the EUVL mask has a large qualitative difference in defect transfer compared to the conventional transmission mask.

  In the mask blank defect inspection in the previous stage of forming the absorber pattern, the same wavelength as that used for the mask pattern exposure and the inspection method for irradiating the mask blank obliquely to the mask blank and detecting foreign matter from the irregularly reflected light There is an at-wavelength defect inspection method that detects defects using EUV light of a wavelength. As the latter method, for example, Japanese Patent Application Laid-Open No. 2003-114200 (Patent Document 1) discloses a method using a dark field image, and Japanese Patent Application Laid-Open No. 6-349715 (Patent Document 2) uses a bright field. X-ray microscopy is disclosed. In addition, US Patent Application Publication No. 2004/0057107 (Patent Document 3) discloses a dark-field bright-field combination in which a defect is detected using a dark field and defect identification is performed using a bright-field system using a Fresnel zone plate. The law is disclosed.

  In addition, in the inspection of a conventional transmission mask blank, an inspection method for irradiating laser light obliquely to the mask blank and detecting foreign matter from the irregularly reflected light, and an inspection method for detecting a bright field image (microscope image), There is. As a modification of the latter method, for example, Japanese Patent Application Laid-Open No. 2001-174415 (Patent Document 4) and Japanese Patent Application Laid-Open No. 2002-333313 (Patent Document 5) describe whether a detected defect is a convex defect or a concave defect due to asymmetry. A technique for discriminating is disclosed.

  Japanese Patent Application Laid-Open No. 11-354404 (Patent Document 6) discloses that a multi-layer defect can be obtained by forming a peelable pattern on a multi-layer mask, performing actual pattern transfer, and inspecting the transferred pattern. A method of inspecting is disclosed.

  Japanese Patent Laying-Open No. 2005-241290 (Patent Document 7) discloses a detection signal by monitoring the irradiation intensity as a countermeasure when the intensity of the inspection light varies, in the case of pattern defect inspection of an optical mask. Means for providing correction to the above are disclosed.

  Japanese Patent Application Laid-Open No. 2007-219130 (Patent Document 8) discloses that the signal strength of the dark field detection image of the dark field detection image of the focus position and / or the hole pattern where the signal strength of the dark field detection image of the dot pattern is maximum. A method for detecting a defect of a mask blank by setting the focus position to be described is posted.

JP 2003-114200 A JP-A-6-349715 US Patent Application Publication No. 2004/0057107 JP 2001-174415 A JP 2002-333313 A Japanese Patent Laid-Open No. 11-354404 JP 2005-241290 A JP 2007-219130 A

  However, when the present inventor examined the defect inspection technique for the mask blank described above, the following became clear.

  For example, although the dark field detection method using EUV light disclosed in Patent Document 1 described above can detect a defective portion with high sensitivity as a bright spot, it varies due to a difference in surface characteristics of the mask blank or illumination light source intensity. It is not a detection signal processing method considering the signal level.

  Further, for example, in the X-ray microscope method using the bright field disclosed in the above-mentioned Patent Document 2, since only the reflectance of the multilayer film is examined, it is not possible to detect all the defects that cause the phase change.

  Further, for example, the method combining the bright field inspection and the dark field inspection disclosed in Patent Document 3 described above can perform a high-speed dark field inspection, but the inspection apparatus is complicated and the detection sensitivity is not high. It is not a detection signal processing method considering the signal level.

  Further, for example, the methods using the lasers disclosed in Patent Documents 4 and 5 described above are sufficiently small in the size of the defect to be detected compared to the inspection wavelength and lack sensitivity. Furthermore, this method is a method for detecting uneven defects only on the surface of the multilayer film, and cannot detect defects that exist inside the multilayer film and cause abnormal EUV light reflection.

  For example, as disclosed in the above-mentioned Patent Document 6, a peelable pattern is formed on a multilayer mask, and pattern transfer is actually performed, and the transferred pattern is inspected to inspect multilayer defects. Although the method can detect a phase defect, it requires a step of actually performing pattern transfer, and is complicated as an inspection.

  Further, for example, Patent Document 7 described above discloses a detection signal processing method that takes into account a signal level that varies due to variations in illumination light source intensity. This method depends on the amount of variation in illumination light source intensity. A process of multiplying all the pixel intensities of the detection signals collected by the variable to be corrected is required, and the amount of calculation before the defect recognition process is enormous.

  In addition, in any of the inspection methods described above, if a defect that is difficult to correct is detected, the mask blank is handled as a defective product and disposed of even if it is a micro-sized defect.

  An object of the present invention is to provide a defect inspection apparatus and a defect inspection method for a mask blank that can accurately and easily inspect the presence and type of defects in the mask blank.

  Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device employing a reflective exposure method by improving the manufacturing yield of the reflective mask.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  This embodiment is a mask blank inspection apparatus. This mask blank inspection apparatus collects EUV light emitted from a stage on which a mask blank is placed and movable in the X-axis and Y-axis directions, a light source that emits EUV light, and a predetermined mask blank. An illumination optical system that irradiates the inspection area, an imaging optical system that collects reflected light scattered from the inspection area and forms an image, and a detection image obtained by the imaging optical system as a two-dimensional signal Obtained by an image detector that captures and holds as a detection signal, an illumination light intensity monitor that branches a part of the EUV light emitted from the light source, and measures the light intensity of the EUV light emitted from the light source, and an illumination light intensity monitor The threshold value setting circuit calculates a threshold value from the light intensity of EUV light emitted from the light source, and the threshold value comparison circuit compares the signal detected by the image detector with the threshold value calculated by the threshold value setting circuit.

  Further, this embodiment is a mask blank inspection method. Mask blank defects include a step of irradiating a predetermined inspection region of the mask blank with EUV light emitted from a light source, a step of detecting a dark field detection image by capturing reflected light scattered from the inspection region, The step of converting the field-of-view detection image into a two-dimensional detection signal and taking it into the image detector, the step of branching a part of the EUV light emitted from the light source, measuring the light intensity of the EUV light emitted from the light source, and the light emitted from the light source Inspection is performed by a step including a step of calculating a threshold value from the light intensity of EUV light and a step of comparing the detection signal with the threshold value to determine the presence or absence of a mask blank defect.

  Further, this embodiment is a semiconductor device having a step of projecting and exposing an absorber pattern onto a semiconductor substrate using a reflective mask in which an absorber pattern that substantially absorbs EUV light is formed on a mask blank. It is a manufacturing method. The absorber pattern design step compares the step of inspecting the defect of the mask blank, the step of storing the position information of the defect, and the position information of the absorber pattern prepared in advance and the position information of the defect. And a step of changing the arrangement position of the absorber pattern or changing a part of the shape of the absorber pattern when it is determined that the defect impedes the position of the absorber pattern. The mold mask forming step includes a step of determining an absorber pattern designed by the above-described steps and a relative position of the mask blank, and an absorber pattern is formed on the mask blank based on the determined relative position. Process. Further, the defect of the mask blank includes a step of irradiating a predetermined inspection area of the mask blank with EUV light emitted from a light source, a step of detecting a dark field detection image by capturing reflected light scattered from the inspection area, and A step of converting a dark field detection image into a two-dimensional detection signal and taking it into an image detector, a step of branching a part of the EUV light emitted from the light source, and measuring a light intensity of the EUV light emitted from the light source, and a light source Are inspected by a process including a step of calculating a threshold value from the light intensity of EUV light emitted from the light source, and a step of comparing the detection signal with the threshold value to determine the presence or absence of a defect in the mask blank.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  In mask blank defect inspection, the presence and type of mask blank defects can be accurately and easily inspected. In addition, even if a defect is detected by the defect inspection of the mask blank, it is possible to improve the manufacturing yield of the reflective mask by enabling the manufacture of the reflective mask. The manufacturing cost of the adopted semiconductor device can be reduced.

It is the schematic explaining the structure of the inspection apparatus of the mask blank by Embodiment 1 of this invention. It is a figure explaining the mask blank by Embodiment 1 of this invention. (A) is an overall plan view of a mask blank to be inspected, (b) is an enlarged plan view of a main part showing a part of FIG. (A), and (c) is a diagram showing a state of a convex defect. FIG. 4B is a main part sectional view taken along the line AA ′ in FIG. 5B, and FIG. 5D is a main part sectional view taken along the line AA ′ in FIG. It is a figure explaining the defect detection image signal by Embodiment 1 of this invention. It is a top view which shows the division | segmentation and scanning direction of the test | inspection area | region for test | inspecting the whole mask blank by Embodiment 1 of this invention. It is a figure which shows an example of the fluctuation | variation of the defect detection image with respect to two types of mask blanks by Embodiment 1 of this invention. It is a figure which shows notionally the fluctuation | variation of the threshold value set synchronizing with the test | inspection image signal from two types of mask blanks by Embodiment 1 of this invention. It is a flowchart which shows the flow of the defect inspection by Embodiment 1 of this invention. It is the schematic explaining a part of structure of the inspection apparatus of the mask blank using the reflection type diffraction grating by Embodiment 2 of this invention. It is the schematic explaining a part of structure of the inspection apparatus of the mask blank using the other reflection type diffraction grating by Embodiment 2 of this invention. It is a top view which shows the whole mask blank in which the reference mark by Embodiment 3 of this invention was formed. (A) And (b) is the top view which expands and shows the reference mark by Embodiment 3 of this invention, respectively, and sectional drawing along the BB 'line | wire of the same figure (a). (A) And (b) is the top view which looked at the reflective mask by Embodiment 3 of this invention from the pattern surface side, respectively, and sectional drawing in the device area of a reflective mask. (A) And (b) is a top view explaining an example of positioning of an absorber pattern by Embodiment 3 of the present invention, respectively, and a top view explaining other examples of positioning of an absorber pattern. It is a figure which shows the structure concept of the reflection type exposure apparatus by Embodiment 4 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device by Embodiment 4 of this invention. FIG. 16 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the semiconductor device during a manufacturing step following that of FIG. 16; FIG. 18 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the semiconductor device during a manufacturing step following that of FIG. 18; FIG. 20 is an essential part cross-sectional view of the same portion as that of FIG. 15 of the semiconductor device during a manufacturing step following that of FIG. 19;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A mask blank inspection apparatus according to the first embodiment will be described with reference to FIGS. FIG. 1 is a schematic diagram illustrating the configuration of a mask blank inspection apparatus. FIG. 2A is an overall plan view of a mask blank to be inspected, FIG. 2B is an enlarged plan view showing a part of FIG. 2A, and FIGS. 2C and 2D. FIG. 3 is a cross-sectional view of the main part along the line AA ′ in FIG. 2C and 2D show phase defects having different shapes.

  As shown in FIG. 1, the mask blank inspection apparatus includes a stage 2 for mounting a reflective mask blank MB, a light source 1 for generating EUV light (inspection light, illumination light) BM, an illumination optical system CIO, a connection Image optical system DPO, two-dimensional array sensor (image detector) SE, sensor circuit 5, pattern memory 6, threshold setting circuit 8, threshold comparison circuit 9, timing control circuit 10, mask stage control circuit 11, position circuit 12 , And a system control computer 18 for controlling the operation of the entire apparatus.

  The imaging optical system DPO is, for example, a Schwarzschild optical system with a condensing NA = 0.25 and a central light shielding NA = 0.1, and the magnification is 26 times. A mask blank MB to be inspected for defects is placed on the stage 2, and EUV light BM having a central wavelength of 13.5 nm emitted from the light source 1 is irradiated onto a predetermined area of the mask blank MB through the illumination optical system CIO. Of the reflected light from the mask blank MB, the light scattered at the defect portion forms a convergent beam SL1 via the imaging optical system DPO and is condensed on the two-dimensional array sensor SE. As a result, the defect on the mask blank MB is captured by the two-dimensional array sensor SE and detected as a bright spot in the inspection image.

  Here, the defect 21 of the mask blank according to the first embodiment will be described with reference to FIG. Usually, the mask blank MB is made of a multilayer film ML in which silicon (Si) and molybdenum (Mg) are alternately laminated on the mask substrate MS so that the reflectance of the EUV light BM having a wavelength of 13.5 nm is sufficiently obtained. Formed and manufactured. Further, a capping layer (not shown) is formed on the uppermost layer for the purpose of protecting the surface. When the multilayer film ML is formed, if fine particles such as foreign matters exist on the mask substrate MS, the multilayer film ML is affected by the influence, and as shown in FIG. A so-called convex phase defect 22 having a convex surface is generated. On the other hand, when a minute depression exists on the mask substrate MS, for example, a so-called concave phase defect 23 in which the surface of the multilayer film ML is concave is generated as shown in FIG.

  Further, as shown in FIG. 1 described above, the EUV light BM emitted from the light source 1 and shaped by the illumination optical system CIO is bent by the multilayer mirror PM to illuminate the inspection area of the mask blank MB. The incident direction of the EUV light BM is set so as to substantially coincide with the normal direction of the mask blank MB. The imaging optical system DPO includes a concave mirror L1 and a convex mirror L2, and is configured as a Schwarzschild optical system in which an exit aperture is provided at the center of the concave mirror L1. Of the light reflected by the inspection area of the mask blank MB, specular reflection light traveling in the regular reflection direction and in the vicinity thereof is blocked by the convex mirror L2. On the other hand, the scattered light enters the concave mirror L1, is enlarged and projected according to the combination magnification of the concave mirror L1 and the convex mirror L2, passes through the exit aperture of the concave mirror L1, and travels toward the two-dimensional array sensor SE having a large number of pixels. Are emitted.

  By adopting such a dark field optical system, scattered light is not generated in a region where there is no defect on the mask blank MB, and only the specular reflection light is not captured by the imaging optical system DPO. It does not enter the two-dimensional array sensor SE. On the other hand, scattered light is generated in a portion where a defect exists on the mask blank MB, and is captured by the imaging optical system DPO and enters the two-dimensional array sensor SE. Therefore, a bright signal can be obtained only for pixels corresponding to a portion where a defect exists, and an inspection with a high S / N ratio can be realized. The two-dimensional detection signal obtained in this way is sequentially stored in the pattern memory 6 via the sensor circuit 5.

  In such a defect inspection process, a part of the EUV light BM illuminating the mask blank MB is a thin film beam splitter BSP in which only 7 to 10 pairs of silicon (Si) and molybdenum (Mo) are alternately laminated. The light is bent approximately 90 degrees and enters the illumination light intensity monitor 7. The information on the irradiation light intensity obtained here is sent to the threshold value setting circuit 8, and a threshold value to be applied to the defect detection image is calculated by a method described later.

  In the mask blank inspection apparatus according to the first embodiment, various data files 13 related to the mask or the mask blank MB can be referred to. Further, the calculated threshold value can be stored in the threshold value storage file 14, and the defect information detected by the method described later can be stored in the storage device 15.

  Next, a method for determining the presence of a defect from the threshold value and the defect detection image according to the first embodiment will be described with reference to FIG. FIG. 3 is a diagram for explaining a part of a signal cut out in the one-dimensional direction from the inspection image obtained by the above-described two-dimensional array sensor SE and stored in the pattern memory 6. The horizontal axis represents the pixel number representing the one-dimensional direction position, and the vertical axis represents the signal intensity of each pixel. In FIG. 3, the inspection image is represented by an intensity distribution 24, and a pixel position exceeding a separately defined threshold TH1 is recognized as a defect position. Here, an example is shown in which two phase defects are found.

  Here, the intensity of the inspection image corresponding to the portion having no defect is lower than the threshold value TH1. In an ideal dark field inspection, the intensity of an inspection image in an area having no defect is “0”. However, actually, an intensity signal of the background level BG appears due to a dark current component that depends on the scattered light caused by the surface roughness of the mask blank MB or depending on the electrical characteristics of the two-dimensional array sensor SE. Furthermore, noise components due to various factors are also included. In particular, the intensity of scattered light resulting from the surface roughness of the mask blank MB varies with different mask blanks MB, and fluctuates when the intensity of the EUV light BM varies.

  On the other hand, in order to improve the detection reliability, it is necessary to set a threshold value TH1 that is larger than the background level BG including noise. Therefore, it is necessary to always set the threshold value TH1 suitable for the intensity of the inspection image.

  Next, a method for inspecting the entire surface in a predetermined region of the mask blank MB according to the first embodiment will be described with reference to FIGS. FIG. 4 is a plan view showing an inspection region in the mask blank MB, FIG. 5 is a diagram showing an example of fluctuation of the detected image signal, and FIG. 6 is an example of fluctuation of the threshold value set in synchronization with the detected image signal. FIG.

  An area where the imaging optical system DPO can form an inspection image on the two-dimensional array sensor SE is an area of at most 0.5 mm on the mask rank MB plane. Therefore, the inspection images are repeatedly collected while stepping the stage 2 on which the mask blank MB is mounted, for example, by 0.5 mm. Alternatively, while the stage 2 is continuously moved, the two-dimensional array sensor SE is operated in a time delay and integration (TDI: Time Delay and Integration) manner so as to synchronize with the stage 2 to continuously collect inspection images. As shown in FIG. 4, in the first embodiment, the inspection area 25 is divided into a plurality of strip-shaped areas 27 having a width of about 0.5 mm, and each of the strip-shaped areas 27 has a time delay in the direction indicated by the arrow 26. Inspection images were collected by integration operation.

  Next, as shown in FIG. 5, the inspection images of the plurality of strip-shaped regions 27 are connected horizontally, and the intensity of the one-dimensional inspection image therein is extracted. The horizontal axis in FIG. 5 represents the integrated displacement due to the continuous movement of the stage, and therefore represents the inspection time. In FIG. 5, the intensity distributions of the inspection image signals 28 and 29 for two different types of mask blanks are shown superimposed. Here, also in the inspection image signal 28 of one mask blank, the background level changes with time. This is due to variations in illumination intensity. In this state, for example, if the threshold value is fixed so as to extract the inspection image signal of the defective portion indicated by 28-1, the inspection image signal of the defective portion indicated by 28-2 may not be extracted. Further, when the fixed threshold value is applied to the inspection image signal 29 of a different mask blank, the inspection image signal of the defective portion indicated by 29-1 cannot be recognized.

  Therefore, in the first embodiment, when the inspection image shown in FIG. 5 is collected, the variable threshold TH2 or the threshold TH3 as shown in FIG. 6 can be set in synchronization with the inspection image collection. did. That is, by applying the threshold value TH2 shown in FIG. 6 to the inspection image signal 28 shown in FIG. 5 and applying the threshold value TH3 shown in FIG. 6 to the inspection image signal 29 shown in FIG. It is possible to perform a highly reliable defect inspection without being affected by the difference in surface roughness of the light source or the temporal fluctuation of the illumination light intensity.

  Next, details of the mask blank inspection method for maintaining the optimum threshold by changing the threshold according to the first embodiment will be described with reference to the mask blank inspection apparatus shown in FIG. 1 and the flowchart shown in FIG. .

  First, the mask blank MB is placed on the stage 2 that can move in the X-axis and Y-axis directions. Subsequently, prior to the entire surface inspection of the mask blank MB, the mask blank MB is positioned at a predetermined position designated in advance by the mask stage control circuit 11. The predetermined area of the mask blank MB is irradiated with EUV light BM, and inspection images are collected by the two-dimensional array sensor SE (step S101).

  Next, the irradiation light intensity monitor 7 measures and stores the initial value of the intensity of the EUV light BM. At the same time, the background or noise variance is calculated from the inspection image obtained by the two-dimensional array sensor SE, and an initial value of the threshold is set in the threshold setting circuit 8 (step S102). At this time, the background level is desirably a level from which the dark current component of the two-dimensional array sensor SE is removed.

  Next, the mask blank MB is moved to the inspection start position when the entire mask blank MB is inspected (step S103). Thereafter, the stage 2 is continuously moved while the illumination light intensity is monitored, and the inspection is performed. At this time, the timing control circuit 10 gives a synchronization signal to the mask stage control circuit 11 and the sensor circuit 5, and continuously collects inspection image signals by the TDI operation of the two-dimensional array sensor SE. If it is determined that the change of the irradiation light intensity exceeds the predetermined range and the threshold value needs to be changed in the middle of collecting the inspection image signal (step S104), the threshold value is changed (step S105). For the new threshold value, the threshold value setting circuit 8 can determine, for example, the initial value of the threshold value determined in step S102 and the ratio between the illumination light intensity and the illumination light intensity initial value that are sequentially monitored as input parameters. This threshold value is sequentially stored in the threshold value storage file 14.

  Next, the inspection image signal obtained by the TDI operation of the two-dimensional array sensor SE is compared with the updated threshold value to determine the presence or absence of a defect (step S106).

  Next, when it is determined that the inspection image signal exceeds the threshold value and there is a defect (step S107), defect information such as the position or the defect signal level is recorded in the storage device 15 (step S108). At this time, a local inspection image including a defect is appropriately displayed on the image monitor 16 or output to the image output unit 17.

  Next, it is determined whether or not the inspection process for all desired areas of the mask blank MB has been completed (step S109). If there is an area to be inspected, the area is changed (step S110). The process proceeds to step S104, and the determination process for the presence / absence of a defect is repeated again.

  As described above, according to the first embodiment, the optimum threshold value can always be set with respect to the difference in the mask blank MB or the intensity fluctuation of the illumination light for inspection, so that the sensitivity of defect inspection is improved. At the same time, false detection can be greatly reduced, and inspection reliability can be improved. In addition, since the inspection reliability can be improved, the analysis and reliability of defect generation factors can be improved, and the development of a manufacturing technique for a defect-free mask blank MB can be promoted.

(Embodiment 2)
In the second embodiment, instead of the beam splitter BSP provided in the mask blank inspection apparatus described in the first embodiment, an optical branching element composed of a diffraction grating is used to measure the intensity of inspection illumination light. An example of the mask blank inspection apparatus to be performed will be described.

  A part of the mask blank inspection apparatus using the total reflection type diffraction grating according to the second embodiment will be described with reference to FIG. FIG. 8 is a schematic diagram illustrating a partial configuration of the mask blank inspection apparatus. Since the configuration other than the optical branching element is the same as that described in the first embodiment, description thereof is omitted here.

  The diffraction grating GR1 has grooves with a pitch of about 0.9 μm, for example. When the EUV light BM emitted from the illumination optical system CIO is incident on the diffraction grating GR1 at an incident angle of about 80 degrees, the EUV light BM is regularly reflected to irradiate the mask blank MB, and the diffraction angle determined by the grating pitch and the light wavelength. According to FIG. The first-order diffracted light is incident on the illumination light intensity monitor 7. Since the intensity ratio between the specularly reflected light and the diffracted light is determined depending on the surface shape or blaze angle of the diffraction grating GR1, the mask blank MB can be obtained by knowing the intensity of the diffracted light captured by the irradiation light intensity monitor 7. The intensity of the EUV light BM to be irradiated can be calculated.

  Another diffraction grating according to the second embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram illustrating another diffraction grating.

  The reflection type diffraction grating GR2 is formed with a multilayer film in which silicon (Si) and molybdenum (Mo) are alternately laminated on the surface so that a sufficient reflectance of EUV light BM having a wavelength of 13.5 nm can be obtained. It has a periodic structure of about 160 nm. When the EUV light BM is incident on the diffraction grating GR2 at an incident angle of about 15 degrees, the EUV light BM that irradiates the mask blank MB and the light that enters the illumination light intensity monitor 7 can be separated. FIG. 9 shows only a part for branching the EUV light BM, but this light branching means is appropriately incorporated in a part between the light source 1 and the area where the mask blank MB is mounted, or in the illumination optical system CIO. Thus, it is possible to always monitor the illumination light intensity while executing the defect inspection of the mask blank MB.

  As described above, a part of the illumination light is guided to the illumination light intensity monitor 7 by the light branching element using the diffraction gratings GR1 and GR2, and the illumination light intensity is measured. If it is determined to be necessary, the threshold value is changed. be able to.

  As described above, according to the second embodiment, by using the rigid diffraction gratings GR1 and GR2, the light branching is stably performed, and the accuracy of the illumination light intensity monitor 7 is also improved. As a result, the threshold value is appropriately changed, and the reliability of the defect inspection apparatus is improved.

(Embodiment 3)
The structure and manufacturing method of the reflective mask according to the third embodiment will be described.

  First, the structure of the mask blank according to the third embodiment will be described with reference to FIGS. FIG. 10 is a plan view showing the entire mask blank on which the reference mark is formed, and FIGS. 11A and 11B are an enlarged plan view showing the reference mark and a BB ′ line in FIG. FIG.

  As shown in FIG. 10, the mask blank MB on which the reference mark 31 is formed is, for example, rectangular, and the reference mark 31 is provided in advance in the vicinity of at least two adjacent portions of the four corners.

  As shown in FIG. 11, a concave portion 32 having a fine width is formed in advance on a part of the surface of a mask substrate (ultra-smooth substrate) MS constituting the mask blank MB by FIB (Focused Ion Beam) or the like. The reference mark 31 is formed by depositing the multilayer film ML so as to cover the recess 32. Here, the case where a pair of recessed parts 32 comprises the one reference mark 31 is illustrated. Although not particularly limited, the planar dimension of the recess 32 is, for example, about 0.2 to 2 μm.

  When the concave portion 32 is observed with the EUV light BM, it can be recognized as a pattern portion with a large phase change. Therefore, using the reference mark 31 as a reference for coordinates on the mask blank MB, the position of the defect detected by the method described in the first embodiment can be defined by a relative coordinate based on the reference mark 31. it can.

  Next, the structure and manufacturing method of the reflective mask according to the third embodiment will be described with reference to FIGS. 12A and 12B are a plan view of the reflective mask viewed from the pattern surface side and a cross-sectional view in the device area of the reflective mask, respectively, and FIGS. 13A and 13B are positioning of the absorber pattern, respectively. It is a top view explaining the other example of the top view explaining an example, and positioning of an absorber pattern.

  As shown in FIG. 12A, the reflective mask M for EUV exposure is manufactured by forming an absorber pattern made of a material that absorbs EUV light BM on the surface of a mask blank MB. The central part of the reflective mask M has a device pattern area MDE having an integrated circuit pattern, and the peripheral part includes an alignment mark area MA1, including a mark for alignment of the reflective mask M or a wafer alignment mark. MA2, MA3 and MA4 are arranged.

  As shown in FIG. 12B, in the device pattern area MDE of the reflective mask M, the multilayer film ML described above is deposited on a mask substrate MS such as quartz glass or a low thermal expansion material, and a capping layer is formed thereon. CAP is attached. On top of this, an absorber pattern ABS is provided via a buffer layer BUF. Although not shown, an antireflection film that suppresses reflection of ultraviolet light is provided as necessary. On the other hand, a metal film CF for electrostatic chucking of the reflective mask M is coated on the back side of the mask substrate MS.

  When manufacturing the reflective mask M, first, the positional information of the defect of the mask blank MB is stored in advance by the inspection method described above. At this time, the position coordinates of the defect can be accurately grasped by using the reference mark 31 described above.

  Subsequently, based on the stored defect position information, a relative position between the absorber pattern mask and the mask blank for defining the formation position of the absorber pattern is determined. At this time, for example, as shown in FIG. 13A, the absorber pattern mask can be positioned so that the absorber pattern ABS covers the phase defect PD on the mask blank. Then, the absorber pattern ABS is formed on the mask blank based on the determined relative position. Since the obtained reflective mask has defects hidden under the absorber pattern ABS, for example, there is no problem in the exposure projection of the hole pattern 33 onto the semiconductor substrate.

  Further, when the phase defect PD on the mask blank is small so as not to affect the transfer by itself, if the absorber pattern ABS does not exist in the vicinity thereof, it may cause a variation in the dimension of the pattern to be projected and exposed. Must not. Therefore, for example, as shown in FIG. 13B, only when the phase defect PD is fine, the absorber pattern ABS is positioned so that the absorber pattern ABS is sufficiently separated from the phase defect PD, and the determined relative position is determined. Based on the above, the absorber pattern ABS is formed on the mask blank. In the obtained reflective mask, since the phase defect PD does not exist in the vicinity of the absorber pattern ABS, pattern transfer can be performed without hindering the exposure projection of the absorber pattern ABS onto the semiconductor substrate.

  As described above, the method of substantially removing the influence of the phase defect PD by adjusting the arrangement position of the entire prepared absorber pattern ABS on the mask blank has been described. In addition to this method, for example, in an area where the pattern density is relatively small, absorption that is transferred by changing the shape of a part of the absorber pattern ABS within a range that does not affect the performance of the finally completed semiconductor device. The local absorber pattern ABS may be redesigned so that the distance between the body pattern ABS and the phase defect PD is greater than or equal to a predetermined distance.

  In order to form the absorber pattern ABS, after the inspection of the mask blank MB is completed, the absorber material is first uniformly deposited, and then a mask pattern drawing method using normal electron beam lithography or the like is employed. . Even if the absorber material is uniformly deposited, the concave portion 32 constituting the reference mark 31 described above appears on the surface of the absorber material, and this can be detected with an electron beam. Therefore, the reference mark 31 can be used also in the formation of the absorber pattern ABS, and the absorber pattern ABS that is not affected by the phase defect PD as described above can be formed.

  Note that the method of forming the reference mark 31 is not limited to the above-described forming method. For example, after forming the multilayer film ML on the mask substrate MS, the fiducial mark 31 can be formed by irradiating the multilayer film ML with FIB or short wavelength laser light. Even if a method of optically detecting the edge position of the mask blank MB is employed, the same effect can be obtained.

  As described above, according to the third embodiment, the position of the phase defect PD can be specified, and the positional relationship between the absorber pattern ABS for defining the integrated circuit and the phase defect PD of the mask blank MB can be adjusted. it can. As a result, the frequency with which the mask blank MB having the phase defect PD can be used as a non-defective product is increased, the manufacturing yield of the mask blank MB is greatly improved, and the cost of the reflective mask M to be manufactured can be reduced.

(Embodiment 4)
A method of manufacturing a semiconductor device using a reflective mask for EUV exposure according to the fourth embodiment will be described with reference to FIGS. FIG. 14 is a view showing a configuration concept of a reflection type exposure apparatus, and FIGS.

  As shown in FIG. 14, the reflective mask M is manufactured by the mask manufacturing method according to the third embodiment described above. The EUV light having a central wavelength of 13.5 nm emitted from the light source 40 irradiates the pattern surface of the reflective mask M through the illumination optical system 41 composed of a plurality of multilayer mirrors. The reflected light from the pattern surface passes through a reduction projection optical system 42 (for example, a magnification of ¼) constituted by a plurality of multilayer mirrors and forms an image on the wafer 43. The wafer 43 is mounted on a stage 44 that can move in the plane, and a circuit pattern corresponding to the reflective mask M is transferred to a desired region of the wafer 43 by repeating the movement of the stage 44 and pattern exposure.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment will be described. Here, a case where a twin well type CMIS (Complimentary Metal Insulator Semiconductor) circuit is manufactured is exemplified, but the present invention can be applied to other various types of circuits. 15 to 20, a region indicated by reference numeral 100p is a pMIS formation region, and a region indicated by reference numeral 100n is an nMIS formation region.

  First, as shown in FIG. 15, a substrate 101 made of single crystal silicon (Si) (at this stage, a planar thin semiconductor plate called a semiconductor wafer) is prepared. Next, an n-well 102n and a p-well 102p are formed on the substrate 101. An impurity exhibiting n-type conductivity, such as phosphorus (P) or arsenic (As) is introduced into the n-well 102n. Further, p-type conductivity, for example, p-type impurity boron (B) is introduced into the p-well 102p.

  The n well 102n and the p well 102p are formed as follows, for example. First, alignment marks for mask alignment are formed on the substrate 101 (not shown). This alignment mark can be formed at the time of wafer formation by adding a selective oxidation step. Subsequently, an oxide film 103 is formed on the substrate 101, and a resist pattern 104 for an implantation (abbreviation of ion implantation) mask is formed on the oxide film 103 by using normal photolithography. Thereafter, phosphorus (P) or arsenic (As) is ion-implanted to form an n-type well 102n.

  Next, as shown in FIG. 16, ashing is performed to remove the resist pattern 104, and then the oxide film 103 is removed. Subsequently, an oxide film 105 is formed on the substrate 101, and a resist pattern 106 for an implantation mask is formed on the oxide film 105 by using normal photolithography. Thereafter, boron (B) is ion-implanted to form the p-type well 102p.

  Next, as shown in FIG. 17, after removing the resist pattern 106 by performing an ashing process, a separation field insulating film 107 made of, for example, silicon oxide is formed on the main surface of the substrate 101 in the shape of a groove type isolation. Form. As for the shape of the groove type isolation, for example, the minimum dimension is as small as 36 nm on the wafer, and the dimensional accuracy is required to be as severe as 3.5 nm. Therefore, EUV lithography can be used as lithography for forming this groove type isolation.

  In the active region surrounded by the field insulating film 107, an nMIS 100n and a pMIS 100p are formed. Each of the gate insulating films 108 of the nMIS 100n and the pMIS 100p is made of, for example, silicon oxide and is formed by a thermal oxidation method or the like. The gate electrodes 109 of the nMIS 100n and the pMIS 100p are required to have strict values such as a minimum dimension as small as 32 nm on the wafer and a dimensional accuracy of 3 nm. Therefore, after depositing a conductive film made of low resistance polycrystalline silicon (Si) using, for example, a CVD (Chemical Vapor Deposition) method, a resist pattern is formed using EUV lithography, and the gate electrode 109 is formed by etching. Form. Lithography in this process is generally referred to as gate layer lithography, and requires extremely fine pattern transfer with high dimensional accuracy.

  The semiconductor region 110 of the nMIS 100n is formed in a self-aligned manner with respect to the gate electrode 109 by introducing, for example, phosphorus (P) or arsenic (As) into the substrate 101 using the gate electrode 109 as a mask, by ion implantation or the like. The Further, the semiconductor region 111 of the pMIS 100p is formed in a self-aligned manner with respect to the gate electrode 109 by introducing, for example, boron (B) into the substrate 101 by using the gate electrode 109 as a mask by an ion implantation method or the like.

  Here, the gate electrode 109 is not limited to being formed of a single layer film of low-resistance polycrystalline silicon (Si), and can be variously changed. For example, the gate electrode 109 may have a so-called polycide structure in which a silicide layer such as tungsten silicide or cobalt silicide is provided on a low-resistance polycrystalline silicon film. Alternatively, the gate electrode 109 is formed by interposing a barrier conductor film such as titanium nitride (TiN) or tungsten nitride (WN) on a low-resistance polycrystalline silicon film, and further forming a metal film such as tungsten (W). A so-called polymetal structure may be provided.

  Next, as shown in FIG. 18, an interlayer insulating film 112 made of silicon oxide is formed on the substrate 101 using, for example, a CVD method, and then a polycrystalline silicon film for wiring is formed on the interlayer insulating film 112 by CVD. Deposit by the method. Subsequently, the polycrystalline silicon film is patterned by lithography and etching, and then impurities are introduced into a predetermined region of the patterned polycrystalline silicon film, thereby forming a wiring 113L and a resistor 113R made of the polycrystalline silicon film.

  Next, as shown in FIG. 19, a silicon oxide film 114 is deposited on the substrate 101 by using, for example, a CVD method or the like. Then, a resist pattern is formed on the interlayer insulating film 112 and the silicon oxide film 114 by using EUV lithography, and a connection hole 115 is formed by etching to expose a part of the semiconductor regions 110 and 111 and the wiring 113L. To do. Since minute holes are difficult to resolve due to the influence of light diffraction, EUV lithography technology having high resolution is applied to the lithography for connection holes.

  Next, as shown in FIG. 20, after sequentially depositing a metal film made of titanium (Ti), titanium nitride (TiN) and tungsten (W) on the substrate 101 by using, for example, a sputtering method or a CVD method, A resist is formed on the metal film by using EUV lithography, and the first wiring layer 116 is formed by an etching process. The first wiring layer 116 includes a fine dense pattern and an isolated pattern, and has a complicated layout shape because the wiring is routed around neighboring wirings or connected between the wirings. For this reason, the lithography of the first wiring layer 116 is also required to have high resolution and dimensional accuracy.

  Thereafter, the final product can be manufactured by forming the second wiring layer (not shown) and the like in the same manner as the first wiring layer 116. In the above-described series of semiconductor device manufacturing processes, sufficiently high resolution performance is required for gate layer lithography, connection hole lithography, and first wiring layer lithography. Therefore, EUV lithography may be applied. desirable.

  For the mask for the gate layer and the first wiring layer, the mask blank was inspected using the defect inspection apparatus and method described in the first and second embodiments, and no defects were confirmed at the mask blank stage. It is preferable to use a reflective mask. Even if a fine defect is detected, if there is no absorber pattern in the vicinity when the mask is manufactured, and if the defect alone is not substantially transferred onto the wafer, it is handled in the same way as no defect. There is a possibility that

  Further, the connection hole mask is inspected for a mask blank using the defect inspection apparatus and method described in the first and second embodiments, and it is confirmed that there is no defect in the vicinity of the connection hole formation planned region in the mask blank stage. It is preferable to use the confirmed reflective mask. Since the area of the connection hole is small and the pattern density is about 5%, the ratio of occurrence of defects near the connection hole is small, and the production yield of the mask blank that can be used by this method is high. Therefore, the manufacturing yield of the semiconductor device manufactured according to the fourth embodiment is higher than that manufactured by performing conventional mask blank defect inspection.

  Thus, according to the fourth embodiment, the mask blank is inspected using the defect inspection apparatus and method described in the first and second embodiments, and the reflective mask described in the third embodiment. And pattern transfer using a reflective mask with high reliability can be performed. For this reason, it becomes possible to improve the performance, reliability, and manufacturing yield of the manufactured semiconductor device, and as a result, it can contribute to the cost reduction of the semiconductor device.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the manufacture of a semiconductor device that requires fine processing.

DESCRIPTION OF SYMBOLS 1 Light source 2 Stage 5 Sensor circuit 6 Pattern memory 7 Illumination light intensity monitor 8 Threshold setting circuit 9 Comparison circuit 10 with threshold 10 Timing control circuit 11 Mask stage control circuit 12 Position circuit 13 Various data files 14 Threshold storage file 15 Storage device 16 Image Monitor 17 Image output unit 18 System control computer 21 Defect 22, 23 Phase defect 24 Intensity distribution 25 Inspection region 26 Arrow 27 Strip region 28, 29 Inspection image signal 28-1, 28-2, 29-1 Inspection image of defective part Signal 31 Reference mark 32 Recess 33 Hole pattern 40 Light source 41 Illumination optical system 42 Reduction projection optical system 43 Wafer 44 Stage 100n nMIS
100p pMIS
101 substrate 102n n well 102p p well 103 oxide film 104 resist pattern 105 oxide film 106 resist pattern 107 field insulating film 108 gate insulating film 109 gate electrodes 110 and 111 semiconductor region 112 interlayer insulating film 113L wiring 113R resistance 114 silicon oxide film 115 connection Hole 116 First wiring layer ABS Absorber pattern BG Background level BM EUV light (inspection light, illumination light)
BSP Beam splitter BUF Buffer layer CAP Capping layer CIO Illumination optical system CF Metal film DPO Imaging optical system GR1, GR2 Diffraction grating L1 Concave mirror L2 Convex mirror M Reflective mask MA1, MA2, MA3, MA4 Alignment mark area MB Mask blank MDE Device pattern area ML Multilayer film MS Mask substrate (Ultra smooth substrate)
PD phase defect PM multilayer mirror SE 2D array sensor (image detector)
SL1 convergent beam TH1, TH2, TH3 threshold

Claims (12)

A stage on which a mask blank is placed and movable in the X-axis and Y-axis directions;
A light source that emits EUV light;
An illumination optical system that collects EUV light emitted from the light source and irradiates a predetermined inspection area of the mask blank;
An imaging optical system that collects reflected light scattered from the region to be inspected to form an image;
An image detector that captures a detection image obtained by the imaging optical system as a two-dimensional signal and holds it as a detection signal;
An illumination light intensity monitor that branches a part of the EUV light emitted from the light source and measures the light intensity of the EUV light emitted from the light source;
A threshold setting circuit for calculating a threshold from the light intensity of EUV light emitted from the light source obtained by the illumination light intensity monitor;
A threshold comparison circuit that compares a signal detected by the image detector with a threshold calculated by the threshold setting circuit;
A defect inspection apparatus for a mask blank, comprising:   2. The defect inspection apparatus for a mask blank according to claim 1, wherein the imaging optical system is a dark field optical system.   2. The mask blank defect inspection apparatus according to claim 1, wherein the means for branching a part of the EUV light emitted from the light source is a multilayer film in which silicon and molybdenum are alternately laminated. Defect inspection equipment.   2. The defect inspection apparatus for a mask blank according to claim 1, wherein means for branching a part of the EUV light emitted from the light source is a reflection type diffraction grating.   2. The defect inspection apparatus for a mask blank according to claim 1, further comprising a stage driving unit for continuously moving the stage in a plane at a constant speed, and the image detector is synchronized with the continuous movement of the stage. A defect inspection apparatus for a mask blank, which is a two-dimensional array sensor that enables a delay integration operation. (A) irradiating a predetermined inspection area of a mask blank with EUV light emitted from a light source;
(B) capturing reflected light scattered from the region to be inspected to detect a dark field detection image;
(C) converting the dark field detection image into a two-dimensional detection signal and taking it into an image detector;
(D) branching part of the EUV light emitted from the light source and measuring the light intensity of the EUV light emitted from the light source;
(E) calculating a threshold value from the light intensity of EUV light emitted from the light source;
(F) comparing the detection signal obtained in the step (c) with the threshold value obtained in the step (e) to determine the presence or absence of a defect in the mask blank;
A defect inspection method for a mask blank, comprising:   7. The defect inspection method for a mask blank according to claim 6, wherein the threshold value is changed according to a change in light intensity of EUV light emitted from the light source.   The defect inspection method for a mask blank according to claim 6, wherein in the step (f), the detection signal is compared with the threshold value updated at a timing closest to the timing at which the detection signal is captured by the image detector. And determining whether or not the mask blank has a defect. The mask blank defect inspection method according to claim 6, wherein before the step (d),
(G1) irradiating EUV light emitted from the light source onto a predetermined area of the mask blank;
(G2) capturing reflected light scattered from the predetermined region and detecting a dark field detection image;
(G3) converting the dark field detection image into a two-dimensional detection signal and taking it into the image detector;
(G4) branching a part of the EUV light emitted from the light source and measuring an initial value of the light intensity of the EUV light emitted from the light source;
(G5) A defect inspection method for a mask blank, further comprising a step of setting an initial value of a threshold value corresponding to the detection signal obtained in the step (g3). A method of manufacturing a semiconductor device comprising a step of projecting and exposing the absorber pattern onto a semiconductor substrate using a reflective mask in which an absorber pattern that substantially absorbs EUV light is formed on a mask blank,
The design process of the absorber pattern is as follows:
(A) inspecting the mask blank for defects;
(B) storing the position information of the defect;
(C) comparing the position information of the absorber pattern prepared in advance with the position information of the defect;
(D) When it is determined that the defect impedes the position of the absorber pattern, the step of changing the arrangement position of the absorber pattern or changing the shape of a part of the absorber pattern; A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device comprising a step of projecting and exposing the absorber pattern onto a semiconductor substrate using a reflective mask in which an absorber pattern that substantially absorbs EUV light is formed on a mask blank,
The design process of the absorber pattern is as follows:
(A) inspecting the mask blank for defects;
(B) storing the position information of the defect;
(C) comparing the position information of the absorber pattern prepared in advance with the position information of the defect;
(D) When it is determined that the defect impedes the position of the absorber pattern, the step of changing the arrangement position of the absorber pattern or changing the shape of a part of the absorber pattern; Including
The step of forming the reflective mask includes
(E) determining the relative position of the absorber pattern designed by the process including the process (d) from the process (a) and the mask blank;
(F) forming the absorber pattern on the mask blank based on the determined relative position, and a method for manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the step (a) includes:
(A1) irradiating a predetermined inspection area of the mask blank with EUV light emitted from a light source;
(A2) capturing reflected light scattered from the inspection region and detecting a dark field detection image;
(A3) converting the dark field detection image into a two-dimensional detection signal and taking it into an image detector;
(A4) branching a part of the EUV light emitted from the light source and measuring the light intensity of the EUV light emitted from the light source;
(A5) calculating a threshold value from the light intensity of EUV light emitted from the light source;
(A6) comparing the detection signal obtained in the step (a3) with the threshold value obtained in the step (a5) to determine the presence or absence of a defect in the mask blank;
A method for manufacturing a semiconductor device, further comprising:

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