JP2010263086A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing degradation of charge retention characteristics of a nonvolatile memory cell. <P>SOLUTION: The nonvolatile memory cell includes a tunnel insulation film 2, a charge storage layer 3, an insulation layer 4 (4<SB>1</SB>, 4<SB>2</SB>), a control electrode 5, and a source/drain region 6, and also includes element isolation insulation films 7, wherein the insulation layer 4 includes, in a channel width direction, a first insulation layer 4<SB>1</SB>in contact with the upper surface of the charge storage layer 3, and a second insulation layer 4<SB>2</SB>in contact with an end of the charge storage layer 3; and the upper surfaces of the element isolation insulation films 7 located outside the second insulation layer 4<SB>2</SB>are located above an interface between the tunnel insulation film 2 and the charge storage layer 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an electrically rewritable nonvolatile memory cell.

  A NAND flash memory is known as one of electrically rewritable semiconductor memories (Patent Document 1). Since NAND flash memory is advantageous for miniaturization, its capacity is increasing.

  In the NAND type flash memory, a memory cell column is provided in which a plurality of memory cells are arranged in the word line direction through an element isolation insulating film. Each of the plurality of memory cells includes a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode (charge storage layer) provided on the tunnel insulating film, and an interelectrode insulating film provided on the floating gate electrode And a control gate electrode (word line) provided on the interelectrode insulating film. In the word line direction, the control gate electrode is continuously provided in adjacent memory cells.

  In a NAND flash memory, suppression of leakage current is one of important issues. This is because the leakage current causes deterioration of charge retention characteristics of the nonvolatile memory cells constituting the NAND flash memory.

  The cause of the leak current is, for example, the manufacturing process used and the type of film used. Specifically, the film constituting the device is damaged by the RIE (Reactive Ion Etching) process or chemical mechanical polishing (CMP), or the inter-electrode insulating film has a high dielectric constant but a defect. It is possible to use a dielectric film called a high-k film that has a disadvantage that cannot be ignored.

JP-A-8-125148

  An object of the present invention is to provide a semiconductor device capable of suppressing deterioration of charge retention characteristics of a nonvolatile memory cell.

  A semiconductor device according to one embodiment of the present invention is a semiconductor substrate, a nonvolatile memory cell formed on the semiconductor substrate, a tunnel insulating film formed on the semiconductor substrate, and formed on the tunnel insulating film A charge storage layer, an insulating layer formed on the charge storage layer, a control electrode formed on the insulating layer, and a pair of sources / sources formed on the surface of the semiconductor substrate at a predetermined distance. A non-volatile memory cell including a drain region and having a channel length direction as a direction in which the pair of source / drain regions are separated, and an element isolation insulating film filling an element isolation groove formed in the semiconductor substrate The upper surface of the element isolation insulating film is above the interface between the tunnel insulating film and the charge storage layer in a direction perpendicular to the channel length direction, In a direction orthogonal to the direction, the insulating layer includes a first insulating layer in contact with the upper surface of the charge storage layer and a second insulating layer in contact with a side surface of the charge storage layer, An upper end portion of the element isolation insulating film facing the side surface is in contact with the side surface of the charge storage layer through the second insulating layer.

  A semiconductor device according to another aspect of the present invention includes a semiconductor substrate, a nonvolatile memory cell formed on the semiconductor substrate, a tunnel insulating film formed on the semiconductor substrate, and the tunnel insulating film A charge storage layer formed on the charge storage layer, a high dielectric constant insulating layer formed on the charge storage layer and having a higher dielectric constant than silicon oxide, a control electrode formed on the high dielectric constant insulating layer, A non-volatile memory cell including a pair of source / drain regions formed on a surface of a semiconductor substrate at a predetermined distance, and a direction in which the pair of source / drain regions are separated is a channel length direction; An element isolation insulating film embedded in an element isolation groove formed in a semiconductor substrate, and the charge storage facing the high dielectric constant insulating layer in a direction orthogonal to the channel length direction On the top surface of, wherein the leakage current suppressing layer for suppressing a leakage current between the charge storage layer and the high dielectric constant insulating layer is selectively provided.

  According to the present invention, a semiconductor device capable of suppressing leakage current can be realized.

FIG. 2 is a cross-sectional view schematically showing a cross section of a nonvolatile memory cell constituting the nonvolatile semiconductor memory device according to the first embodiment. Sectional drawing for demonstrating the effect of the non-volatile memory cell which comprises the non-volatile semiconductor memory device by 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of the non-volatile memory cell which comprises the non-volatile semiconductor memory device of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing which shows typically the cross section of the non-volatile memory cell which comprises the non-volatile semiconductor memory device by 2nd Embodiment. The energy band figure of the non-volatile memory cell which comprises the non-volatile semiconductor memory device by 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of the non-volatile memory cell which comprises the non-volatile semiconductor memory device of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process following FIG. Sectional drawing for demonstrating the manufacturing process following FIG. FIG. 24 is a cross-sectional view for explaining a manufacturing step following FIG. 23. Sectional drawing which shows typically the cross section of the non-volatile memory cell of a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a cross section of a non-volatile memory cell constituting the non-volatile semiconductor memory device according to the first embodiment. In the present embodiment, a nonvolatile memory cell having a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure will be described as an example.

  FIG. 1A is a cross-sectional view schematically showing a cross section of the nonvolatile memory cell in the word line direction (channel width direction). FIG. 1B is a cross-sectional view schematically showing a cross section of the nonvolatile memory cell in the bit line direction (channel length direction).

  In the figure, reference numeral 1 denotes a silicon substrate, and a tunnel insulating film 2 is formed on the silicon substrate 1. A charge storage insulating film (charge storage layer) 3 is formed on the tunnel insulating film 2. A block insulating film 4 is formed on the charge storage insulating film 3. A control gate electrode 5 is formed on the block insulating film 4.

  As shown in FIG. 1B, a pair of source / drain regions 6 are formed on the surface of the silicon substrate 1 at a predetermined distance. A tunnel insulating film 2 is formed on the surface (channel region) of the silicon substrate 1 between the pair of source / drain regions 6.

  An element isolation insulating film 7 is formed on the silicon substrate 1. The element isolation insulating film 7 fills an element isolation groove formed in the silicon substrate 1.

Further, the block insulating film 4 is formed on the upper surface of the charge storage insulating film 3 in a direction orthogonal to the direction in which the pair of source / drain regions 6 are separated (channel length direction), that is, in the word line direction (channel width direction). The first block insulating film 4 ₁ (first insulating layer) in contact with the second block insulating film 4 ₂ (second insulating layer) in contact with the end (side surface) of the charge storage insulating film 3 Including.

The FIG. 1 (a), but the second block insulating film 4 ₂ is shown in contact with the entire end portion of the charge storage insulating film 3 (the side surface), the end of the charge storage insulating film 3 (the side surface) it may be a second block insulating film 4 ₂ in contact with the part.

Further, here, the second block insulating film 4 ₂ is further also in contact with the end of the tunnel insulating film 2. FIG. 1A shows an example in which the second block insulating film 4 ₂ is in contact with part of the end portion (upper end portion) of the tunnel insulating film 2, but the second block insulating film 4 ₂ is shown. May be in contact with the entire end portion of the tunnel insulating film 2, or may be in contact with a part or all of the end portion (side surface of the element isolation trench) of the silicon substrate 1 under the tunnel insulating film 2. Absent.

Upper surface of the element isolation insulating film 7 on the outside of the second block insulating film 4 _2, is above the interface between the tunnel insulating film 2 and the charge storage insulating film 3. FIG. 1A shows an example in which the upper surface of the element isolation insulating film 7 is the same height (or substantially the same height) as the upper surface of the charge storage insulating film 3.

FIG. 24 is a cross-sectional view schematically showing a cross section of a nonvolatile memory cell of a comparative example. FIG. 24 corresponds to a cross-sectional view in the channel width direction of FIG. The comparative example, the second block insulating film 4 ₂ no. In FIG. 24, reference numeral 8 indicates a defect region including a defect in the element isolation insulating film 7. During the formation of the element isolation region, the element isolation insulating film 7 is processed by RIE, thereby causing the above defects.

  In the case of the comparative example, a positive bias gate voltage is applied to the control gate electrode 5, electrons are injected from the silicon substrate 1 through the tunnel insulating film 2 into the charge storage insulating film 3, and electrons are injected into the charge storage insulating film 3. When accumulated, the following problems occur.

  That is, since the charge storage insulating film 3 is in direct contact with the defect region 8, some of the electrons (e −) stored in the charge storage insulating film 3 enter the element isolation insulating film 7 through the defect region 8. Moving. Such electron movement 9 causes a leak current to flow, and as a result, the charge retention characteristics deteriorate.

On the other hand, even in the case of this embodiment, as shown in FIG. 2, although the defect region 8 exists in the element isolation insulating film 7, the charge storage insulating film 3 is defective through the _second block insulating film 42. The charge storage insulating film 3 is in contact with the region 8 and is not in direct contact with the defect region 8. Therefore, even if a positive bias gate voltage is applied to the control gate electrode 5, as shown in FIG. 2, the electrons (e ⁻ ) accumulated in the charge storage insulating film 3 are caused by the second block insulating film 4 ₂ . It is blocked and does not move out of the charge storage insulating film 3. Therefore, according to the present embodiment, the leakage current can be suppressed. Since leakage current can be suppressed, deterioration of charge retention characteristics can also be suppressed.

FIG. 2 shows a structure in which the entire end portion (side surface) of the charge storage insulating film 3 is not in direct contact with the defect region 8, but a part of the end portion (side surface) of the charge storage insulating film 3 is shown. Even in the structure directly in contact with the defect region 8, the deterioration of the charge retention characteristics is suppressed as compared with the conventional structure. The structure in which a part of the end portion (side surface) of the charge storage insulating film 3 is in direct contact with the defect region 8 is, for example, the second structure in contact with a part of the end portion (side surface) of the charge storage insulating film 3 described above. This is realized by using the block insulating film 4 ₂ .

Note that the first block insulating film 4 ₁ and the second block insulating film 4 ₂ It may be formed of the same material, or may be formed respectively of different materials. In the case of the same material, the process can be simplified. For different materials, optimum materials for the first block insulating film 4 ₁ as the block insulating film, the effect is highly material to suppress the leakage current with respect to the second block insulating film 42 There is an advantage that it can be used.

  Next, the manufacturing method of this embodiment is demonstrated.

[Fig. 3]
A tunnel insulating film 2 is formed on the silicon substrate 1. Here, a silicon oxide film is formed as the tunnel insulating film 2. Such a silicon oxide film can be formed, for example, by thermal oxidation at 600-1000 ° C. in a dry O ₂ atmosphere or a water vapor atmosphere. The silicon oxide film may be formed by a CVD method or an ALD method. The film thickness of the silicon oxide film is, for example, about 3-9 nm, but may be a film thickness outside this range.

[Fig. 4]
A charge storage layer 3 is formed on the tunnel insulating film 2. Here, a silicon nitride film is formed as the charge storage layer 3. In such a silicon nitride film, for example, dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) are introduced into a reaction furnace set at a temperature of 600 to 800 ° C., and the pressure is maintained at 0.1-1 Torr. Then, the CVD method is used. Here, a silicon nitride film is used as the charge storage layer 3. However, in the case of a nonvolatile memory cell having a floating gate structure, for example, a polycrystalline silicon film is used as the charge storage layer 3.

[Fig. 5]
A silicon oxide film 10 is formed on the charge storage layer 3 by CVD. For example, dichlorosilane (SiH ₂ Cl ₂ ) and nitrogen dioxide (N ₂ O) are introduced into a reaction furnace whose temperature is set to 600 to 800 ° C., and the silicon oxide film 10 is pressurized to 0.1-5 Torr. It is formed by the CVD method performed while maintaining the above. Next, a silicon nitride film 11 is formed on the silicon oxide film 10. For example, this silicon nitride film 11 introduces dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) into a reaction furnace set at a temperature of 600-800 ° C., and maintains the pressure at 0.1-1 Torr. The CVD method is used.

[Fig. 6]
A photoresist film 12 is deposited on the silicon nitride film 11 by a coating method.

[Fig. 7]
The photoresist film 12 is left only in the transistor formation region by a photolithography process (exposure, development).

[Fig. 8]
By the RIE process, the silicon oxide film 10 and the silicon nitride film 11 in a region other than the portion where the photoresist film (resist pattern) 12 remains are removed.

[Fig. 9]
The photoresist film is removed, and thereafter, the charge storage layer 3, the silicon oxide film 2 and the silicon substrate 1 are etched by an RIE process using the silicon oxide film 10 and the silicon nitride film 11 (hard mask) as a mask. Open the separation groove.

[FIG. 10]
By introducing tetraethoxysilane (TEOS) into the reaction furnace at 600-750 ° C. and setting the pressure to about 0.1-5 Torr, silicon oxide that becomes the element isolation insulating film 7 is embedded so that the element isolation trench is embedded. A film is deposited on the entire surface, and then the surface is planarized by CMP to form an element isolation region (STI (Shallow Trench Isolation)) in which the element isolation trench is filled with the element isolation insulating film 7. During the CMP, a defect occurs on the surface (upper surface portion) of the element isolation insulating film 7.

[Fig. 11]
The element isolation insulating film (silicon oxide film) 7 is etched to the same height as the upper surface of the charge storage layer 3 by an RIE process under conditions that allow a selection ratio with the silicon nitride film.

[Fig. 12]
The silicon nitride film 11 remaining on the silicon oxide film 10 is selectively removed by wet etching using a mixed solution of phosphoric acid and water at about 200 ° C.

[FIG. 13]
A photoresist film is deposited on the entire surface by a coating method, and then the photoresist film (resist pattern) 13 is left only in the transistor formation region and other regions in the vicinity thereof by a photolithography process (exposure and development).

[FIG. 14]
The element isolation insulating film (silicon oxide film) 7 in the vicinity of the transistor formation region is selectively etched by the RIE process using the resist pattern 13 as a mask, and the element isolation insulating film (silicon oxide film) 7 in the vicinity of the transistor formation region is etched. The height of the surface (upper surface) is lowered to the lower surface of the charge storage layer 3 or to a position lower than the lower surface. FIG. 14 shows an example of the same height as the lower surface of the charge storage layer 3.

  It should be noted that most of the defects generated in the element isolation insulating film 7 at the time of CMP exist on the upper surface portion of the element isolation insulating film 7, so that the upper surface portion of the element isolation insulating film 7 facing the side surface of the charge storage layer 3 is etched. It is sufficient to remove it.

[FIG. 15]
The photoresist film (resist pattern) 13 is removed.

[FIG. 16]
A block insulating film 4 is formed on the entire surface. Here, a silicon oxide film is formed as the block insulating film 4. Such a silicon oxide film is obtained, for example, by introducing dichlorosilane (SiH ₂ Cl ₂ ) and nitrogen dioxide (N ₂ O) into the reaction furnace set at a temperature of 600-00 ° C. as described above. It can be formed by a CVD method performed while maintaining the pressure at 1-5 Torr.

The block insulating film 4 may be a high dielectric film in addition to the silicon oxide film, for example, an alumina film. As a method for forming an alumina film, for example, trimethylaluminum (TMA) and ozone (O ₃ ) are introduced together into a reaction furnace set at a temperature of 500-700 ° C., and the pressure is maintained at 0.1-5 Torr. There is a CVD method.

As a method for forming an alumina film with better step coverage, for example, trimethylaluminum (TMA) and ozone (O ₃ ) are alternately placed in a reaction furnace at a temperature of 100 to 500 ° C. and a pressure of 0.1 to 5 Torr. There is an ALD method introduced in

[Fig. 17]
A control gate electrode 5 is formed on the block insulating film 4. As the control gate electrode 5, for example, a P-added silicon film is used. Such a P-added silicon film is formed by, for example, a CVD method in which monosilane (SiH ₄ ) and phosphine (PH ₃ ) are introduced into a reaction furnace at a temperature of 400 to 700 ° C. and a pressure of 0.1 to 5 Torr. Can be formed. A metal film may be used for the control gate electrode 5. Thereafter, known steps such as a step of forming a transistor to be a flash memory cell by performing processing in the word line direction are performed.

  According to the embodiment as described above, in the step of FIG. 11, defects are formed on the surface of the element isolation insulating film 7 due to damage by RIE. However, in the steps after FIG. Since the element isolation insulating film 7 formed with is removed, the charge stored in the charge storage layer 3 does not escape through the defects in the element isolation insulating film 7, and the leakage current is suppressed, and the charge is reduced. The retention characteristics can be improved.

(Second Embodiment)
FIG. 18 is a cross-sectional view schematically showing a cross section of a nonvolatile memory cell constituting the nonvolatile semiconductor memory device according to the second embodiment. FIG. 18 corresponds to a cross-sectional view in the channel width direction of FIG.

  In the following drawings, the same reference numerals as those in the previous drawings indicate the same reference numerals or corresponding parts, and detailed description thereof will be omitted.

  In the first embodiment, the silicon oxide film 4 is used as the block insulating film, but in this embodiment, a high dielectric film (high-k film) 4h (for example, an alumina film) is used as the block insulating film. In the present embodiment, a barrier insulating film (leakage current suppressing layer) 20 is provided between the charge storage layer 3 and the high dielectric film 4h. Hereinafter, the barrier insulating film 20 will be further described.

  In the MONOS type nonvolatile memory cell, a positive bias gate voltage is applied to the control gate electrode 5, electrons are injected from the silicon substrate 1 through the tunnel insulating film 2, and electrons are injected into the charge storage layer 3. Is done.

  Here, when the block insulating film is a high dielectric film, since the high dielectric film has more defects than the insulating film such as a silicon oxide film, the electrons accumulated in the charge storage layer are in the high dielectric film. A phenomenon (leakage current) that the control gate electrode is pulled out through a defect occurs, and as a result, there arises a problem that charge retention characteristics deteriorate.

Therefore, in this embodiment, the barrier insulating film 20 is provided between the charge storage layer 3 and the high dielectric film 4h. As shown in the energy band diagram of FIG. 19, the barrier insulating film 20 has a higher energy barrier against electrons (e ⁻ ) than the charge storage layer 3 and the high dielectric film 4h. Therefore, the leakage current that electrons stored in the charge storage layer 3 escape to the control gate electrode 5 through defects in the high dielectric film 4h is suppressed. Therefore, according to the present embodiment, even when a high dielectric film is used as the block insulating film, the leakage current is suppressed and the deterioration of the charge retention characteristics is suppressed.

  In the present embodiment, the barrier insulating film 20 that increases the energy barrier between the charge storage layer 3 and the high dielectric film 4h is used as the leakage current suppression layer. However, the leakage current suppression that suppresses the leakage current by other mechanisms. Layers may be used.

  20 to 23 are cross-sectional views for explaining the manufacturing process of the nonvolatile memory cell constituting the nonvolatile semiconductor memory device of this embodiment.

  First, the steps of FIG. 3 and FIG. 4 described in the first embodiment are performed.

[FIG. 20]
A barrier insulating film 20 is formed on the charge storage layer 3 by a CVD method. The barrier insulating film 20 is, for example, a silicon oxide thin film. The thickness of this silicon oxide thin film is selected, for example, in the range of 1-10 nm, and is, for example, 2-3 nm.

  Thereafter, a silicon nitride film 11 is formed in the same manner as in FIG. 5 of the first embodiment, and further, the steps from FIG. 6 to FIG. 10 of the first embodiment are performed.

[FIG. 21]
The element isolation insulating film (silicon oxide film) is kept until the upper surface of the element isolation insulating film (silicon oxide film) 7 is flush with the upper surface of the barrier insulating film 20 by the RIE process under conditions that allow a selection ratio with the silicon nitride film 11. ) 7 is etched.

[FIG. 22]
Next, the silicon nitride film 11 remaining on the barrier insulating film 20 is selectively removed by wet etching using a mixed solution of phosphoric acid and water at about 200.degree.

[FIG. 23]
A high dielectric insulating film 4h as a block insulating film is formed on the entire surface.

  The high dielectric insulating film 4h is, for example, an alumina film (aluminum oxide film).

The alumina film can be formed by a CVD method. Such an alumina film (CVD alumina film) is formed by, for example, simultaneously introducing trimethylaluminum (TMA) and ozone (O ₃ ) into a reaction furnace set at 500 to 700 ° C. and pressure within a range of 0.1-5 Torr. It can be formed by maintaining

The alumina film can also be formed by an ALD method. Such an alumina film (ALD alumina film), for example, alternately introduces trimethylaluminum (TMA) and ozone (O ₃ ) into a reaction furnace at a temperature of 100 to 500 ° C. and a pressure of 0.1 to 5 Torr. Can be formed. By using the ALD method, an alumina film with good step coverage can be formed.

  Thereafter, as in the first embodiment, a flash memory cell is obtained through known processes such as a control gate electrode forming process and a processing process in the word line direction.

  The present invention is not limited to the embodiment described above. For example, in the above embodiment, the MONOS structure nonvolatile memory cell has been described. However, the present invention can also be applied to a floating gate structure nonvolatile memory cell. In this case, the charge storage insulating film is read as a floating gate electrode, and the block insulating film is read as an interelectrode insulating film (interpoly).

  Further, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Tunnel insulating film, 3 ... Charge storage insulating film (charge storage layer), 4 ... Block insulating film, 4 ₁ ... 1st block insulating film (2nd insulating layer), 4 ₂ ... 1st 2 block insulating film (second insulating layer), 4h... Block insulating film (high dielectric film), 5... Control gate electrode, 6... Source / drain region, 7. DESCRIPTION OF SYMBOLS 9 ... Electron transfer, 10 ... Silicon oxide film, 11 ... Silicon nitride film, 12, 13 ... Photoresist film, 20 ... Barrier insulating film (leakage current suppression layer).

Claims (5)

A semiconductor substrate;
A nonvolatile memory cell formed on the semiconductor substrate, comprising: a tunnel insulating film formed on the semiconductor substrate; a charge storage layer formed on the tunnel insulating film; and a charge storage layer formed on the charge storage layer. An insulating layer, a control electrode formed on the insulating layer, and a pair of source / drain regions formed at a certain distance on the surface of the semiconductor substrate, the pair of source / drain regions being The nonvolatile memory cell having a channel length direction as a separated direction; and
An element isolation insulating film embedded in an element isolation groove formed in the semiconductor substrate,
In the direction orthogonal to the channel length direction, the upper surface of the element isolation insulating film is above the interface between the tunnel insulating film and the charge storage layer,
In a direction orthogonal to the channel length direction, the insulating layer includes a first insulating layer in contact with an upper surface of the charge storage layer, and a second insulating layer in contact with a side surface of the charge storage layer, and the charge An upper end portion of the element isolation insulating film facing the side surface of the storage layer is in contact with the side surface of the charge storage layer through the second insulating layer.   In the direction orthogonal to the channel length direction, a portion below the upper end portion of the element isolation insulating film is also in contact with a side surface of the charge storage layer through the second insulating layer. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are made of the same material. A semiconductor substrate;
A nonvolatile memory cell formed on the semiconductor substrate, comprising: a tunnel insulating film formed on the semiconductor substrate; a charge storage layer formed on the tunnel insulating film; and a charge storage layer formed on the charge storage layer. A high dielectric constant insulating layer having a dielectric constant higher than that of silicon oxide, a control electrode formed on the high dielectric constant insulating layer, and a pair of sources formed on the surface of the semiconductor substrate at a predetermined distance A non-volatile memory cell having a channel length direction as a direction in which the pair of source / drain regions are separated,
An element isolation insulating film embedded in an element isolation groove formed in the semiconductor substrate,
A semiconductor device, wherein a leakage current suppressing layer is selectively provided on an upper surface of the charge storage layer facing the high dielectric constant insulating layer in a direction orthogonal to the channel length direction.   5. The semiconductor device according to claim 4, wherein the charge storage layer is formed of a silicon nitride film or a silicon film, and the leakage current suppression layer is formed of a silicon oxide film.

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