JP2010258527A - Output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variations of a slew rate of an output signal at a time of an off operation of a MOS transistor even if a threshold voltage of the MOS transistor with which an output buffer of an output circuit is equipped varies. <P>SOLUTION: An output circuit includes: an NMOS transistor 15 of an output buffer 8, a transistor on drive circuit 51 configured to turn on the transistor 15; a switchable current source 52 configured to turn off the transistor 15; and a drive control circuit 50 configured to control the transistor on drive circuit 51 and the switchable current source 52 respectively. Electric charges at the gate terminal are pulled out at a fixed current value by the current of the switchable current source 52, even when the gate voltage of the NMOS transistor 15 of the output buffer 8 varies within a range of variations of a threshold voltage Vth. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an output circuit mounted on a semiconductor integrated circuit device.

  FIG. 18 shows a conventional output circuit. Such a conventional output circuit is described in Patent Document 1.

  This output circuit has the effect of suppressing variation in the slew rate of the external output signal SC1 even if the threshold voltage Vth of the NMOS transistor 15 (hereinafter, the threshold voltage is simply referred to as Vth) varies due to the following operation. is there.

  In FIG. 18, in the output circuit 71 provided in the semiconductor integrated circuit 70, the control signal voltage change adjustment circuit 59 is similar to the Vth of the NMOS transistor 60 in the control signal voltage change adjustment circuit 59 when the Vth of the NMOS transistor 15 is small. The drain current capability of the PMOS transistors 10 and 62 is reduced by utilizing this reduction. Similarly, when the Vth of the NMOS transistor 15 is large, the Vth of the NMOS transistor 60 is also increased, thereby increasing the drain current capability of the PMOS transistors 10 and 62. In this way, the slew rate variation of the external output signal SC1 (the drain voltage of the NMOS transistor 15) due to the variation of the Vth of the NMOS transistor 15 can be suppressed.

JP 2007-150991 A

  However, in the conventional circuit configuration shown in FIG. 18, when the NMOS transistor 15 is turned on, there is an effect of suppressing the slew rate variation with respect to the Vth variation, but the Vth when the NMOS transistor 15 is turned off. There is a problem that there is no effect of suppressing the slew rate variation with respect to the variation.

  FIG. 19 is a signal waveform diagram of the conventional output circuit shown in FIG. When the input signal SA1 of the output circuit changes from H level to L level, the signal SB1 that drives the gate of the NMOS transistor 15 changes from L level to H level, and the NMOS transistor 15 is turned on, The external output signal SC1 changes from H level to L level.

  Similarly, when the input signal SA1 changes from L level to H level, the signal SB1 that drives the gate of the NMOS transistor 15 changes from H level to L level, and the NMOS transistor 15 performs an off operation, The external output signal SC1 changes from L level to H level.

  In the output circuit, when the Vth of the NMOS transistor 15 varies, the control voltage change adjusting circuit 59 causes the transition of the external output signal SC1 from the H level to the L level when the transistor 15 is turned on. The variation in the falling slew rate at the time is suppressed, but the variation in the falling slew rate at the transition from the L level to the H level of the external output signal SC1 when the transistor 15 performs the off operation cannot be suppressed.

  With respect to this problem, the above-mentioned Patent Document 1 points out an improvement with an output circuit as shown in FIG. The output circuit of FIG. 20 is a combination of the output circuit shown in FIG. 18 and an output circuit having a configuration in which the NMOS transistor and the PMOS transistor of the output circuit of FIG. 18 are reversed.

  The advantages of this output circuit will be described with reference to the signal waveform diagram of FIG. When the input signal SA changes from the H level to the L level, the control signal voltage change adjusting circuit 59 operates, and the SBN signal that drives the gate of the NMOS transistor 15 becomes the H level. At the same time, when the PMOS transistor 211 is turned on, the SBP signal for driving the gate of the PMOS transistor 215 becomes H level.

  The NMOS transistor 15 of the output buffer 8 is turned on when the signal SBN is changed from L level to H level, and the PMOS transistor 215 of the output buffer 8 is turned off when the signal SBP is changed from L level to H level. To work. Since the NMOS transistor 15 is turned on and the load 56 is driven, the external output signal SC changes from the H level to the L level.

  When the input signal SA changes from the L level to the H level, the control signal voltage change adjusting circuit 259 operates, and the signal SBP that drives the gate of the PMOS transistor 215 becomes the L level. At the same time, when the NMOS transistor 11 is turned on, the signal SBN for driving the gate of the NMOS transistor 15 becomes L level.

  The PMOS transistor 215 of the output buffer 8 is turned on when the signal SBP is changed from the H level to the L level, and the NMOS transistor 15 of the output buffer 8 is turned off when the signal SBN is changed from the H level to the L level. To work. Since the PMOS transistor 215 is turned on and the load 56 is driven, the external output signal SC changes from the L level to the H level.

  In this way, in this output circuit, the output falling transition of the external output signal SC from the H level to the L level is caused by the on operation of the NMOS transistor 15 of the output buffer 8, and from the L level of the external output signal SC. The rising transition to the H level is caused by the on operation of the PMOS transistor 215 of the output buffer 8.

  When the Vth of the NMOS transistor 15 varies, the control signal voltage change adjustment circuit 59 operates to suppress the slew rate variation when the NMOS transistor 15 is on. In other words, the falling slew rate variation at the time of transition of the external output signal SC from the H level to the L level is suppressed.

  When the Vth of the PMOS transistor 215 varies, the control signal voltage change adjusting circuit 259 operates in the same manner as the control signal voltage change adjusting circuit 59 to suppress the slew rate variation when the PMOS transistor 215 is turned on. . In other words, the rising slew rate variation at the time of transition of the external output signal SC from the L level to the H level is suppressed.

  Therefore, the output circuit shown in FIG. 20 does not require a measure for suppressing variation with respect to Vth variation of the slew rate of the drain output terminal during the off operation of the transistors of the output buffer such as the NMOS transistor 15 and the PMOS transistor 215.

  However, in the output circuit of FIG. 20, during the period of the code (A) in which the signal SBP and the signal SNB shown in FIG. 21 simultaneously change from the L level to the H level, the PMOS transistor 215 changes from the on operation to the off operation. Since the NMOS transistor 15 changes from the off operation to the on operation at the same time, there is a moment when the two transistors 15 and 215 simultaneously operate on. When the two transistors 15 and 215 are simultaneously turned on, the power supply VDD and the ground power supply GND are conducted through the two transistors, and a large current flows. This state is called a through state between the PMOS transistor 215 and the NMOS transistor 15, and this large current is called a through current.

  Similarly, the period (B) in which the signal SBP and the signal SNB simultaneously transition from the H level to the L level is a period in which the PMOS transistor 215 changes from the off operation to the on operation, and at the same time, the NMOS transistor 15 operates on. Since there is a period during which the operation changes from off to off operation, there is a moment when these two transistors are turned on simultaneously. When these two transistors are turned on at the same time, as in the period (A), the two transistors are in a through state, and a large through current flows from the power supply VDD to the ground power supply GND.

  During the periods (A) and (B), the characteristics of the NMOS transistor 15 and the PMOS transistor 215 deteriorate over time due to a through state in which a through current flows from the power supply VDD to the ground power supply GND through the NMOS transistor 15 and the PMOS transistor 215. Otherwise, the power supply voltage VDD may fluctuate and noise may be generated through the power supply wiring, resulting in malfunction of the output circuit and other circuits.

  As can be seen from the above description, the output circuit shown in FIG. 20 has a heavy load 56. Therefore, when the NMOS transistor 15 and the PMOS transistor 215 constituting the output buffer 8 need to be capable of driving a large current. The through current becomes a very large current, and this output circuit has a problem in reliability and is not practical.

  Normally, the output circuit when the load 56 is heavy and the drive capability of the NMOS transistor 15 and the PMOS transistor 215 of the output buffer 8 is required has a circuit configuration as shown in FIG.

  In FIG. 22, the output inversion delay circuit 1 is a circuit that outputs the drive signal SBP for driving the PMOS transistor 215 of the output buffer 8 in the inverted form of the input signal SA with a delay of a certain delay time. It is a circuit having the function of a buffer circuit.

  The output inversion delay circuit 1 normally has two different delay times for the delay time D1F when the signal SA switches from the H level to the L level and the delay time D1R when the signal SA switches from the L level to the H level. have.

  Similarly, the output inversion delay circuit 2 is a circuit that outputs the drive signal SBN for driving the NMOS transistor 15 of the output buffer 8 by inverting the input signal SA and delaying it by a certain delay time. It is a circuit having the function of a circuit.

  This output inversion delay circuit 2 also normally has two different delay times for the delay time D2F when the signal SA switches from the H level to the L level and the delay time D2R when the signal SA switches from the L level to the H level. have.

  Further, the delay times D1F and D2R may be omitted. Further, the delay times D2F and D2R may be the same time. In the output circuit configuration shown in FIG. 22, the delay times D2F and D1R must be set to appropriate values in order to prevent the NMOS transistor 15 and the PMOS transistor 215 constituting the output buffer 8 from penetrating.

  The operation of the output circuit shown in FIG. 22 will be described in detail below using the signal waveform diagram of FIG.

  When the input signal SA changes from the H level to the L level, the output inversion delay circuit 1 changes the signal SBP for driving the gate of the PMOS transistor 215 from the L level to the H level after the delay time D1F, and turns off the PMOS transistor 215. Although there is no problem if the delay time D1F is not provided, the delay time D1F may be set as necessary for convenience of output circuit design.

  When the input signal SA changes from the H level to the L level, the output inversion delay circuit 2 changes the signal SBN for driving the gate of the NMOS transistor 15 from the L level to the H level after the delay time D2F, and turns on the NMOS transistor 15. The delay time D2F needs to be set so that the NMOS transistor 15 is turned on after the PMOS transistor 215 is turned off. Thereby, the penetration state (A) shown in FIG. 21 can be prevented.

  When the input signal SA changes from the L level to the H level, the output inversion delay circuit 2 changes the signal SBN for driving the gate of the NMOS transistor 15 from the H level to the L level after the delay time D2R, and turns off the NMOS transistor 15.

  While the NMOS transistor 15 was on, the external output signal SC was at the L level by driving the load 56. When the NMOS transistor 15 is turned off and the load 56 is not driven, the external output signal SC rises to the voltage VDD of the power source in which one end of the load 56 is pulled up. That is, when the NMOS transistor 15 is turned off, the external output signal SC changes from the L level to the H level.

  This point is different in operation from the output circuit of FIG. In the output circuit of FIG. 20, the external output signal SC has transitioned from the L level to the H level as the PMOS transistor 215 is turned on. Further, the slew rate at the time of this transition is determined by the on-operation state of the PMOS transistor 215, and the control signal voltage change adjusting circuit 259 controls the on-operation.

  On the other hand, in the output circuit of FIG. 22, the slew rate when the external output signal SC transits from the L level to the H level is determined by the off operation state of the NMOS transistor 15. As will be described later, it is an object of the present invention to control the slew rate of the external output signal SC by the off operation of the NMOS transistor 15 and to suppress variations in the slew rate even if the threshold voltage Vth of the transistor 15 varies. It is.

  Returning to the description of the operation of the output circuit of FIG. 22 using the signal waveform diagram of FIG. The delay time D2R described above may be omitted. The delay time D2R is set so that the delay times of the output signal SC with respect to the two input signals SA at the falling transition from the H level to the L level and at the rising transition from the L level to the H level are equal. May be.

  When the input signal SA changes from L level to H level, the output inversion delay circuit 1 changes the signal SBP for driving the gate of the PMOS transistor 215 from H level to L level after the delay time D1R, turns on the PMOS transistor 215, and outputs it. The external terminal 54 of the circuit is completely set to the H level. The delay time D1R needs to be set so that the PMOS transistor 215 is turned on after the NMOS transistor 15 is turned off. Thereby, the penetration state (B) shown in FIG. 21 can be prevented.

  As can be seen from the above description, in the output circuit shown in FIG. 22, each slew rate at the falling transition from the H level to the L level and the rising transition from the L level to the H level of the external output signal SC is This is determined by the on / off operation of the NMOS transistor 15 of the output buffer 8. When the conventional output circuit shown in FIG. 18 is applied to the output circuit shown in FIG. 22, that is, the control signal voltage change adjusting circuit 59 shown in FIG. 18 is connected to the output inversion delay circuit 2 and the NMOS transistor 15. When inserted in between, the slew rate at the falling transition of the external output signal SC when the NMOS transistor 15 is in the ON state has an effect of suppressing variation in the threshold voltage Vth of the NMOS transistor 15. However, the slew rate at the rising transition of the external output signal SC during the off operation of the NMOS transistor 15 has no effect of suppressing the Vth variation.

  The present invention solves the above-described conventional problems, and an object of the present invention is to slew the drain voltage during the off operation of the output MOS transistor when the threshold voltage Vth of the output MOS transistor varies in the output circuit. It is to suppress rate variation.

  Also in the output circuit as shown in FIGS. 18 and 20, and other output circuits, the MOS transistor (which may be an NMOS transistor or a PMOS transistor) of the output buffer is turned off, so that the external output signal SC changes its state. It is possible to suppress variations in slew rate with respect to Vth.

  In order to solve the above-described problem, the output circuit of the present invention includes a pre-drive circuit 1 that inputs an input signal SA and outputs a drive signal SB, and the drive signal SB as shown in FIG. The NMOS transistor 15 is of the common source / open drain type that inputs to the gate terminal and outputs an external output signal from the drain terminal.

  The pre-drive circuit 1 outputs a transistor-on operation drive circuit 51 that outputs the drive signal SB for turning on the NMOS transistor 15, and a SW that outputs the drive signal SB for turning off the NMOS transistor 15. A function-equipped current source 52 and a drive control circuit 50 that receives the input signal SA and outputs control signals Son and Soff for controlling the transistor-on-operation drive circuit 51 and the SW function-equipped current source 52, respectively. Composed. The polarities of the input signal SA and the control signals Son and Soff are not particularly defined. Therefore, the relationship between the polarities of the input signal SA and the drive signal SB may be set arbitrarily.

  The SW function current source 52 has one end connected to the gate of the NMOS transistor 15 and the other end connected to the ground power supply GND. The current IG of the current source 52 is characterized in that even if the gate voltage of the NMOS transistor 15 varies within the variation range of the threshold voltage Vth, the charge at the gate terminal is extracted with a constant current value.

  As shown in FIG. 3, the output circuit of the present invention has an SW function capable of switching the current value of the current IG of the current source 52 with SW function by a current value switching signal in the output circuit configuration. When the external output signal SC of the output circuit reaches a certain voltage value, the current value switching signal is changed and the current value switching signal for switching the current value of the variable current source 52 with SW function is output. A circuit configuration in which the output voltage detection circuit 2 to be added is added may be employed.

  The slew rate of the external output signal SC is determined mainly by the gate-drain capacitance value Cgd of the NMOS transistor 15 and the current value of the current IG of the current source 52 with SW function. The slew rate of the external output signal SC can be approximately approximated by the following equation.

Slew rate≈ (current value of current IG / Cgd) (1)
The equation (1) means that even if the threshold voltage Vth of the NMOS transistor 15 varies, the slew rate does not vary unless the current IG current value of the current source 52 with SW function varies. Yes.

  The relationship between the off operation of the NMOS transistor 15 and the slew rate when the external output signal SC transitions from the L level to the H level will be described in detail with reference to FIG.

  As an initial state, the drive signal SB of the pre-drive circuit 1 is at the H level by the input signal SA, and the NMOS transistor 15 is in the on operation state. As a result, the external output signal SC is at L level.

  Next, the polarity of the input signal SA changes, the control signal Soff of the drive control circuit 50 changes, and the current source with SW function 52 pulls the current IG into the ground power supply GND so that the drive signal SB is set to the L level. To do. At this time, the signal Son of the drive control circuit 50 causes the output of the transistor on operation drive circuit 51 to be in an indefinite state, and the current IG of the current source 52 with SW function is between the gate and source of the NMOS transistor 15 and between the gate and drain. The charges charged in the respective capacitors are extracted, and the gate voltage of the NMOS transistor 15 (the voltage of the drive signal SB) starts to fall from the H level to the L level. The capacitance between the gate and source of the NMOS transistor 15 and the capacitance between the gate and drain are not shown in FIG.

  When the gate voltage of the NMOS transistor 15 falls to the threshold voltage Vth, the NMOS transistor 15 starts an off operation. At this time, the following two actions act on the gate of the NMOS transistor 15.

  (1) Due to the off operation of the NMOS transistor 15, the drain terminal voltage (voltage of the external output signal SC) of the transistor 15 tends to rise to the power supply voltage VDD through the load 56 whose one end is pulled up to the power supply voltage VDD. . As a result, since there is a capacitance Cgd between the gate and drain of the NMOS transistor 15, the gate voltage tends to rise to the H level through this capacitance Cgd.

  (2) As described above, the SW function-equipped current source 52 draws the current IG from the gate terminal of the NMOS transistor 15 and attempts to lower the gate voltage to the L level.

  The above two actions are balanced, and the gate voltage of the NMOS transistor 15 becomes substantially constant at the threshold voltage Vth. At this time, the NMOS transistor 15 is in the critical operation state of the on region and the off region in which the drain terminal voltage gradually changes from the L level to the H level although the on operation is performed.

  In this state, the current IG of the current source 52 with SW function flows through the capacitance between the gate and the drain of the NMOS transistor 15, and changes the voltage between the gate and the drain. The time differentiation of the gate-drain voltage Vgd at this time can be approximated by the following equation.

Time derivative of Vgd ≒ (Current value of current IG / Cgd) (2)
In the equation (2), the symbol IG is the current value of the current IG of the current source 52 with SW function, and Cgd is the gate-drain capacitance value of the NMOS transistor 15.

  As described above, in this state, the gate voltage of the NMOS transistor 15 is substantially constant at the threshold voltage Vth. Therefore, the time differentiation of the gate-drain voltage Vgd is a slew of the drain terminal voltage (voltage of the external output signal SC). Equivalent to rate. Therefore, the slew rate of the external output signal SC satisfies the above equation (1).

  The situation in which equation (1) holds is continued until the drain terminal voltage reaches the voltage VDD. When the drain terminal voltage reaches the voltage VDD, the drain terminal voltage does not change. Therefore, in order to establish the relationship of the expression (2), the gate voltage of the NMOS transistor 15 must be lowered. As a result, the NMOS transistor 15 Settles to the off operating state.

  As can be seen from the equation (1), the threshold voltage Vth is not directly related to the output slew rate. The reason why the slew rate varies due to the variation of the threshold voltage Vth is that the value of the current flowing through the gate varies with the threshold voltage Vth.

  In the present invention, the current IG of the current source 52 with SW function for lowering the gate voltage (SB signal voltage) of the NMOS transistor 15 is designed so that the current value does not change even in the range where the threshold voltage Vth varies.

  As a result, in the output circuit of the present invention, by appropriately setting the current value of the current IG, the slew rate during the off operation of the NMOS transistor 15 can be set to a desired value, and even if the threshold voltage Vth varies, the current Since the current value of IG is constant, an effect of suppressing the slew rate variation of the external output signal SC when the NMOS transistor 15 is turned off can be obtained.

  Further, according to the present invention, as shown in FIG. 3, the output circuit switches the current value of the current IG of the current source 52 with SW function by the current value switching signal in the output circuit configuration of FIG. When the external output signal SC of the output circuit reaches a certain voltage value, the value of the current value switching signal is changed to change the current IG of the variable current source with SW function. A circuit configuration in which an output voltage detection circuit 2 having a function of switching values is added may be used.

  The effect of this configuration will be described with reference to FIG. In this circuit configuration, the period of the symbol (a) shown in FIG. 4, that is, the drive signal SB of the pre-drive circuit 1 changes from the H level when the NMOS transistor 15 is in the on operation state to the L level. The current of the variable current source 52 with the SW function during the period until the gate voltage becomes substantially constant at the threshold voltage Vth and the output signal SC voltage (drain terminal voltage) reaches a predetermined voltage value from the L level (approximately 0 V). The current value of IG can be set to a large current value.

  When the setting is such that the threshold voltage Vth of the NMOS transistor 15 varies, the time interval from when the voltage of the drive signal SB starts to transition from the H level to the L level until the output signal SC voltage rises from the L level varies. Can be reduced.

  As shown in the equation (1), the current value of the current IG of the variable current source 52 with SW function determines the slew rate of the output signal SC. The output circuit having this configuration appropriately sets the current value of the current IG in the period (b) after the period (a) in FIG. 4 reaches the H level (VDD voltage) from a certain voltage value. The slew rate of the desired output voltage can be set.

  Therefore, in the output circuit of the present invention having this configuration, the current source with the SW function is used by appropriately setting the current value of the current IG to be different between the periods (a) and (b). Similarly to one output circuit of the present invention, when the NMOS transistor 15 is turned off, the current value of the current IG can be set even if the slew rate can be set to a desired output voltage slew rate and the threshold voltage Vth varies. Therefore, an effect of suppressing the slew rate variation of the external output signal when the NMOS transistor 15 is turned off can be obtained. In addition, as compared with another output circuit of the present invention using the current source 52 with SW function described above, variation in delay time from the input signal SA to the output signal SC is suppressed even if the threshold voltage Vth varies. Effect is also obtained.

It is a block diagram of the output circuit of the present invention. It is operation | movement explanatory drawing of the same output circuit. FIG. 2 is a block diagram of an output circuit obtained by further improving the output circuit of FIG. 1. It is operation | movement explanatory drawing of the same output circuit. It is a circuit diagram of the output circuit of the 1st Embodiment of this invention. It is a figure which shows the characteristic of the electric current of the current source with SW function with which the same output circuit is equipped. It is a circuit diagram of another composition of the output circuit. It is a circuit diagram of the output circuit of the 2nd Embodiment of this invention. FIG. 9 is a circuit diagram of another configuration of the output circuit of FIG. 8. It is a block diagram of the output circuit of the 3rd Embodiment of this invention. (A) is a block diagram of an output inversion delay circuit provided in the output circuit, and (b) is an operation explanatory diagram of the output inversion delay circuit. It is operation | movement explanatory drawing of the output circuit of the 3rd Embodiment of this invention. It is a block diagram of another composition of the output circuit. It is operation | movement explanatory drawing of the output circuit of FIG. It is a block diagram of the output circuit of the 4th Embodiment of this invention. It is operation | movement explanatory drawing of the same output circuit. It is a circuit diagram of the output circuit of the 5th Embodiment of this invention. It is a circuit diagram of the conventional output circuit. It is operation | movement explanatory drawing of the same output circuit. It is a circuit diagram of another conventional output circuit. It is operation | movement explanatory drawing of the same output circuit. It is a circuit diagram of the output circuit which does not penetrate between the transistors of an output buffer. It is operation | movement explanatory drawing of the output circuit of FIG.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In principle, the description of the same or similar parts will not be repeated unless particularly necessary.

(First embodiment)
The first embodiment of the present invention will be described with reference to FIG. The output circuit of FIG. 5 is an output circuit of a specific embodiment of the output circuit of the present invention shown in FIG. The output circuit configuration of the first embodiment shown in FIG. 5 will be described below with reference to FIG.

  The drive control circuit 50 in FIG. 1 includes an inverter 3 and an NMOS transistor 2. The input signal SA is input to the gate terminal of the NMOS transistor 2 via the inverter 3, and a Soff signal for controlling the current source 52 with SW (switch) function is output from the drain terminal of the transistor 2. Further, the input signal SA directly becomes a Son signal, and drives the gate of the PMOS transistor 10 of the transistor-on operation drive circuit 51.

  1, the transistor on operation drive circuit 51 uses the control signal voltage change adjustment circuit 59 and the PMOS transistor 10 of the conventional output circuit shown in FIG. 18 and the same configuration as the conventional output circuit of FIG. To. With this configuration, even if the threshold voltage Vth of the NMOS transistor 15 varies, it is possible to suppress variations in the slew rate of the external output signal SC with respect to the threshold voltage Vth when the NMOS transistor 15 is on.

  In FIG. 1, a current source 52 with SW function includes a current mirror circuit composed of an NMOS transistor 21 and an NMOS transistor 22 for outputting the current IG of the current source 52 with SW function, and a current source as a basis of the current IG. And I0.

  The gate terminal of the NMOS transistor 15 of the output buffer 8 is connected to the drain terminal of the PMOS transistor 62 of the transistor on operation drive circuit 51 and the drain terminal of the NMOS transistor 22 of the current source 52 with SW function. The drain terminal of the NMOS transistor 15 serves as an output terminal and outputs an external output signal SC. The other end of the load 56 connected to this output terminal is pulled up to the power supply VDD.

  The signal Soff of the drive control circuit 50 is connected to the drain terminal / gate terminal of the NMOS transistor 21 of the current source 52 with SW function. If the input signal SA is at L level, this node is lowered to L level. The current source 52 with SW function is turned off, and the current value of the current IG is made zero.

  With the above configuration, in the output circuit shown in FIG. 5, when the input signal SA is at the H level, the PMOS transistor 10 of the transistor on operation drive circuit 51 is turned off, and the SW function-equipped current source 52 is turned on. Therefore, the gate drive signal SB of the NMOS transistor 15 of the output buffer 8 becomes L level, and the external output signal SC becomes H level. On the contrary, if the input signal SA is at L level, the PMOS transistor 10 of the transistor on operation drive circuit 51 is turned on, and the current source 52 with SW function is turned off. Therefore, the drive signal SB becomes H level and the external output signal SC becomes L level.

  The current IG of the SW function-equipped current source 52 is within a variation range of the threshold voltage Vth of the NMOS transistor 15 (threshold voltages Vth1 to Vth2 in FIG. 6), as indicated by an IDS-VDS characteristic curve (IG) shown in FIG. In the range of (1), a constant constant current value is maintained. That is, it is necessary to avoid the characteristic curves (a) and (b) as shown in FIG.

  For this purpose, the channel length L of each of the NMOS transistors 21 and 22 is set to an appropriate size, the channel widths W ′ and W of the NMOS transistors 21 and 22 are set to appropriate values, and W '/ L and W / L are made sufficiently larger than the current source I0 and the output current IG.

  It is assumed that the current source I0 is made so as not to depend on the threshold voltage Vth of the NMOS transistor 15. Further, the mirror ratio between the current I0 and the current IG of the current mirror circuit constituted by the NMOS transistors 21 and 22 does not depend on the threshold voltage Vth of each transistor constituting the circuit by designing an appropriate mask. .

  As described above, when the channel length L and the channel widths W ′ and W are appropriately set, the current value of the current IG of the current source 52 with SW function is constant within the variation range of the threshold voltage Vth of the NMOS transistor 15. It becomes.

  Although not shown in FIG. 5, the slew rate of the external output signal SC is determined mainly by the capacitance value Cgd of the gate-drain capacitance of the NMOS transistor 15 and the current value of the current IG. That is, it can be approximated as the following equation (1).

Slew rate≈ (IG current value / Cgd) (1)
Since the gate-drain capacitance Cgd does not depend on the threshold voltage Vth, it can be considered that the slew rate of the external output signal SC during the off operation of the NMOS transistor 15 has almost no Vth dependency.

  From the above, according to the first embodiment, the slew rate variation of the external output signal SC relative to the variation of the threshold voltage Vth of the NMOS transistor 15 is not only when the NMOS transistor 15 is turned on, Even when operating, it can be suppressed.

  In FIG. 5, the output circuit according to the first embodiment of the present invention replaces the roles of the NMOS transistor 10 and the PMOS transistor 15 and switches the load connected to the external output terminal 54 as shown in FIG. The other end may be grounded to the ground power supply GND. Even in this case, the slew rate variation of the external output signal SC with respect to the variation of the threshold voltage Vth of the PMOS transistor 15 can be suppressed not only when the PMOS transistor 15 is turned on, but also when it is turned off.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. The output circuit of FIG. 8 is an output circuit of a specific embodiment of the output circuit of the present invention shown in FIG. The configuration of the output circuit of the second embodiment shown in FIG. 8 will be described below in correspondence with FIG.

  The drive control circuit 50 in FIG. 1 includes two inverters 3 and 4, an NMOS transistor 2, and a PMOS transistor 5. The input signal SA is input to the gate terminal of the NMOS transistor 2 via the inverter 3, and a signal Soff for controlling the current source 52 with SW function is output from the drain terminal of the transistor 2. The input signal SA is input to the gate terminal of the PMOS transistor 5 via the inverter 4, and the signal Son for controlling the transistor on operation driving circuit 51 is output from the drain terminal of the transistor 5.

  In FIG. 8, a transistor on operation drive circuit 51 includes a current mirror circuit composed of a PMOS transistor 31 and a PMOS transistor 32, and an input node of the current mirror circuit (the gate terminal and drain terminal of the PMOS transistor 31 and the PMOS transistor 32). A current source 30 connected to the gate terminal), a PMOS transistor 33 of a grounded gate type inserted in series between the drain terminal of the PMOS transistor 32 and the output terminal 14 of the pre-drive circuit 1, and the PMOS transistor 33 And a voltage source 34 connected to the gate terminal.

  The signal Son of the aforementioned drive control circuit is connected to the drain terminal and gate terminal of the PMOS transistor 31 of the transistor on operation drive circuit 51. If the input signal SA is at H level, this node is dropped to H level, The transistor on operation drive circuit 51 is turned off, and the current value of the drain current of the PMOS transistors 32 and 33, which is the output current of this circuit, is made zero.

  The output current of the transistor on operation drive circuit 51 is based on the drain current of the PMOS transistor 32. The current value of the output current becomes a substantially constant current value even if the voltage of the output terminal 14 of the pre-drive circuit 1 fluctuates due to the action of the PMOS transistor 33 of the grounded gate type.

  Therefore, as described above with respect to the external output signal slew rate, the transistor on operation drive circuit 51 has the slew rate of the external output signal SC when the NMOS transistor 15 is on even when the threshold voltage Vth of the NMOS transistor 15 varies. Variation with respect to the threshold voltage Vth can be suppressed.

  The configuration of the current source with SW function 52, the output buffer 8, and the load 56 in FIG. 8 is the same as that of the output circuit of the first embodiment shown in FIG. 5, and the operation and effect are also the same.

  From the above, according to the invention according to the second embodiment, the slew rate variation of the external output signal SC with respect to the variation of the threshold voltage Vth of the NMOS transistor 15 is not only when the NMOS transistor 15 is turned on, It can be suppressed even when the off operation is performed.

  The output circuit of the second embodiment of the present invention shown in FIG. 8 is connected to the external output terminal 54 by switching the roles of the NMOS transistor 10 and the PMOS transistor 15 as shown in FIG. The load 56 may be of a type in which the other end is grounded to the ground power supply GND. Even in this case, the slew rate variation of the external output signal SC with respect to the variation of the threshold voltage Vth of the PMOS transistor 15 can be suppressed not only when the PMOS transistor 15 is turned on, but also when it is turned off.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. In the output circuit of FIG. 10, the output buffer 8 includes an NMOS transistor 15 and a PMOS transistor 215. This output circuit can also draw and discharge the output current from the external output terminal 54.

  Further, this output circuit is basically the same as the output circuit for preventing the through state between the NMOS transistor 15 and the PMOS transistor 215 of the output buffer 8 described with reference to FIG. 22 in the above-mentioned “problem to be solved by the invention”. The same structure is effective in preventing the penetration state.

  The output inversion delay circuit 1 shown in FIG. 10 has the configuration of the logic circuit shown in FIG.

  In FIG. 11A, two delay circuits D1F and D1R are delay circuits having different delay times D1F and D1R, respectively. The selector 5 selects the signal R2 when the input signal SA is at the H level, and selects the signal F2 when the input signal SA is at the L level, and outputs it as the signal SB.

  As shown in the timing diagram of FIG. 11A, when the input signal SA transitions from the H level to the L level, the output signal SB outputs the inverted signal SA after the delay time D1F. When the input signal SA transitions from the L level to the H level, the output signal SB outputs the inverted signal SA after the delay time D1R.

  The output inversion delay circuit 2 in FIG. 10 has the same configuration as the output inversion delay circuit 1 described in FIG. 11 and operates in the same way, but the delay time when transitioning from the H level to the L level is D2F. The only difference is that the delay time at the transition from the level to the H level is D2R. Here, the four delay times D1F, D1R, D2F, and D2R are different from each other, but may be the same delay time according to the circuit design.

  In the circuit configuration shown in FIG. 10, the predrive circuit 6 that outputs the signal SBN that drives the gate of the NMOS transistor 15 of the output buffer 8 is the predrive circuit 1 of the first embodiment of FIG. 5 or the embodiment of FIG. 2 is the same as the pre-drive circuit 1 of FIG.

  The inverter circuit 5 in FIG. 10 is a driving inverter for driving the PMOS transistor 215 of the output buffer 8.

  The operation of the output circuit of FIG. 10 is as shown in the signal waveform diagram of FIG. This signal waveform diagram is the same timing diagram as the signal waveform diagram of FIG. 23 used for explanation of the operation in the sentence of the “problem to be solved by the invention”. The output circuit of FIG. 10 can prevent the through state between the NMOS transistor 15 and the PMOS transistor 215 by the delay times D2F and D1R as described in the text of “Problems to be Solved by the Invention”.

  The slew rate at the time of transition from the H level to the L level of the external output signal SC and the transition from the L level to the H level is determined by the on operation and the off operation of the NMOS transistor 15. The predrive circuit 6 that outputs the signal SBN that drives the gate of the NMOS transistor 15 is the same as the predrive circuit 1 of the first embodiment of FIG. 5 or the predrive circuit 1 of the second embodiment of FIG. Variation in the slew rate of the external output signal SC with respect to variation in the threshold voltage Vth of the transistor 15 is suppressed.

  From the above, according to the invention according to the third embodiment, the output circuit of the present invention allows the output current from the external output terminal while preventing the NMOS transistor 15 and the PMOS transistor 215 of the output buffer 8 from penetrating. Even if the threshold voltage Vth of the NMOS transistor 15 of the output buffer 8 that determines the slew rate of the output buffer 8 varies, the slew rate variation of the external output signal SC is suppressed. Has the effect of

  In the third embodiment of the present invention shown in FIG. 10, the other end of the load 56 connected to the external output terminal 54 is connected to the power supply VDD, but the other end of the load 56 is grounded to the ground power supply GND. In this case, the output circuit configuration shown in FIG. 13 is obtained.

  13, the difference in configuration from FIG. 10 is that, in the output circuit of FIG. 13, the gate terminal of the NMOS transistor 15 of the output buffer 8 is connected to the driving inverter 6 for driving the NMOS transistor 15, and the PMOS of the output buffer 8 The gate terminal of the transistor 215 is connected to the predrive circuit 5. The predrive circuit 5 is the same as the predrive circuit 1 of the first embodiment shown in FIG. 7 or the predrive circuit 1 of the second embodiment shown in FIG.

  The operation of the output circuit of FIG. 13 is as shown in the signal waveform diagram of FIG. By the delay times D2F and D1R, the through state between the NMOS transistor 15 and the PMOS transistor 215 can be prevented.

  The slew rate at the time of transition of the external output signal SC from the H level to the L level and at the transition from the L level to the H level is determined by the on operation and the off operation of the PMOS transistor 215. The predrive circuit 5 that outputs the signal SBP for driving the gate of the PMOS transistor 215 is the same as the predrive circuit 1 of the first embodiment of FIG. 7 or the predrive circuit 1 of the second embodiment of FIG. Variation in the slew rate of the external output signal SC with respect to variation in the threshold voltage Vth of the transistor 215 is suppressed.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. The output circuit of FIG. 15 has two input terminals 7 and 307 and two external output terminals 54 and 354. This output circuit is made up of two output circuits having the same configuration, and in FIG. 15, a left output circuit having an input terminal 7 and an output terminal 54, and a right output circuit having an input terminal 307 and an output terminal 354, Have the same circuit configuration and the same operation. Therefore, only the left output circuit will be described.

  The output circuit on the left side of FIG. 15 has substantially the same configuration as the output circuit of the third embodiment of the present invention illustrated in FIG. 10, and the difference in configuration is that the gate terminal of the PMOS transistor 215 of the output buffer 8 is Instead of the driving inverter for the PMOS transistor 215, the output terminal of the pre-drive circuit 1 of the first or second embodiment shown in FIG. 7 or FIG. 9 is connected. A load 56 is connected between the two external output terminals 54 and 354.

  The operation of this output circuit will be described with reference to FIG. This output circuit is configured so that each of the output signal SC of the output terminal 54 and the output signal SC3 of the output terminal 354 is equal to the time difference DT between the pulse signals of the input signal SA of the input terminal 7 and the input signal SA3 of the input terminal 307. Outputs the pulse output signal with a time difference. Therefore, this output circuit can apply power proportional to the time difference DT of the two input signals to the load 56 connected between the output terminals 54 and 354. The operation will be described below.

  First, after the input signal SA transitions from the L level to the H level, after the delay time D1R, the output signal SC transitions from the L level to the H level as in the state of the symbol (H) in FIG. In this state of the sign (H), the output signal SC3 of the output terminal 354 is at the L level, so that the output signal SC transits from the L level to the H level by the on operation of the PMOS transistor 215 of the output circuit on the left side of FIG. .

  Next, after the input signal SA transits from the L level to the H level, the input signal SA3 transits from the L level to the H level after time DT. After that, after the delay time D2R, the output signal SC3 transitions from the L level to the H level as in the state of the reference (F) in FIG. In this state (F), since the output signal SC of the output terminal 54 is at the H level, the output signal SC3 changes from the L level to the H level by the off operation of the NMOS transistor 315 of the output circuit on the right side of FIG.

  If the two delay times D1R and D2R are set to be equal, the time difference between the transition (H) of the output signal SC and the transition (F) of the output signal SC3 is DT.

  Third, after the input signal SA3 transits from the H level to the L level, the output signal SC3 transits from the H level to the L level after the delay time D2F, as in the state of the symbol (E) in FIG. In this state (E), since the output signal SC of the output terminal 54 is at the H level, the output signal SC3 changes from the H level to the L level by the on operation of the NMOS transistor 315 of the output circuit on the right side of FIG.

  Fourth, after the input signal SA3 transits from the H level to the L level, the input signal SA transits from the H level to the L level after time DT. After that, after the delay time D1F, the output signal SC transitions from the H level to the L level as in the state of the symbol (G) in FIG. In this state (G), since the output signal SC3 of the output terminal 354 is at the L level, the output signal SC3 transits from the H level to the L level by the off operation of the PMOS transistor 215 of the left output circuit in FIG.

  If the two delay times D1F and D2F are set to be equal, the time difference between the transition (G) of the output signal SC and the transition (E) of the output signal SC3 is DT.

  As can be seen from the above operation description, as shown in FIG. 16, when two input signals SA and SA3 are given, the transition operation of the output signals SC and SC3 at the two output terminals of this output circuit is as follows. , Depending on the on operation and off operation of each of the PMOS transistor 215 and the NMOS transistor 315. The PMOS transistor 215 is driven by the predrive circuit 5 in FIG. 15, and the NMOS transistor 315 is driven by the predrive circuit 306 in FIG. Each of the predrive circuits 5 and 306 is the predrive circuit 1 of the first or second embodiment shown in FIGS. 7 and 9 and FIGS. 5 and 8. Therefore, in this output circuit, each of the output signals SC of (H), (F), (E), and (G) shown in FIG. 16 with respect to variations in the threshold voltage Vth of the NMOS transistor 315 and the PMOS transistor 215. , Variation in the slew rate of the transition state of SC3 is suppressed.

  From the above, according to the invention according to the fourth embodiment, the output circuit of the present invention has each of the two output terminals 54 and 354 corresponding to the time difference DT between the pulse signals of the two input signals SA and SA3. An output for applying power proportional to the time difference DT of the two input signals to the load 56 connected between the output terminals 54 and 354 by giving a time difference between the pulse output signals of the output signals SC and SC3. Even if the threshold voltages Vth of the NMOS transistors 15 and 315 and the PMOS transistors 215 and 415 of the output circuit vary, the variation of the slew rate at the time of the state transition of each output signal is suppressed, and as a result, the load 56 The power variation proportional to the applied time difference DT is suppressed.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIG.

  The output circuit of FIG. 17 is different from the output circuit of the second embodiment illustrated in FIG. 8 in that a differential circuit including PMOS transistors 61 and 62, a current source 60 that determines a tail current of the differential circuit, A voltage source 63 connected to the gate of the PMOS transistor 62 serving as one input terminal of the differential circuit, an NMOS transistor 64 having a gate terminal and a drain terminal connected to the drain terminal of the PMOS transistor 62, and the PMOS transistor 62 This is a circuit in which an NMOS transistor 65 having a gate terminal connected to the drain terminal is added.

  The NMOS transistors 64 and 65 constitute a current mirror circuit. This current mirror circuit is a part of the variable current source 52 with SW function, and the mirror current of the output current ISUB of the differential circuit composed of the two PMOS transistors 61 and 62 is also used as the variable current source 52 with SW function. Is added to the current of the current source 20 of the current mirror circuit composed of the two NMOS transistors 21 and 22 which are a part of the current.

  An output voltage is detected by a differential circuit composed of the two PMOS transistors 61 and 62, a current source 60 for determining a tail current of the differential circuit, and a voltage source 63 connected to the gate of the PMOS transistor 62. The circuit 2 is configured. The gate terminal of the PMOS transistor 61 that is the input at the other end of the differential circuit is connected to the drain terminal of the NMOS transistor 15 of the output buffer 8. This differential circuit detects the voltage value of the external output signal SC and compares it with the voltage value of the voltage source 63. If the voltage value of the external output signal SC is higher than this voltage value, the output current ISUB is used as a current switching signal. It outputs to the variable current source 52 with SW function.

  The variable current source 52 with SW function outputs a current IG determined by the current of the current source 20 if the current ISUB of the current switching signal is zero, and subtracts the current ISUB from the current of the current source 20 if there is a current ISUB. The current IG determined by the current is output.

  With this circuit configuration, the current IG of the variable current source with SW function 52 during the period until the voltage (drain terminal voltage) of the external output signal SC reaches the voltage value of the voltage source 63 from the L level (approximately 0 V). The value can be set to a large current value. The period is the period (a) of FIG. 4 used in the description of the “effect of the invention”.

  As described in the above “Effects of the Invention”, in the output circuit having this configuration, the output voltage after the period (a) in FIG. 4 reaches the H level (power supply voltage VDD) from the voltage value of the voltage source 63. In the period (b), the current value of the current IG can be appropriately set to set the desired output voltage slew rate.

  Therefore, in the output circuit having this configuration, the current source 52 with the SW function described above is used by appropriately setting the current value of the current IG to be different between the periods (a) and (b) of FIG. Similar to the output circuit of the present invention, when the NMOS transistor 15 is turned off, the slew rate can be set to a desired output voltage slew rate, and even if the threshold voltage Vth varies, the current value of the current IG Therefore, an effect of suppressing the slew rate variation of the external output signal when the NMOS transistor 15 is turned off can be obtained. In addition, as compared with another output circuit of the present invention using the current source 52 with SW function described above, even if the threshold voltage Vth varies, the effect of suppressing variation in delay time from the input signal SA to the output signal SC Can also be obtained.

  As described above, according to the present invention, in an output circuit mounted on a semiconductor integrated circuit device, it is necessary to suppress variations in the slew rate of an external output signal even if the threshold voltage Vth of the MOS transistor of the output buffer varies. It is useful as an output circuit.

DESCRIPTION OF SYMBOLS 1 Predrive circuit 2 Output voltage detection circuit 8 Output buffer 15 NMOS transistor 50 Drive control circuit 51 Transistor on operation drive circuit 52 Current source with SW function 54 External terminal 56 Load 59 Control signal voltage change adjustment circuit

Claims (4)

A pre-drive circuit that inputs an input signal and outputs a drive signal;
An output circuit composed of a grounded source / open drain type transistor that inputs a drive signal from the pre-drive circuit to a gate terminal and outputs an external output signal from a drain terminal,
The pre-drive circuit is
A transistor on operation drive circuit for outputting the drive signal for turning on the source-grounded / open drain type transistor; and
A current source with SW function that outputs the drive signal for turning off the source-grounded / open-drain transistor;
In response to the input signal, the transistor on operation drive circuit and a drive control circuit that outputs a control signal for controlling each of the current sources with SW function,
The SW function current source has one end connected to the gate terminal of the source ground / open drain type transistor and the other end connected to the ground. The current of the SW function current source is connected to the source ground / open drain. An output circuit characterized in that even if the gate voltage of a type transistor varies within the range of variations in threshold voltage, the charge at the gate terminal is extracted with a constant current value. The output circuit according to claim 1, wherein
The current source with SW function is replaced with a variable current source with SW function capable of switching the current value of the current of the current source by a current value switching signal,
An output voltage detection circuit for outputting a current value switching signal for switching the current value of the variable current source with SW function by changing the value of the current value switching signal when the external output signal of the output circuit reaches a predetermined voltage value. An output circuit further comprising: The output circuit according to claim 1, wherein
An output circuit characterized in that a common source / open drain type transistor is composed of an NMOS transistor. The output circuit according to claim 1, wherein
An output circuit characterized in that a common source / open drain type transistor is composed of a PMOS transistor.

Images