JP2010245291A - Method of manufacturing electronic device - Google Patents

Method of manufacturing electronic device Download PDF

Info

Publication number
JP2010245291A
JP2010245291A JP2009092325A JP2009092325A JP2010245291A JP 2010245291 A JP2010245291 A JP 2010245291A JP 2009092325 A JP2009092325 A JP 2009092325A JP 2009092325 A JP2009092325 A JP 2009092325A JP 2010245291 A JP2010245291 A JP 2010245291A
Authority
JP
Japan
Prior art keywords
slope
droplet
bulk
droplets
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009092325A
Other languages
Japanese (ja)
Inventor
Noboru Uehara
昇 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2009092325A priority Critical patent/JP2010245291A/en
Publication of JP2010245291A publication Critical patent/JP2010245291A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic device for improving reliability of wiring laminated on a slope, wherein a step part is formed of an electronic component arranged on a mounting surface of a mounting substrate and the mounting surface, an insulating slope is formed on the step part, and the electronic device is formed by laminating a wiring for connecting the mounting substrate and electronic component on the slope. <P>SOLUTION: A bulk 25 of the slope 17 is formed of slope elements 26 which are formed by curing droplets D1 at every discharge. In addition, droplets D2 formed of insulating ink with lower viscosity than the droplets D1 are discharged on a surface of the bulk 25. The droplets D2 with lower viscosity are easily wetted and spread after landing, and flow between projections on the surface of the bulk 25. The slope 17 is formed of a cured object 35, which is formed by curing the droplets D2 in the above state, and the bulk 25. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、実装基板の実装面に配置される電子部品と実装面とによって形成される段差部に絶縁性のスロープが形成されて、実装基板と電子部品とを接続する配線が当該スロープに積層されてなる電子装置の製造方法に関する。   In the present invention, an insulating slope is formed in a step portion formed by an electronic component disposed on the mounting surface of the mounting substrate and the mounting surface, and wiring for connecting the mounting substrate and the electronic component is laminated on the slope. The present invention relates to a method for manufacturing an electronic device.

実装基板の電極パッドとこれに実装される半導体チップなどの電極パッドとを接続する配線の形成方法には、近年、導電性インクからなる液滴を乾燥して焼成することにより配線を形成するといったインクジェット法が提案されている。インクジェット法は、配線の形状を液滴の単位で変更できるために、従来のワイヤボンディング法に比べて、配線構造の自由度を大幅に拡張させることができる。そのうえ、ワイヤボンディング法のような空中配線を必要としないために、配線の占有空間を小さくすることもでき、その結果、電子部品の実装スペースそのものを縮小することもできる。   In recent years, a method of forming a wiring for connecting an electrode pad of a mounting substrate and an electrode pad such as a semiconductor chip mounted on the mounting substrate is to form a wiring by drying and firing droplets made of conductive ink. An ink jet method has been proposed. Since the ink jet method can change the shape of the wiring in units of droplets, the degree of freedom of the wiring structure can be greatly expanded compared to the conventional wire bonding method. In addition, since the aerial wiring as in the wire bonding method is not required, the occupied space of the wiring can be reduced, and as a result, the mounting space of the electronic component itself can be reduced.

ところで、上述のようにして電子部品を実装する場合には、実装基板の実装面と電子部品との間に電子部品の厚みに相当する段差が形成されることになる。インクジェット法を利用する場合であれば、このような段差に沿っても配線を形成することはできる。ただし、こうした段差に沿って形成される配線は、屈曲する箇所が段差の分だけ多くなってしまい、配線そのものの機械的さらには電気的な信頼性を損なう虞がある。そのため、配線の接続対象である電極パッド間に段差があるような場合、上述したインクジェット法では、通常、配線へのこうした機械的なストレスを抑えるべく、段差を緩和するための技術が採用されている。   By the way, when the electronic component is mounted as described above, a step corresponding to the thickness of the electronic component is formed between the mounting surface of the mounting substrate and the electronic component. If the inkjet method is used, the wiring can be formed along such a step. However, the wiring formed along such a step has a number of bent portions that are increased by the amount of the step, which may impair the mechanical and electrical reliability of the wiring itself. Therefore, when there is a step between the electrode pads to which the wiring is to be connected, the above-described inkjet method usually employs a technique for reducing the step to suppress such mechanical stress on the wiring. Yes.

このような段差を緩和するための技術には、例えば特許文献１に記載されるように、電子部品のパッド形成面と実装面とを繋ぐように吐出された絶縁性の樹脂材料からなる絶縁性スロープが利用されている。そして上記段差を緩和するかたちに構成された絶縁性スロープ上に導電性インクからなる液滴が吐出されて、この導電性インクが乾燥及び焼成されることにより上記配線が形成される。これにより配線としての屈曲が緩和され、機械的かつ電気的な信頼性も高く維持されるようになる。   As a technique for reducing such a step, for example, as described in Patent Document 1, an insulating property made of an insulating resin material discharged so as to connect a pad forming surface and a mounting surface of an electronic component is used. A slope is used. Then, droplets made of conductive ink are ejected onto an insulating slope configured to relieve the step, and the conductive ink is dried and baked to form the wiring. As a result, the bending as the wiring is eased, and the mechanical and electrical reliability is maintained high.

特開２００６−１４７６５０号公報JP 2006-147650 A

ところで、実装スペースのさらなる縮小化や実装基板の微細化が進行する近年では、上述した絶縁性スロープの位置や形状などにも高い精度が必要とされている。そしてこうした要請に応える絶縁性スロープの製造方法としても上記インクジェット法が検討されている。インクジェット法を用いた絶縁性スロープの製造方法としては、吐出毎に硬化させられる液滴がスロープ状に積み重ねられる態様にて、こうした吐出と硬化とが繰り返される方法が提案されている。しかしながら、こうした製造方法にあっては、絶縁性スロープの形状や位置が高い精度の下で再現されるものの、液滴の吐出と硬化とが液滴毎に繰り返されるために、絶縁性スロープの表面には、各々が球面形状をなす複数の凸部が形成されてしまう。こうした絶縁性スロープ上に導電性インクからなる液滴が吐出されると、着弾した液滴が凸部の間に流れ込み、その結果、配線幅の拡大や膜厚のばらつきなどが生じてしまう。そして、こうした配線幅の拡大や膜厚のばらつきは、隣接する配線との短絡や配線
の機械的強度の不足など、配線の信頼性を低下させばかりか、電子装置自体の信頼性をも低下させてしまう。 By the way, in recent years when the mounting space is further reduced and the mounting substrate is miniaturized, high accuracy is required for the position and shape of the insulating slope described above. The ink jet method has been studied as a method for producing an insulating slope that meets these requirements. As an insulating slope manufacturing method using an ink jet method, a method in which such discharge and curing are repeated in a mode in which droplets that are cured at each discharge are stacked in a slope shape has been proposed. However, in such a manufacturing method, although the shape and position of the insulating slope are reproduced with high accuracy, since the discharge and curing of the droplet are repeated for each droplet, the surface of the insulating slope is A plurality of convex portions each having a spherical shape are formed. When a droplet made of conductive ink is ejected onto such an insulating slope, the landed droplet flows between the convex portions, resulting in an increase in the wiring width and variation in film thickness. Such widening of the wiring width and variations in film thickness not only reduce the reliability of the wiring, such as a short circuit with the adjacent wiring or the insufficient mechanical strength of the wiring, but also reduce the reliability of the electronic device itself. End up.

本発明は、上記課題を解決するためになされたものであり、その目的は、実装基板の実装面に配置される電子部品と実装面とによって形成される段差部に絶縁性のスロープが形成されて、実装基板と電子部品とを接続する配線が当該スロープに積層されてなる電子装置の製造方法において、当該スロープに積層される配線の信頼性を向上させる電子装置の製造方法を提供することにある。   The present invention has been made to solve the above-described problems, and an object of the present invention is to form an insulating slope at a step portion formed by an electronic component disposed on a mounting surface of a mounting board and the mounting surface. And providing a method of manufacturing an electronic device that improves the reliability of the wiring stacked on the slope in the method of manufacturing an electronic device in which wiring connecting the mounting substrate and the electronic component is stacked on the slope. is there.

本発明の電子装置の製造方法は、実装基板の実装面と該実装面に配置された電子部品との段差を緩和する絶縁性のスロープが前記電子部品の外周に形成されて、前記実装基板と前記電子部品とを接続する配線が前記スロープに積層されてなる電子装置の製造方法において、前記スロープが形成される領域に、吐出毎に硬化された液滴からなる層が重なるかたちに、第１の絶縁性インクからなる第１の液滴の吐出と硬化とを繰り返し、前記第１の液滴からなる凸部が表面に形成されるかたちに前記スロープのバルクを形成する工程と、前記バルクの表面に、前記バルクの表面に着弾した液滴が前記凸部の間を埋めるように、前記第１の絶縁性インクよりも粘度が低い第２の絶縁性インクからなる第２の液滴をさらに吐出し、同第２の液滴を硬化させることにより、前記スロープの表面を形成する工程とを備えた。   In the method for manufacturing an electronic device according to the present invention, an insulating slope that relaxes a step between a mounting surface of a mounting substrate and an electronic component disposed on the mounting surface is formed on an outer periphery of the electronic component, In the method of manufacturing an electronic device in which wiring for connecting to the electronic component is laminated on the slope, a first layer is formed in a form in which a layer made of liquid droplets cured at each discharge overlaps a region where the slope is formed. Repeating the discharge and curing of the first droplet made of the insulating ink to form the bulk of the slope in a manner that the convex portion made of the first droplet is formed on the surface; A second droplet made of a second insulating ink having a viscosity lower than that of the first insulating ink is further provided on the surface so that the droplet landed on the surface of the bulk fills the space between the convex portions. Discharge and cure the second droplet By, and a step of forming a surface of the slope.

この電子装置の製造方法によれば、バルクを形成するための第１の絶縁性インクよりも粘度が低い第２の絶縁性インクからなる第２の液滴が、表面に凸部を有するバルクに対して、そのバルクの表面の凸部間を埋めるかたちに吐出され、この第２の絶縁性インクが硬化されることにより、スロープの表面が形成される。このため、スロープの表面が第２の液滴により滑らかとなり、こうしたスロープの表面に積層される配線は、その配線幅及びその膜厚の均一化が図られることとなり、隣接した配線との短絡や配線の機械的強度の不足などの問題を低減することが可能になる。それゆえ配線の信頼性、ひいては電子装置の信頼性をも向上させることが可能となる。   According to this method for manufacturing an electronic device, the second liquid droplet made of the second insulating ink having a viscosity lower than that of the first insulating ink for forming the bulk is formed in the bulk having a convex portion on the surface. On the other hand, the surface of the slope is formed by discharging between the convex portions on the bulk surface and curing the second insulating ink. For this reason, the surface of the slope is smoothed by the second droplet, and the wiring laminated on the surface of such a slope is made uniform in its wiring width and film thickness. Problems such as insufficient mechanical strength of the wiring can be reduced. Therefore, it is possible to improve the reliability of the wiring and thus the reliability of the electronic device.

この電子装置の製造方法は、前記凸部に前記第２の液滴を積み重ねることが好ましい。
硬化された第１の液滴からなる凸部の表面は、第１の絶縁性インクの表面張力により例えば球面形状をなし、その周辺を構成する他の第１の液滴に向けて、少なからず等方的なかたちをなす。この電子装置の製造方法によれば、こうした凸部に第２の液滴が積み重ねられることから、粘度が低く流動性が高い第２の液滴は、それが重なる第１の液滴の周囲に向けて、少なからず等方的に流動することになる。この結果、第１の液滴からなる凸部間が、第２の液滴によって、より効果的に埋められることになる。 In the method for manufacturing the electronic device, it is preferable that the second droplets are stacked on the convex portion.
The surface of the convex portion formed of the cured first droplet has, for example, a spherical shape due to the surface tension of the first insulating ink, and is directed toward the other first droplets constituting the periphery. Isotropic shape. According to this method for manufacturing an electronic device, since the second droplets are stacked on these convex portions, the second droplets having low viscosity and high fluidity are placed around the first droplets on which they overlap. Toward, it will flow more or less isotropically. As a result, the space between the convex portions made of the first droplet is more effectively filled with the second droplet.

この電子装置の製造方法は、前記第１の液滴と同じ容量からなる前記第２の液滴を、一部の前記凸部に積み重ねて前記スロープの表面を形成してもよい。
ここで、バルク表面の全ての凸部に対して第１の液滴と同じ容量の第２の液滴を吐出した場合、第２の液滴の容量が過剰となり、その過剰な分の第２の液滴が、実装面に流れ出す虞がある。この点、この電子装置の製造方法によれば、第１の液滴と同じ容量の第２の液滴が一部の凸部に積み重ねられることから、液滴の容量を変更せずとも、上述した液滴の流れ出しが抑制されることになる。こうすることにより、スロープを所望形状に確実に形成することが可能になる。 In this electronic device manufacturing method, the surface of the slope may be formed by stacking the second droplets having the same capacity as the first droplets on a part of the convex portions.
Here, when the second droplet having the same capacity as the first droplet is discharged to all the convex portions on the bulk surface, the second droplet has an excessive capacity, and the excess second amount May flow out to the mounting surface. In this regard, according to the method for manufacturing the electronic device, the second droplet having the same capacity as the first droplet is stacked on a part of the convex portions, so that the above-described operation can be performed without changing the droplet capacity. Thus, the flowing out of the droplets is suppressed. This makes it possible to reliably form the slope into a desired shape.

この電子装置の製造方法は、前記第１の液滴よりも小さい容量からなる前記第２の液滴を、全ての前記凸部に積み重ねて前記スロープの表面を形成してもよい。
この電子装置の製造方法によれば、全ての凸部に対して、第１の液滴の容量よりも小さ
い容量からなる第２の液滴が全ての凸部に対して積み重ねられることから、第１の液滴と第２の液滴との吐出位置を変更せずとも、上述した液滴の流れ出しが抑制されることになる。こうすることにより、スロープを所望形状に確実に形成することが可能になる。 In this method of manufacturing an electronic device, the surface of the slope may be formed by stacking the second droplets having a smaller capacity than the first droplets on all the convex portions.
According to this method for manufacturing an electronic device, since the second droplets having a volume smaller than the volume of the first droplet are stacked on all the convex portions, all the convex portions are stacked. Even if the ejection positions of the first droplet and the second droplet are not changed, the above-described droplet flow-out is suppressed. This makes it possible to reliably form the slope into a desired shape.

この電子装置の製造方法は、前記絶縁性インクとして光硬化性樹脂を用いることが好ましい。
絶縁性インクに熱硬化性樹脂が用いられる場合、第１の液滴の吐出と硬化とを繰り返してバルクを形成する上では、例えば実装基板を加熱し続けながら第１の液滴を吐出することが必要である。こうした場合には、着弾した第２の液滴が凸部の間を埋める前に、その余熱によって硬化してしまう虞があるため、バルクを形成する工程とスロープの表面を形成する工程との間にバルクなどを冷却する期間が必要となる。この点、この電子装置の製造方法によれば、上述したようなバルクの冷却期間が必要ないばかりか、バルクを形成する工程とスロープの表面を形成する工程とを連続して実行することが可能であることから、電子装置の生産効率を向上させることも可能である。 In this electronic device manufacturing method, it is preferable to use a photocurable resin as the insulating ink.
When a thermosetting resin is used for the insulating ink, the first droplet is discharged while continuing to heat the mounting substrate, for example, when the bulk is formed by repeating the discharge and curing of the first droplet. is required. In such a case, since the landed second droplet may be cured by the remaining heat before filling the space between the convex portions, it is between the step of forming the bulk and the step of forming the surface of the slope. A period for cooling the bulk is required. In this respect, according to the method for manufacturing an electronic device, the bulk cooling period as described above is not necessary, and the bulk forming step and the slope surface forming step can be continuously performed. Therefore, it is possible to improve the production efficiency of the electronic device.

（ａ）電子装置を示す平面図、（ｂ）１ｂ−１ｂ線に沿った断面図。(A) The top view which shows an electronic device, (b) Sectional drawing along line 1b-1b. （ａ）（ｂ）絶縁性スロープのパターン格子を模式的に示す図。(A) (b) The figure which shows typically the pattern grid | lattice of an insulating slope. （ａ）（ｂ）電子装置の製造方法、特に電子部品の実装方法を示すフローチャート。(A) (b) The flowchart which shows the manufacturing method of an electronic device, especially the mounting method of an electronic component. （ａ）〜（ｄ）絶縁性スロープの形成過程を示す図。The figure which shows the formation process of (a)-(d) insulating slope. 吐出工程における液滴の吐出位置をパターン格子に模式的に示す図。The figure which shows typically the discharge position of the droplet in a discharge process on a pattern grid | lattice. （ａ）（ｂ）着弾後の低粘度液滴の様子を模式的に示す図。(A) (b) The figure which shows typically the mode of the low-viscosity droplet after landing.

以下、本発明の電子装置の製造方法を具体化した一実施形態について図１〜図６を参照して説明する。図１（ａ）は本実施形態の電子装置１０の平面構造を示す平面図であり、図１（ｂ）は図１（ａ）に示す１ｂ−１ｂ線に沿うような断面構造を示す部分断面図である。   Hereinafter, an embodiment of a method for manufacturing an electronic device according to the present invention will be described with reference to FIGS. FIG. 1A is a plan view showing a planar structure of the electronic device 10 of the present embodiment, and FIG. 1B is a partial sectional view showing a sectional structure taken along line 1b-1b shown in FIG. FIG.

図１（ａ），（ｂ）に示されるように、電子装置１０が具備する矩形板状の実装基板１１にはその最上層に絶縁層が設けられており、この絶縁層の上面である実装面１１ａには矩形状の第１電極パッド１３が同実装面１１ａの四辺に沿って配列されている。実装基板１１の最上層である絶縁層の構成材料としては、可撓性あるいは非可撓性の各種絶縁材料を用いることができる。可撓性を有する具体的な材料としては、ポリイミド系樹脂、エポキシ系樹脂、ポリエステル系樹脂、フェノール系樹脂、フッ素系樹脂などの合成樹脂を用いることが可能である。また非不可撓性を有する具体的な材料としては、低温焼結基材であるガラスセラミックの他、高温焼結基材や誘電体材料などを用いることが可能である。   As shown in FIGS. 1A and 1B, a rectangular plate-shaped mounting substrate 11 provided in the electronic device 10 is provided with an insulating layer as the uppermost layer, and the mounting is the upper surface of the insulating layer. On the surface 11a, rectangular first electrode pads 13 are arranged along the four sides of the mounting surface 11a. As a constituent material of the insulating layer that is the uppermost layer of the mounting substrate 11, various insulating materials that are flexible or inflexible can be used. As a specific material having flexibility, a synthetic resin such as a polyimide resin, an epoxy resin, a polyester resin, a phenol resin, or a fluorine resin can be used. Further, as a specific material having non-flexibility, it is possible to use a high-temperature sintered base material, a dielectric material, or the like, in addition to a glass ceramic that is a low-temperature sintered base material.

なお、上述する実装基板１１は、上記第１電極パッド１３の他、実装基板１１の実装面１１ａに各種配線を有する構成であってもよい。さらに、上述する実装基板１１は、各種配線がプリントされた複数の回路基板を下層に有する多層基板であってもよく、上記実装面１１ａに第１電極パッド１３が形成されているものであればよい。さらにまた、実装基板１１の第１電極パッド１３は、実装面１１ａの四辺に沿って配列されているが、例えば実装面１１ａの１辺にだけ形成される構成でもよい。   Note that the mounting substrate 11 described above may have various wirings on the mounting surface 11 a of the mounting substrate 11 in addition to the first electrode pad 13. Further, the mounting board 11 described above may be a multilayer board having a plurality of circuit boards on which various wirings are printed as a lower layer, as long as the first electrode pad 13 is formed on the mounting surface 11a. Good. Furthermore, the first electrode pads 13 of the mounting substrate 11 are arranged along the four sides of the mounting surface 11a, but may be formed only on one side of the mounting surface 11a, for example.

実装面１１ａには、上記複数の第１電極パッド１３に取り囲まれるように、電子部品としての矩形板状の半導体チップ１２が図示しない接着層を介して接合されている。半導体チップ１２の上面であるパッド形成面１２ａには、矩形状をなす複数の第２電極パッド１５が、実装基板１１の各第１電極パッド１３に対応するかたちで、半導体チップ１２の四
辺に沿って配列されている。さらにパッド形成面１２ａには、第２電極パッド１５を囲うかたちで絶縁層が形成されている。第２電極パッド１５を囲う絶縁層は、無機絶縁材料や有機絶縁材料からなる薄膜であって、無機絶縁材料としては、ＳｉＯ２やＳｉＮなどを用いることが可能であり、有機絶縁材料としては、ポリイミド樹脂などを用いることが可能である。 A rectangular plate-like semiconductor chip 12 as an electronic component is bonded to the mounting surface 11a via an adhesive layer (not shown) so as to be surrounded by the plurality of first electrode pads 13. On the pad forming surface 12 a that is the upper surface of the semiconductor chip 12, a plurality of rectangular second electrode pads 15 correspond to the first electrode pads 13 of the mounting substrate 11, along the four sides of the semiconductor chip 12. Are arranged. Further, an insulating layer is formed on the pad forming surface 12 a so as to surround the second electrode pad 15. The insulating layer surrounding the second electrode pad 15 is a thin film made of an inorganic insulating material or an organic insulating material. As the inorganic insulating material, SiO 2 or SiN can be used. As the organic insulating material, A polyimide resin or the like can be used.

なお、上述する電子部品は、半導体チップ１２等の能動部品に限らず、抵抗器やコンデンサなどに代表されるような受動部品であってもよく、パッド形成面１２ａに第２電極パッド１５が形成されて、そのパッド形成面１２ａの反対側面を実装面１１ａに向けた実装、所謂フェイスアップ方式の実装が可能なものであればよい。さらに、半導体チップ１２の第２電極パッド１５は、パッド形成面１２ａの四辺に沿って配列されているが、実装基板１１の第１電極パッド１３と同様に、例えばパッド形成面１２ａの１辺にだけ第２電極パッド１５が形成される構成や第２電極パッド１５が１つだけ形成される構成であってもよい。   The electronic component described above is not limited to an active component such as the semiconductor chip 12, but may be a passive component such as a resistor or a capacitor. The second electrode pad 15 is formed on the pad forming surface 12a. In addition, it is only necessary that the side surface opposite to the pad forming surface 12a can be mounted on the mounting surface 11a, that is, so-called face-up mounting. Furthermore, the second electrode pads 15 of the semiconductor chip 12 are arranged along the four sides of the pad forming surface 12a. However, like the first electrode pads 13 of the mounting substrate 11, for example, on the one side of the pad forming surface 12a. Only the second electrode pad 15 may be formed, or only one second electrode pad 15 may be formed.

上述する実装面１１ａとパッド形成面１２ａとの間には、半導体チップ１２の厚さに相当する段差が存在する。半導体チップ１２の外周には、実装面１１ａとパッド形成面１２ａとをつなぐ連続面を有した絶縁性スロープ１７（以下、単にスロープという。）が設けられている。スロープ１７は半導体チップ１２から離間するにつれてその膜厚が薄くなるかたちに構成されており、またスロープ１７の表面である上記連続面は実装面１１ａとパッド形成面１２ａとの間の段差を緩和するかたちに構成されている。   A step corresponding to the thickness of the semiconductor chip 12 exists between the mounting surface 11a and the pad forming surface 12a. An insulating slope 17 (hereinafter simply referred to as a slope) having a continuous surface connecting the mounting surface 11a and the pad forming surface 12a is provided on the outer periphery of the semiconductor chip 12. The slope 17 is configured in such a manner that the film thickness decreases as the distance from the semiconductor chip 12 increases, and the continuous surface that is the surface of the slope 17 relaxes the step between the mounting surface 11a and the pad forming surface 12a. It is configured in a form.

このスロープ１７は、絶縁材料からなる構造単位（スロープ要素）が積み重なる態様で構成されている。詳述すると、図２（ａ），（ｂ）に示されるように、上記スロープ１７が設けられる空間には、実装面１１ａを構成する２つの独立な方向（行方向と列方向）及び半導体チップ１２の厚み方向（層方向）への所定距離の平行移動により不変な空間格子である３次元のパターン格子２０が規定されている。この３次元のパターン格子２０において上記スロープが占有する空間は、例えば実装面１１ａの面方向において４行ｎ列の単位格子２１で構成されており、また半導体チップ１２の厚み方向において１層〜４層の単位格子２１で構成されている。このパターン格子２０を構成する単位格子２１は、スロープ１７の構造単位であるスロープ要素が占有する空間である。つまり単位格子２１を占有する絶縁材料により構造単位であるスロープ要素が構成されており、このスロープ要素が積み重ねられる態様で上記スロープ１７が構成されている。なお図２では、パターン格子２０の構成を説明する便宜上、単位格子２１を十分に拡大して示している。   The slope 17 is configured such that structural units (slope elements) made of an insulating material are stacked. More specifically, as shown in FIGS. 2A and 2B, the space in which the slope 17 is provided has two independent directions (row direction and column direction) constituting the mounting surface 11a and a semiconductor chip. A three-dimensional pattern lattice 20 that is an invariant spatial lattice is defined by parallel movement of a predetermined distance in the thickness direction (layer direction). The space occupied by the slope in the three-dimensional pattern lattice 20 is composed of, for example, unit rows 21 of 4 rows and n columns in the surface direction of the mounting surface 11 a, and one to four layers in the thickness direction of the semiconductor chip 12. It consists of a unit cell 21 of layers. The unit cell 21 constituting the pattern lattice 20 is a space occupied by a slope element which is a structural unit of the slope 17. That is, the slope element which is a structural unit is comprised by the insulating material which occupies the unit cell 21, and the said slope 17 is comprised in the aspect by which this slope element is piled up. In FIG. 2, for convenience of explaining the configuration of the pattern lattice 20, the unit lattice 21 is shown sufficiently enlarged.

なおスロープ１７を構成する絶縁性材料としては、エポキシ系の熱硬化性樹脂やアクリル系の光硬化性樹脂、あるいはこれらを混合させたものを用いることが可能であるが、本実施形態では、所定波長の紫外光を一定時間照射することにより硬化される紫外光硬化性樹脂が用いられている。   The insulating material constituting the slope 17 may be an epoxy thermosetting resin, an acrylic photocurable resin, or a mixture thereof, but in this embodiment, a predetermined material is used. An ultraviolet light curable resin that is cured by irradiation with ultraviolet light having a wavelength for a certain period of time is used.

図１に示されるように、こうしたスロープ１７の表面には、第１電極パッド１３と第２電極パッド１５とを電気的に接続する配線１９が積層されている。上述したように実装面１１ａとパッド形成面１２ａとの間の段差がスロープ１７により緩和されているため、こうしたスロープ１７に積層された配線１９も、上記段差による屈曲が十分に抑えられたものとなっている。実装基板１１の第１電極パッド１３とそれらに対応する半導体チップ１２の各第２電極パッド１５とが段差による屈曲により機械的な信頼性が低下されることのない、すなわちスロープ１７を介して配置された機械的な信頼性の高い配線１９により接続されるようになる。   As shown in FIG. 1, wiring 19 for electrically connecting the first electrode pad 13 and the second electrode pad 15 is laminated on the surface of the slope 17. As described above, the step between the mounting surface 11a and the pad forming surface 12a is relaxed by the slope 17, so that the wiring 19 stacked on the slope 17 is also sufficiently suppressed from bending due to the step. It has become. The first electrode pads 13 of the mounting substrate 11 and the respective second electrode pads 15 of the semiconductor chip 12 corresponding thereto are not lowered in mechanical reliability due to bending due to a step, that is, arranged via the slope 17. It is connected by the wiring 19 with high mechanical reliability.

次に、上述した電子装置１０の製造方法について図３及び図４を参照しながら説明する
。図３（ａ）（ｂ）は、電子装置１０の製造方法、特に半導体チップ１２の実装工程における各工程の流れを示すフローチャートである。図４（ａ）〜（ｄ）は、スロープの形成工程を示した図である。 Next, a method for manufacturing the electronic device 10 described above will be described with reference to FIGS. FIGS. 3A and 3B are flowcharts showing the flow of each process in the method for manufacturing the electronic device 10, particularly the mounting process of the semiconductor chip 12. 4A to 4D are views showing a slope forming process.

図３（ａ）に示されるように、電子装置１０の製造方法、特に半導体チップ１２の実装工程においては、配置工程（ステップＳ１１）と、スロープ形成工程（ステップＳ１２）と、配線形成工程（ステップＳ１３）とが順に実施される。   As shown in FIG. 3A, in the manufacturing method of the electronic device 10, particularly in the mounting process of the semiconductor chip 12, an arrangement process (step S11), a slope formation process (step S12), and a wiring formation process (step S13) are performed in order.

配置工程（ステップＳ１１）は、実装基板１１の実装面１１ａに半導体チップ１２を配置する工程である。この工程ではまず、電子装置１０の設計ルールに基づき、実装面１１ａの所定範囲に図示しない接着層が形成される。次いでチップマウンターなどの搬送装置によって半導体チップ１２が接着層上に載置されて、実装基板１１と半導体チップ１２とが接着層を介して接合される。   The placement step (step S11) is a step of placing the semiconductor chip 12 on the mounting surface 11a of the mounting substrate 11. In this step, first, an adhesive layer (not shown) is formed in a predetermined range of the mounting surface 11a based on the design rule of the electronic device 10. Next, the semiconductor chip 12 is placed on the adhesive layer by a transfer device such as a chip mounter, and the mounting substrate 11 and the semiconductor chip 12 are bonded via the adhesive layer.

スロープ形成工程（ステップＳ１２）は、インクジェット法を用いてスロープ１７を形成する工程である。図３（ｂ）に示されるように、このスロープ形成工程（ステップＳ１２）においては、バルク形成工程（ステップＳ１２−１）、吐出工程（ステップＳ１２−２）、硬化工程（Ｓ１２−３）が順に実行される。   A slope formation process (step S12) is a process of forming the slope 17 using the inkjet method. As shown in FIG. 3B, in the slope forming process (step S12), the bulk forming process (step S12-1), the discharging process (step S12-2), and the curing process (S12-3) are sequentially performed. Executed.

バルク形成工程（ステップＳ１２−１）は、図４（ａ）に示されるように、液滴吐出ヘッド３０から第１の絶縁性インクからなる第１の液滴である液滴Ｄ１をその吐出毎に硬化させたスロープ要素２６をパターン格子２０における１層目の１行目から４行目まで、２層目の１行目から３行目まで、３層目の１行目から２行目まで、４層目の１行目に対して順に形成することによりバルク２５が形成される。   In the bulk forming step (step S12-1), as shown in FIG. 4A, the droplet D1 which is the first droplet made of the first insulating ink is discharged from the droplet discharge head 30 every time it is discharged. The slope element 26 hardened to the first layer in the pattern grid 20 from the first line to the fourth line, the second layer from the first line to the third line, the third layer from the first line to the second line The bulk 25 is formed by sequentially forming the first row of the fourth layer.

詳述すると、絶縁材料である紫外光硬化樹脂が溶媒中に分散した絶縁性インクからなる複数の液滴Ｄ１は、それが他の液滴Ｄ１から離間する態様で液滴吐出ヘッド３０から単位格子２１に吐出される。次いで単位格子２１内の液滴Ｄ１が孤立した状態のまま硬化されることにより、１つのスロープ要素２６が形成される。   More specifically, a plurality of droplets D1 made of an insulating ink in which an ultraviolet light curable resin, which is an insulating material, is dispersed in a solvent, is separated from the other droplets D1 by a unit cell from the droplet discharge head 30. 21 is discharged. Next, the droplet D1 in the unit cell 21 is cured while being isolated, so that one slope element 26 is formed.

この際、硬化する前の液滴Ｄ１が隣接する単位格子２１に存在すると、絶縁性インクの表面張力によって液滴Ｄ１同士が合一するように流動して本来定着すべき位置から各液滴Ｄ１が流動してしまう。こうした状況の下で形成されるスロープ１７は、その位置や形状がスロープ１７を構成する液滴Ｄ１の流動によって本来形成されるべき位置や形状と異なるものとなってしまう。そこで、本実施形態の液滴吐出ヘッド３０においては、着弾した液滴Ｄ１がそれぞれ孤立するように、パターン格子２０における同じ行の奇数列あるいは偶数列にのみ液滴Ｄ１が吐出される。１行目の奇数列の単位格子２１に液滴Ｄ１が着弾すると、その着弾タイミングにあわせて紫外光３１が照射されて同液滴Ｄ１が硬化し、１行目の奇数列の単位格子２１にスロープ要素２６が形成される。   At this time, if the droplet D1 before curing exists in the adjacent unit cell 21, each droplet D1 flows from the position to be originally fixed by flowing so that the droplets D1 are united by the surface tension of the insulating ink. Will flow. The position and shape of the slope 17 formed under such circumstances will differ from the position and shape that should originally be formed by the flow of the droplets D1 constituting the slope 17. Therefore, in the liquid droplet ejection head 30 of the present embodiment, the liquid droplets D1 are ejected only to the odd or even columns of the same row in the pattern grid 20 so that the landed liquid droplets D1 are isolated from each other. When the droplets D1 land on the odd-numbered unit cells 21 in the first row, the ultraviolet light 31 is irradiated in accordance with the landing timing, and the droplets D1 are cured, and the unit cells 21 in the odd-numbered columns in the first row are cured. A slope element 26 is formed.

続いて、液滴吐出ヘッド３０のノズルをパターン格子２０の偶数列の直上に移動させて再び駆動することにより、先行した形成された２つのスロープ要素２６の間に液滴Ｄ１が着弾する。そしてこの液滴Ｄ１の着弾タイミングに合わせて再び紫外光３１が照射されることによりパターン格子２０における１層目の１行目のスロープ要素２６が形成される。そして複数のスロープ要素２６をパターン格子２０に敷き詰めて、かつ、積み重ねる態様で液滴Ｄ１の吐出及び硬化を繰り返すことにより、バルク２５が形成される。これらのスロープ要素２６は、着弾した液滴Ｄ１の表面張力によりその各々が球面形状をなすように形成される。そのため、上述したように液滴Ｄ１をその吐出毎に硬化させて形成されるバルク２５は、その形成位置や形状の再現性が向上されるものの、その表面にスロープ要素２６による凸部２５ａ（図６参照）を有したかたちに形成される。   Subsequently, by moving the nozzle of the droplet discharge head 30 directly above the even-numbered row of the pattern grid 20 and driving it again, the droplet D1 lands between the two previously formed slope elements 26. Then, by irradiating the ultraviolet light 31 again in accordance with the landing timing of the droplet D1, the slope element 26 in the first row of the first layer in the pattern grating 20 is formed. The bulk 25 is formed by repeatedly discharging and curing the droplets D1 in such a manner that a plurality of slope elements 26 are spread on the pattern lattice 20 and stacked. Each of the slope elements 26 is formed to have a spherical shape due to the surface tension of the landed droplet D1. Therefore, as described above, the bulk 25 formed by curing the droplet D1 for each discharge improves the reproducibility of the formation position and shape, but the convex portion 25a (see FIG. 6)).

ちなみに、各層のスロープ要素２６を半導体チップ１２に近い側から形成していくことにより、先行して形成したスロープ要素２６が、後続する液滴Ｄ１への紫外光３１の照射する際に光学的な障害になることを回避することが可能になる。   Incidentally, by forming the slope element 26 of each layer from the side close to the semiconductor chip 12, the previously formed slope element 26 is optical when the subsequent droplet D1 is irradiated with the ultraviolet light 31. It becomes possible to avoid becoming an obstacle.

なお、バルク２５は、吐出された液滴Ｄ１をその吐出毎に硬化させたスロープ要素２６を敷き詰めて、かつ、積み重ねられる態様で形成されればよく、例えばスロープ要素２６を積み重ねた積層体をパターン格子２０の１行目から順に形成する態様であってもよい。   The bulk 25 may be formed in such a manner that the slope elements 26 in which the ejected droplets D1 are cured each time it is ejected are stacked and stacked. For example, the bulk 25 is formed by stacking the slope elements 26 in a pattern. The aspect formed in order from the 1st line of the grating | lattice 20 may be sufficient.

吐出工程（ステップＳ１２−２）は、図４（ｂ）に示されるように、バルク形成工程（ステップＳ１２−１）で形成されたバルク２５の表面に対して、第２の液滴である液滴Ｄ２を吐出する工程である。この際吐出される液滴Ｄ２は、バルク２５の形成時に用いた第１の絶縁性インクと同じ絶縁材料を含むとともに同絶縁性インクよりも粘度の低い第２の絶縁性インクからなり、バルク２５の表面の凸部間を埋める流動性を有している。   As shown in FIG. 4B, the discharging process (step S12-2) is a liquid that is a second droplet with respect to the surface of the bulk 25 formed in the bulk forming process (step S12-1). This is a step of discharging the droplet D2. The droplet D2 ejected at this time is made of the second insulating ink containing the same insulating material as the first insulating ink used when forming the bulk 25 and having a lower viscosity than the insulating ink. It has fluidity to fill in the gaps between the convex portions on the surface.

ところで、こうした液滴Ｄ２を吐出する際に、バルク２５の形成時とその液滴の容量を変更せずにパターン格子２０の各行各列に液滴Ｄ２を吐出したのでは、その吐出量が過剰となってバルク２５の周辺に流れ出してしまい、かえってスロープ１７の形状を崩してしまうばかりか、第１電極パッド１３を覆い隠してしまう虞もある。   By the way, when discharging such droplets D2, if the droplets D2 are discharged to each row and column of the pattern grid 20 without changing the volume of the bulk 25 and the droplets, the discharge amount is excessive. As a result, it flows out to the periphery of the bulk 25, and instead of destroying the shape of the slope 17, there is a possibility of covering the first electrode pad 13.

そこで本実施形態では、図５に示されるように、パターン格子２０を構成する各単位格子２１の中から予め選択された一部の単位格子２１（吐出位置）に向けて液滴Ｄ２が吐出される。これにより、液滴Ｄ１と同じ容量の液滴Ｄ２がバルク２５の一部の凸部２５ａに積み重ねられるとともに、液滴Ｄ２の容量が液滴Ｄ１から変更されずとも、上述するような液滴Ｄ２の流れ出しが回避可能になる。   Therefore, in the present embodiment, as shown in FIG. 5, the droplet D <b> 2 is ejected toward a part of the unit grids 21 (ejection positions) selected in advance from among the unit grids 21 constituting the pattern grid 20. The As a result, the droplet D2 having the same volume as the droplet D1 is stacked on a part of the convex portions 25a of the bulk 25, and the droplet D2 as described above is obtained even if the volume of the droplet D2 is not changed from the droplet D1. Can be avoided.

バルク２５の表面、特に凸部２５ａに積み重ねられた低粘度の液滴Ｄ２は、その流動性が高いことから、図６に示されるように、着弾した凸部２５ａの周辺に等方的に濡れ広がることでバルク２５の表面の凸部２５ａの間へと流動することになり、この凸部２５ａの間を液滴Ｄ２によって効果的に埋めることが可能である。こうした液滴Ｄ２の流動により、バルク２５の表面は、その段差が軽減されて、見かけ上、滑らかな表面となる。   Since the low-viscosity droplets D2 stacked on the surface of the bulk 25, in particular, the convex portion 25a have high fluidity, as shown in FIG. 6, the periphery of the landed convex portion 25a is isotropically wet. By spreading, it flows between the convex portions 25a on the surface of the bulk 25, and the space between the convex portions 25a can be effectively filled with the droplets D2. Due to the flow of the droplet D2, the step of the surface of the bulk 25 is reduced, and an apparently smooth surface is obtained.

ここで、絶縁材料として熱硬化性樹脂が用いられる場合には、バルク形成工程（ステップＳ１２−１）では、例えば実装基板１１が加熱されながら液滴Ｄ１が吐出されることになる。このバルク形成工程と吐出工程（ステップＳ１２−２）とが連続して実行されると、バルク形成工程において実装基板１１やバルク２５の温度が昇温されていることから、吐出工程で吐出された液滴Ｄ２がこうしたバルク２５の余熱を受けて着弾後に硬化してしまう場合がある。こうした場合には、バルク２５の表面における凸部２５ａの間に液滴Ｄ２が流動するどころか、同液滴Ｄ２が凸部２５ａ上で硬化してしまうことにより、かえってバルク２５の表面の段差を大きくしてしまう虞がある。そのため、バルク形成工程と吐出工程とを連続して行うことができず、これらの間にバルク２５などを冷却する期間が必要となってしまうことで電子装置１０の生産効率を低下させてしまう虞がある。これに対して、本実施形態では、絶縁材料として紫外光硬化樹脂が用いられることから、上述したような冷却期間が必要ないばかりか、バルク形成工程と吐出工程とを連続して行うことも可能であることから、電子装置１０の生産効率を向上させることもできる。   Here, when a thermosetting resin is used as the insulating material, in the bulk formation step (step S12-1), for example, the droplet D1 is discharged while the mounting substrate 11 is heated. When the bulk forming process and the discharging process (step S12-2) are continuously performed, the temperature of the mounting substrate 11 and the bulk 25 is increased in the bulk forming process, and thus the discharging is performed in the discharging process. The droplet D2 may be cured after landing due to the residual heat of the bulk 25. In such a case, instead of the liquid droplet D2 flowing between the convex portions 25a on the surface of the bulk 25, the liquid droplet D2 is cured on the convex portions 25a, so that the level difference on the surface of the bulk 25 is increased. There is a risk of it. Therefore, the bulk formation process and the discharge process cannot be performed continuously, and a period for cooling the bulk 25 or the like is required between them, which may reduce the production efficiency of the electronic device 10. There is. On the other hand, in this embodiment, since the ultraviolet light curable resin is used as the insulating material, not only the above-described cooling period is necessary, but also the bulk forming process and the discharging process can be performed continuously. Therefore, the production efficiency of the electronic device 10 can also be improved.

硬化工程（ステップＳ１２−３）は、吐出工程（ステップＳ１２−２）でバルク２５の凸部２５ａの間へ流動した液滴Ｄ２を硬化させる工程である。本工程では、バルク形成工程（ステップＳ１２−１）と同様に、液滴Ｄ２に対して紫外光３１が照射される。そして、紫外光３１が照射されることによって、液滴Ｄ２はバルク２５の表面を滑らかにした状
態で硬化されることとなり、バルク２５の表面に硬化物３５が形成される。つまり、バルク２５と硬化物３５とによってスロープ１７を構成することにより、液滴Ｄ１のみからなるスロープの表面と比較して、スロープ１７の表面を滑らかにすることが可能になる。 The curing step (step S12-3) is a step of curing the droplet D2 that has flowed between the convex portions 25a of the bulk 25 in the discharge step (step S12-2). In this step, the ultraviolet light 31 is irradiated to the droplet D2 as in the bulk formation step (step S12-1). By irradiating the ultraviolet light 31, the droplet D <b> 2 is cured with the surface of the bulk 25 smoothed, and a cured product 35 is formed on the surface of the bulk 25. That is, by configuring the slope 17 with the bulk 25 and the cured product 35, the surface of the slope 17 can be made smoother than the surface of the slope made only of the droplets D1.

配線形成工程（ステップＳ１３）は、実装面１１ａの第１電極パッド１３とパッド形成面１２ａの第２電極パッド１５とを電気的に接続する配線１９を形成する工程である。すなわち、スロープ形成工程（ステップＳ１２）において形成されたスロープ１７の表面に配線１９を形成する工程である。配線１９は、導電性材料としての導電性微粒子の分散系からなる導電性インクを用いたインクジェット法によって形成される。本実施形態では、実装面１１ａの第１電極パッド１３の上面からスロープ１７上を通りパッド形成面１２ａの第２電極パッド１５までの各位置に導電性インクからなる液滴が吐出され連続的に配置される。次いで、配置された液滴に加熱処理が施されることにより分散媒の蒸発と導電性微粒子の焼成とが進行して配線１９が形成される。滑らかな表面を有するスロープ１７上に配置された導電性インクからなる配線１９は、液滴Ｄ１のみからなるスロープに比べて、その配線幅や膜厚のばらつきが抑制されることになる。すなわち、隣接した配線との短絡や配線の機械的強度の不足、さらには電気的な抵抗値のばらつきなども低減されて、配線１９の機械的な安定性とともに、電気的な安定性も向上されることになる。つまりは配線１９の信頼性、ひいては電子装置１０の信頼性を向上させることが可能になる。   The wiring forming step (step S13) is a step of forming a wiring 19 that electrically connects the first electrode pad 13 on the mounting surface 11a and the second electrode pad 15 on the pad forming surface 12a. That is, it is a step of forming the wiring 19 on the surface of the slope 17 formed in the slope forming step (step S12). The wiring 19 is formed by an ink jet method using a conductive ink composed of a dispersion system of conductive fine particles as a conductive material. In the present embodiment, droplets made of conductive ink are continuously discharged from the upper surface of the first electrode pad 13 on the mounting surface 11a to the second electrode pad 15 on the pad forming surface 12a through the slope 17 and continuously. Be placed. Next, the disposed droplets are subjected to heat treatment, whereby the dispersion medium evaporates and the conductive fine particles are fired to form the wirings 19. The wiring 19 made of conductive ink disposed on the slope 17 having a smooth surface can suppress variations in the wiring width and film thickness compared to the slope made only of the droplets D1. That is, short-circuiting with adjacent wiring, insufficient mechanical strength of the wiring, and variation in electrical resistance value are reduced, and the electrical stability is improved along with the mechanical stability of the wiring 19. Will be. In other words, it is possible to improve the reliability of the wiring 19 and thus the reliability of the electronic device 10.

なお、導電性インクの導電性微粒子は、数ｎｍ〜数十ｎｍの粒径を有する微粒子であり、例えば銀、金、銅、白金、パラジウム、ロジウム、オスミウム、ルテニウム、イリジウム、鉄、錫、コバルト、ニッケル、クロム、チタン、タンタル、タングステン、インジウム等の金属、あるいはこれらの合金を用いることができる。   The conductive fine particles of the conductive ink are fine particles having a particle diameter of several nanometers to several tens of nanometers, for example, silver, gold, copper, platinum, palladium, rhodium, osmium, ruthenium, iridium, iron, tin, cobalt. Further, metals such as nickel, chromium, titanium, tantalum, tungsten, and indium, or alloys thereof can be used.

一方、分散媒は、導電性微粒子を分散できるもので凝集を起こさないものであれば特に限定されない。例えば、水の他に、メタノール、エタノール、プロパノール、ブタノールなどのアルコール類、ｎ−ヘプタン、ｎ−オクタン、デカン、ドデカン、テトラデカン、トルエン、キシレン、シメン、デュレン、インデン、ジペンテン、テトラヒドロナフタレン、デカヒドロナフタレン、シクロヘキシルベンゼンなどの炭化水素系化合物、またエチレングリコールジメチルエーテル、エチレングリコールジエチルエーテル、エチレングリコールメチルエチルエーテル、ジエチレングリコールジメチルエーテル、ジエチレングリコールジエチルエーテル、ジエチレングリコールメチルエチルエーテル、１，２−ジメトキシエタン、ビス（２−メトキシエチル）エーテル、ｐ−ジオキサンなどのエーテル系化合物、さらにプロピレンカーボネート、縺|ブチロラクトン、Ｎ−メチル−２−ピロリド
ン、ジメチルホルムアミド、ジメチルスルホキシド、シクロヘキサノンなどの極性化合物を例示できる。これらのうち、導電性微粒子の分散性と分散液の安定性、また液滴吐出法への適用の容易さの点で、水、アルコール類、炭化水素系化合物、エーテル系化合物が好ましく、より好ましい分散媒としては、水、炭化水素系化合物を挙げることができる。 On the other hand, the dispersion medium is not particularly limited as long as it can disperse the conductive fine particles and does not cause aggregation. For example, in addition to water, alcohols such as methanol, ethanol, propanol, butanol, n-heptane, n-octane, decane, dodecane, tetradecane, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene, decahydro Hydrocarbon compounds such as naphthalene and cyclohexylbenzene, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, 1,2-dimethoxyethane, bis (2- Methoxyethyl) ether, ether compounds such as p-dioxane, propylene carbonate, Examples include polar compounds such as tyrolactone, N-methyl-2-pyrrolidone, dimethylformamide, dimethyl sulfoxide, and cyclohexanone. Of these, water, alcohols, hydrocarbon compounds, and ether compounds are preferable and more preferable in terms of the dispersibility of the conductive fine particles, the stability of the dispersion, and the ease of application to the droplet discharge method. Examples of the dispersion medium include water and hydrocarbon compounds.

以上説明したように本実施形態の電子装置の製造方法によれば、以下のような効果を得ることができる。
（１）上記実施形態によれば、表面に段差があるバルク２５に対して液滴Ｄ１よりも低粘度であって流動性の高い液滴Ｄ２を吐出して、着弾した液滴Ｄ２をバルク２５の凸部２５ａの間へ流動させて、凸部２５ａの間を埋めた状態で同液滴Ｄ２を硬化させた。そして、その液滴Ｄ２を硬化させた硬化物３５とバルク２５とでスロープ１７を構成した。こうすることにより、スロープ１７の表面を滑らかにすることが可能となる。そして、こうしたスロープ１７に描画される配線１９は、その配線幅及びその膜厚の均一化が図られることとなり、隣接した配線１９との短絡や配線１９の機械的強度の不足などの問題を低減することが可能になる。それゆえ配線の信頼性、ひいては電子装置の信頼性をも向上させることが可能となる。 As described above, according to the electronic device manufacturing method of the present embodiment, the following effects can be obtained.
(1) According to the above embodiment, the droplet D2 having a lower viscosity and higher fluidity than the droplet D1 is discharged to the bulk 25 having a step on the surface, and the landed droplet D2 is discharged to the bulk 25. The liquid droplet D2 was cured in a state where the space between the convex portions 25a was filled and the space between the convex portions 25a was filled. And the slope 17 was comprised with the hardened | cured material 35 and the bulk 25 which hardened the droplet D2. By doing so, the surface of the slope 17 can be made smooth. Then, the wiring 19 drawn on the slope 17 is made uniform in its wiring width and film thickness, thereby reducing problems such as short circuit with the adjacent wiring 19 and insufficient mechanical strength of the wiring 19. It becomes possible to do. Therefore, it is possible to improve the reliability of the wiring and thus the reliability of the electronic device.

（２）上記実施形態の吐出工程（ステップＳ１２−２）では、パターン格子２０を構成する単位格子２１の中から予め選択された一部の単位格子２１（吐出位置）に向けて液滴Ｄ２を吐出した。こうすることにより、凸部２５ａを形成するスロープ要素２６に液滴Ｄ２が積み重ねられることから、低粘度であってその流動性が高い液滴Ｄ２は、これら凸部２５ａの間を効果的に埋めることが可能になる。   (2) In the ejection step (step S12-2) of the above embodiment, the droplets D2 are directed toward some of the unit cells 21 (ejection positions) selected in advance from the unit cells 21 constituting the pattern lattice 20. Discharged. By so doing, the droplets D2 are stacked on the slope element 26 forming the convex portions 25a, so that the droplets D2 having low viscosity and high fluidity effectively fill the space between the convex portions 25a. It becomes possible.

（３）また、一部の単位格子２１（吐出位置）に向けて液滴Ｄ２を吐出することにより、液滴Ｄ１の容量と同じ容量の液滴Ｄ２を吐出したとしても、バルク２５の周辺への液滴Ｄ２の流れ出しが回避可能になる。それゆえスロープ１７を所望の形状に確実に形成することが可能になる。   (3) Further, even when a droplet D2 having the same capacity as that of the droplet D1 is ejected by ejecting the droplet D2 toward a part of the unit cell 21 (ejection position), to the periphery of the bulk 25 The liquid droplet D2 can be prevented from flowing out. Therefore, the slope 17 can be reliably formed in a desired shape.

（４）上記実施形態では、絶縁材料として紫外光硬化樹脂を用いてスロープ１７を形成した。こうすることにより、バルク形成工程（ステップＳ１２−１）と吐出工程（ステップＳ１２−２）とを連続して行ったとしても、絶縁材料として熱硬化性樹脂を用いた場合のように余熱による液滴Ｄ２の硬化が回避される。つまり、バルク２５を冷却する期間を設けることなく、バルク形成工程と吐出工程とを連続して実行することが可能であることから、電子装置１０の生産効率を向上させることも可能である。   (4) In the above embodiment, the slope 17 is formed using an ultraviolet light curable resin as the insulating material. By doing so, even if the bulk formation step (step S12-1) and the discharge step (step S12-2) are performed continuously, the liquid due to residual heat as in the case of using a thermosetting resin as the insulating material. Curing of the drop D2 is avoided. That is, since it is possible to continuously execute the bulk forming process and the discharging process without providing a period for cooling the bulk 25, it is possible to improve the production efficiency of the electronic device 10.

（５）上記実施形態では、液滴Ｄ１をその吐出毎に硬化させながらバルク２５を形成した。こうすることにより、バルク２５の形成位置やその形状の再現性を向上させることが可能になる。再現性が向上したバルク２５で構成されるスロープ１７もその形成位置やその形状の再現性が向上することになる。それゆえ、そうしたスロープ１７に形成される配線１９においては、その配線幅及び膜厚の均一化がより確実に得られることになる。   (5) In the above embodiment, the bulk 25 is formed while the droplets D1 are cured for each discharge. By doing so, it becomes possible to improve the reproducibility of the formation position of the bulk 25 and its shape. The slope 17 composed of the bulk 25 with improved reproducibility also improves the reproducibility of its formation position and shape. Therefore, in the wiring 19 formed on the slope 17, the wiring width and film thickness can be more uniform.

なお、上記実施形態は以下のように変更して実施することもできる。
・上記実施形態では、絶縁材料として紫外光硬化樹脂を用いたが、他の光硬化性樹脂を用いてもよいし、熱硬化性樹脂を用いてもよい。なお、熱硬化性樹脂を用いる場合には、吐出工程（ステップＳ１２−２）において、液滴Ｄ２の硬化が開始されず、バルク２５の凸部２５ａの間へ液滴Ｄ２が確実に流動するような温度までバルク２５の表面を冷却するとよい。 In addition, the said embodiment can also be changed and implemented as follows.
In the above embodiment, the ultraviolet light curable resin is used as the insulating material, but another photo curable resin may be used or a thermosetting resin may be used. In addition, when using a thermosetting resin, hardening of the droplet D2 is not started in a discharge process (step S12-2), but the droplet D2 flows reliably between the convex parts 25a of the bulk 25. The surface of the bulk 25 may be cooled to a certain temperature.

・上記実施形態の吐出工程（ステップＳ１２−２）では、パターン格子２０を構成する各単位格子２１の中から予め選択された一部の単位格子２１に対してのみ、バルク２５の形成時と同じ容量の液滴Ｄ２を吐出した。これに限らず、バルク２５にさらに液滴を吐出する上では、例えばバルク２５の形成時よりも少ない容量の液滴Ｄ２を、パターン格子２０の１層目における全ての単位格子２１に向かって吐出するようにしてもよい。すなわち、バルク２５の表面にある全ての凸部２５ａに対して液滴Ｄ２を積み重ねる態様であってもよい。こうした構成であれば、バルク２５の全ての凸部２５ａの間に対してより確実に液滴Ｄ２が流動することから、スロープ１７の表面をより滑らかにすることが可能になる。   In the ejection process (step S12-2) of the above-described embodiment, only a part of the unit cells 21 selected in advance from the unit cells 21 constituting the pattern lattice 20 is the same as when the bulk 25 is formed. A volume of droplet D2 was discharged. For example, when droplets are further ejected to the bulk 25, for example, a droplet D2 having a smaller capacity than that at the time of forming the bulk 25 is ejected toward all the unit cells 21 in the first layer of the pattern lattice 20. You may make it do. In other words, the droplet D2 may be stacked on all the convex portions 25a on the surface of the bulk 25. With such a configuration, since the droplet D2 flows more reliably between all the convex portions 25a of the bulk 25, the surface of the slope 17 can be made smoother.

・上記実施形態では、パターン格子２０の単位格子２１に向けて液滴Ｄ２を吐出することにより、バルク２５の凸部２５ａに液滴Ｄ２が積み重ねらえる態様とした。これに限らず、バルク２５の表面にさらに液滴を吐出する上では、例えば凸部２５ａの間に向けて液滴を吐出するようにしてもよい。   In the above embodiment, the droplet D2 is stacked on the convex portion 25a of the bulk 25 by discharging the droplet D2 toward the unit cell 21 of the pattern lattice 20. However, the present invention is not limited to this. For further discharging droplets onto the surface of the bulk 25, for example, the droplets may be discharged toward the convex portion 25a.

・上記実施形態では、吐出工程（ステップＳ１２−２）、硬化工程（ステップＳ１２−３）を順に行った。すなわち、全ての液滴Ｄ２の吐出した上で、同液滴Ｄ２の硬化を行った。これに限らず、液滴Ｄ２を硬化させる上では、例えば、液滴Ｄ２をその吐出毎に硬化
を行う態様であってもよい。また例えば、パターン格子２０を複数の単位格子２１から構成される領域に分割し、その分割された領域毎に吐出工程、硬化工程を行う態様であってもよい。絶縁性インクを硬化させた場合には、少なからずその容量が減少することから、上述した構成であれば、後続する液滴Ｄ２が凸部２５ａの間に流動したときにその余剰分が少なくなり、液滴Ｄ２の流れ出しをより抑制することが可能になる。 -In the said embodiment, the discharge process (step S12-2) and the hardening process (step S12-3) were performed in order. That is, after all the droplets D2 were discharged, the droplets D2 were cured. However, the present invention is not limited to this. For curing the droplet D2, for example, the droplet D2 may be cured every time it is ejected. For example, the pattern grid | lattice 20 may be divided | segmented into the area | region comprised from the several unit cell | cell 21, and the discharge process and the hardening process may be performed for every divided | segmented area | region. When the insulating ink is cured, its capacity is reduced to a small extent. Therefore, with the above-described configuration, the excess amount is reduced when the subsequent droplet D2 flows between the convex portions 25a. Further, it is possible to further suppress the flow of the droplet D2.

Ｄ１，Ｄ２…液滴、１０…電子装置、１１…実装基板、１１ａ…実装面、１２…半導体チップ、１２ａ…パッド形成面、１３…第１電極パッド、１５…第２電極パッド、１７…スロープ、１９…配線、２０…パターン格子、２１…単位格子、２５…バルク、２５ａ…凸部、２６…スロープ要素、３０…液滴吐出ヘッド、３１…紫外光、３５…硬化物。   D1, D2 ... droplet, 10 ... electronic device, 11 ... mounting substrate, 11a ... mounting surface, 12 ... semiconductor chip, 12a ... pad forming surface, 13 ... first electrode pad, 15 ... second electrode pad, 17 ... slope , 19 ... wiring, 20 ... pattern lattice, 21 ... unit lattice, 25 ... bulk, 25a ... convex portion, 26 ... slope element, 30 ... droplet discharge head, 31 ... ultraviolet light, 35 ... cured product.

Claims (5)

実装基板の実装面と該実装面に配置された電子部品との段差を緩和する絶縁性のスロープが前記電子部品の外周に形成されて、前記実装基板と前記電子部品とを接続する配線が前記スロープに積層されてなる電子装置の製造方法において、
前記スロープが形成される領域に、吐出毎に硬化された液滴からなる層が重なるかたちに、第１の絶縁性インクからなる第１の液滴の吐出と硬化とを繰り返し、前記第１の液滴からなる凸部が表面に形成されるかたちに前記スロープのバルクを形成する工程と、
前記バルクの表面に、前記バルクの表面に着弾した液滴が前記凸部の間を埋めるように、前記第１の絶縁性インクよりも粘度が低い第２の絶縁性インクからなる第２の液滴をさらに吐出し、同第２の液滴を硬化させることにより、前記スロープの表面を形成する工程とを備えた
ことを特徴とする電子装置の製造方法。 An insulating slope that relaxes the step between the mounting surface of the mounting substrate and the electronic component disposed on the mounting surface is formed on the outer periphery of the electronic component, and the wiring that connects the mounting substrate and the electronic component is the In the manufacturing method of the electronic device laminated on the slope,
The first droplet made of the first insulating ink is repeatedly ejected and cured in such a manner that the layer formed of the droplet cured for each ejection overlaps the region where the slope is formed. Forming a bulk of the slope in the form of convex portions formed of droplets formed on the surface;
A second liquid made of a second insulating ink having a viscosity lower than that of the first insulating ink so that the droplets landed on the surface of the bulk fill the space between the convex portions on the surface of the bulk. And a step of forming the surface of the slope by further discharging the droplets and curing the second droplets. 前記凸部に前記第２の液滴を積み重ねる
請求項１に記載の電子装置の製造方法。 The method for manufacturing an electronic device according to claim 1, wherein the second droplet is stacked on the convex portion. 前記第１の液滴と同じ容量からなる前記第２の液滴を、一部の前記凸部に積み重ねて前記スロープの表面を形成する
請求項１または２に記載の電子装置の製造方法。 3. The method of manufacturing an electronic device according to claim 1, wherein the surface of the slope is formed by stacking the second liquid droplet having the same capacity as the first liquid droplet on a part of the convex portion. 前記第１の液滴よりも小さい容量からなる前記第２の液滴を、全ての前記凸部に積み重ねて前記スロープの表面を形成する
請求項１または２に記載の電子装置の製造方法。 3. The method of manufacturing an electronic device according to claim 1, wherein the second droplet having a smaller volume than the first droplet is stacked on all the convex portions to form the surface of the slope. 4. 前記絶縁性インクとして光硬化性樹脂を用いる
請求項１〜４のいずれか一項に記載の電子装置の製造方法。 The method for manufacturing an electronic device according to claim 1, wherein a photocurable resin is used as the insulating ink.
JP2009092325A 2009-04-06 2009-04-06 Method of manufacturing electronic device Pending JP2010245291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009092325A JP2010245291A (en) 2009-04-06 2009-04-06 Method of manufacturing electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009092325A JP2010245291A (en) 2009-04-06 2009-04-06 Method of manufacturing electronic device

Publications (1)

Publication Number Publication Date
JP2010245291A true JP2010245291A (en) 2010-10-28

Family

ID=43097985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009092325A Pending JP2010245291A (en) 2009-04-06 2009-04-06 Method of manufacturing electronic device

Country Status (1)

Country Link
JP (1) JP2010245291A (en)

Similar Documents

Publication Publication Date Title
US7964955B2 (en) Electronic device package and electronic equipment
US8680687B2 (en) Electrical interconnect for die stacked in zig-zag configuration
KR100738738B1 (en) Device package structure, device packaging method, droplet ejection head, connector, and semiconductor device
US20060263930A1 (en) Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method
JP5018024B2 (en) Electronic component mounting method, electronic substrate, and electronic device
JP2009064966A (en) Multilayer wiring board and manufacturing method thereof, and semiconductor device
JP6291738B2 (en) CIRCUIT BOARD, CIRCUIT BOARD MANUFACTURING METHOD, AND ELECTRONIC DEVICE
JP4207917B2 (en) Manufacturing method of multilayer substrate
US20080104832A1 (en) Method for manufacturing electronic substrate
KR101119031B1 (en) Semiconductor device and method for producing same
US7728234B2 (en) Coreless thin substrate with embedded circuits in dielectric layers and method for manufacturing the same
JP2004228375A (en) Method of forming bump, device and electronic apparatus
KR101064887B1 (en) Wiring structure between steps and wiring method thereof
US20080169574A1 (en) Direct Die Attachment
JP2008218758A (en) Electronic circuit mounting structure
JP2010245291A (en) Method of manufacturing electronic device
JP2010245223A (en) Method of manufacturing electronic device
JP2010219379A (en) Method of mounting electronic component
JP4211842B2 (en) Method for manufacturing electronic substrate and method for manufacturing multilayer wiring substrate
JP2010232383A (en) Electronic device and manufacturing method therefor
JP2003218149A (en) Manufacturing method for electronic parts, electronic parts, manufacturing method for semiconductor device, and electronic instrument
JP2011171416A (en) Electronic device
JP2007012662A (en) Flexible printed board and its connection structure
JP5329868B2 (en) Multilayer circuit board manufacturing method
JP2010232375A (en) Electronic device and method of manufacturing the same