JP2010245262A - Cmos circuit - Google Patents

Cmos circuit Download PDF

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JP2010245262A
JP2010245262A JP2009091992A JP2009091992A JP2010245262A JP 2010245262 A JP2010245262 A JP 2010245262A JP 2009091992 A JP2009091992 A JP 2009091992A JP 2009091992 A JP2009091992 A JP 2009091992A JP 2010245262 A JP2010245262 A JP 2010245262A
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cmos circuit
channel transistor
cmos
transistors
regions
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Mitsue Yamanaka
三枝 山中
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Panasonic Corp
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Priority to PCT/JP2009/005611 priority patent/WO2010116429A1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a CMOS circuit from causing latch-up. <P>SOLUTION: In the CMOS circuit 10, an N-channel transistor 11 and a P-channel transistor 12 are formed on different substrates 1A, 1B, respectively, and the transistors 11, 12 on both substrates 1A, 1B face each other and are connected. In the CMOS circuit 10, since a current path is not formed between the N-channel transistor 11 and the P-channel transistor 12 due to a parasitic transistor, the occurrence of latch-up can be completely prevented. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、ＣＭＯＳ回路とその製造方法に関する。   The present invention relates to a CMOS circuit and a manufacturing method thereof.

ＣＭＯＳ回路は、ＰチャネルルトランジスタとＮチャネルトランジスタとで構成される。従来のＣＭＯＳ回路は、ＰチャネルルトランジスタとＮチャネルトランジスタとが同一基板上に混載されているため、ラッチアップ現象が生じる可能性がある。すなわち、ウェルや基板のｐｎ接合部により形成される寄生トランジスタが、電源や入出力端子からの雑音によりオン状態となり、電源と接地の間に大電流が流れる現象を引き起こす可能性がある。この点に関して、ＣＭＯＳ回路を用いたインバータを例に、具体的に説明する。   The CMOS circuit is composed of a P-channel transistor and an N-channel transistor. In the conventional CMOS circuit, since the P-channel transistor and the N-channel transistor are mixedly mounted on the same substrate, a latch-up phenomenon may occur. That is, the parasitic transistor formed by the well or the pn junction of the substrate may be turned on by noise from the power supply or the input / output terminal, which may cause a phenomenon that a large current flows between the power supply and the ground. This point will be specifically described by taking an inverter using a CMOS circuit as an example.

図１６はインバータ回路の回路図である。図１７は従来のＣＭＯＳ構造のインバータ回路の概念図である。図１７に示すように、従来のＣＭＯＳ構造では、同一の基板３０上にＮチャネルトランジスタ３１とＰチャネルトランジスタ３２が形成されている。図１８は、図１７のインバータ回路のＰＮ接合部に寄生トランジスタが形成されることを示す概念図である。図１８では、ＰＮ接合部によって形成される寄生トランジスタがＴｒ１、Ｔｒ２、Ｔｒ３、Ｔｒ４によって示され、Ｐウェル（ＰＷ）３０Ｐ及びＮウェル（ＮＷ）３０Ｎの抵抗がＲｎｗ、Ｒｐｗによって示されている。なお、Ｔｒ１、Ｔｒ２、Ｔｒ３、Ｔｒ４は全てバイポーラトランジスタである。   FIG. 16 is a circuit diagram of an inverter circuit. FIG. 17 is a conceptual diagram of a conventional inverter circuit having a CMOS structure. As shown in FIG. 17, in the conventional CMOS structure, an N channel transistor 31 and a P channel transistor 32 are formed on the same substrate 30. 18 is a conceptual diagram showing that a parasitic transistor is formed at the PN junction of the inverter circuit of FIG. In FIG. 18, the parasitic transistors formed by the PN junction are indicated by Tr1, Tr2, Tr3, and Tr4, and the resistances of the P well (PW) 30P and the N well (NW) 30N are indicated by Rnw and Rpw. Tr1, Tr2, Tr3, and Tr4 are all bipolar transistors.

このインバータ回路におけるラッチアップ現象のメカニズムについて説明する。出力端子（Ｂ）から外部雑音が入った場合を想定すると((１)）、Ｔｒ１のベースとエミッタ間は順バイアスされ、電流伝播経路（Ｔｒ１→Ｔｒ３）からＲｎｗを通り（(２)）、ＶＤＤに電流が流れる。次に、電流伝播経路（Ｔｒ１→Ｔｒ４→Ｔｒ２）からＲｐｗを通り（(３)）、ＶＳＳに電流が流れる。Ｒｐｗの両端に電位差が生じ、Ｔｒ２のベース・エミッタ間の電圧がある一定の電圧以上になると、Ｔｒ２がＯＮ状態になる。Ｔｒ２のコレクタ電流は、Ｔｒ３のベース電位を下げることになり、Ｔｒ３がＯＮ状態になる。それによって、電流伝播経路（Ｔｒ３→Ｔｒ４→Ｔｒ２）からＲｐｗを通り（(４)）、ＶＤＤとＶＳＳの間に電流パスが形成される。これがラッチアップ現象のメカニズムである。   The mechanism of the latch-up phenomenon in this inverter circuit will be described. Assuming that external noise enters from the output terminal (B) ((1)), the base and emitter of Tr1 are forward-biased and pass through Rnw from the current propagation path (Tr1 → Tr3) ((2)). Current flows through VDD. Next, current flows through VSS through the current propagation path (Tr1 → Tr4 → Tr2) through Rpw ((3)). When a potential difference occurs between both ends of Rpw and the voltage between the base and the emitter of Tr2 exceeds a certain voltage, Tr2 is turned on. The collector current of Tr2 lowers the base potential of Tr3, and Tr3 is turned on. As a result, a current path is formed between VDD and VSS through Rpw from the current propagation path (Tr3 → Tr4 → Tr2) ((4)). This is the mechanism of the latch-up phenomenon.

ラッチアップを防止するための技術として、Ｐウェル（ＰＷ）３０Ｐ及びＮウェル（ＮＷ）３０Ｎのコンタクトや基板３０のコンタクトを頻繁にとることにより、電位のふらつきを防止する方法がある。しかし、実際のＣＭＯＳ回路においては、集積度の高いレイアウトが要求されるため、コンタクト領域を十分に確保できないという問題がある。   As a technique for preventing latch-up, there is a method of preventing potential fluctuation by frequently making contacts of the P well (PW) 30P and the N well (NW) 30N and the contact of the substrate 30. However, since an actual CMOS circuit requires a highly integrated layout, there is a problem that a sufficient contact region cannot be secured.

ＳＯＩ構造のＣＭＯＳ回路においては、寄生トランジスタが形成する電流パスを遮断することにより、ラッチアップ現象を防止できる。しかし現実には、ＳＯＩは薄膜で形成されており、大電流を流す回路では耐えられない（例えば、非特許文献１参照）。大電流に対応したＣＭＯＳアナログスイッチも製品化されているが（例えば、非特許文献２参照）、この種の従来の製品はトランジスタ単体で構成されたものである。将来的に回路が複雑になり複数のトランジスタで構成されるようになった場合、寄生トランジスタが形成する電流パスを遮断することは難しくなる。   In a CMOS circuit having an SOI structure, a latch-up phenomenon can be prevented by blocking a current path formed by a parasitic transistor. However, in reality, the SOI is formed of a thin film and cannot withstand a circuit through which a large current flows (see, for example, Non-Patent Document 1). A CMOS analog switch corresponding to a large current has been commercialized (see, for example, Non-Patent Document 2), but this type of conventional product is constituted by a single transistor. If the circuit becomes complex in the future and is composed of a plurality of transistors, it is difficult to cut off the current path formed by the parasitic transistors.

また、基板制御技術の適用に関して言えば、従来のＣＭＯＳ回路のレイアウト構成ではＮチャネルトランジスタとＰチャネルトランジスタとが同一基板上に混在して形成され、これらのトランジスタを形成するためのＰウェル（ＰＷ）とＮウェル（ＮＷ）が同一チップ上に多数分離して配置されているため、多数のウェルに電力供給を行う必要がある。また、基板制御対象トランジスタに対して制御用の配線接続をしなければならない。このため、各トランジスタに電力を供給する電源設計と同様の設計方法が基板制御用の回路にも採用されていた。このような設計方法は、設計工数や配線領域の観点から、あまり効率的とは言い難い。基板制御技術の動向を踏まえると、将来の高性能低電力ＬＳＩは電源制御ブロック毎にスピードと電力の要求や回路的特徴に応じて最適な電源電圧と閾値電圧（Ｖｔｈ）の供給が要求される。（例えば、非特許文献３参照）   As for the application of the substrate control technology, in the conventional CMOS circuit layout configuration, an N-channel transistor and a P-channel transistor are formed on the same substrate, and a P well (PW) for forming these transistors is formed. ) And N wells (NW) are arranged separately on the same chip, and it is necessary to supply power to many wells. In addition, a wiring connection for control must be connected to the substrate control target transistor. For this reason, a design method similar to the power supply design for supplying power to each transistor has been adopted in the circuit for substrate control. Such a design method is not very efficient from the viewpoint of design man-hours and wiring area. Considering the trend of substrate control technology, future high-performance low-power LSIs are required to supply optimal power supply voltage and threshold voltage (Vth) according to speed and power requirements and circuit characteristics for each power supply control block. . (For example, see Non-Patent Document 3)

特開２００３−９２３７５号公報JP 2003-92375 A

相崎尚昭著，「薄膜ＳＯＩ技術」，財団法人 武田計測先端知財団，［平成２０年１２月１日検索］、インターネット＜ＵＲＬ：http://unit.aist.go.jp/ripo/ci/symposium/management/aizaki.pdf＞Naoaki Aizaki, “Thin Film SOI Technology”, Takeda Measurement Advanced Intelligence Foundation, [Searched on December 1, 2008], Internet <URL: http://unit.aist.go.jp/ripo/ci/symposium /management/aizaki.pdf> 「大電流、２５Ω、ＳＰＤＴ、ＣＭＯＳアナログスイッチ」，マキシム・ジャパン株式会社，［平成２０年１２月１日検索］、インターネット＜ＵＲＬ：http://datasheets.maxim-ic.com/jp/ds/MAX4659-MAX4660_jp.pdf＞“High Current, 25Ω, SPDT, CMOS Analog Switch”, Maxim Japan, Inc., [December 1, 2008 search], Internet <URL: http://datasheets.maxim-ic.com/jp/ds/ MAX4659-MAX4660_en.pdf> 黒田忠広著，「ＶＴＣＭＯＳ」，株式会社 東芝（システムＬＳＩ技術研究所）［平成２０年１２月１日検索］、インターネット＜ＵＲＬ：http://www.realize-se.co.jp/items/bt/128-129/2/index.html＞Tadahiro Kuroda, “VTCMOS”, Toshiba Corporation (System LSI Research Laboratories) [searched on December 1, 2008], Internet <URL: http://www.realize-se.co.jp/items/bt /128-129/2/index.html>

上述したように、従来のＣＭＯＳ回路では、ウェルや基板のｐｎ接合部により形成される寄生トランジスタによる電流パスを完全に遮断することができなかったため、ラッチアップの発生を有効に防止することができなかった。   As described above, in the conventional CMOS circuit, the current path caused by the parasitic transistor formed by the well or the pn junction of the substrate cannot be completely cut off, so that the occurrence of latch-up can be effectively prevented. There wasn't.

本発明の目的は、寄生トランジスタによるＮチャネルトランジスタとＰチャネルトランジスタ間の電流パスの形成を完全に防止してラッチアップの発生を防止することができる新規な構成のＣＭＯＳ回路とその製造方法を提供することである。   An object of the present invention is to provide a CMOS circuit having a novel configuration capable of completely preventing the formation of a current path between an N-channel transistor and a P-channel transistor by a parasitic transistor and preventing the occurrence of latch-up, and a method for manufacturing the same. It is to be.

本発明は、ＮチャネルトランジスタとＰチャネルトランジスタがそれぞれ別の基板上に形成され、両基板上のトランジスタが互いに向き合わせて接続されたＣＭＯＳ回路を提供する。   The present invention provides a CMOS circuit in which an N-channel transistor and a P-channel transistor are formed on different substrates, and the transistors on both substrates are connected to face each other.

また、本発明は、上記ＣＭＯＳ回路が複数接続されたＣＭＯＳ回路であって、Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士が、それぞれ基板面に沿った方向に隣り合うように並べて配置されたＣＭＯＳ回路を提供する。   Further, the present invention is a CMOS circuit in which a plurality of the above-described CMOS circuits are connected, in which the regions where the N-channel transistors are formed and the regions where the P-channel transistors are formed are respectively in the direction along the substrate surface. CMOS circuits arranged side by side are provided.

上記ＣＭＯＳ回路では、前記領域の周囲が絶縁材で覆われている。   In the CMOS circuit, the periphery of the region is covered with an insulating material.

また、本発明は、上記ＣＭＯＳ回路が複数接続されたＣＭＯＳ回路であって、Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士が、それぞれ基板の厚さ方向に分離して配置されたＣＭＯＳ回路を提供する。   Further, the present invention is a CMOS circuit in which a plurality of the above-described CMOS circuits are connected, and regions where N-channel transistors are formed and regions where P-channel transistors are formed are respectively in the thickness direction of the substrate. A CMOS circuit is provided separately.

また、本発明は、ＮチャネルトランジスタとＰチャネルトランジスタとをそれぞれ別の基板上に形成し、両基板上のトランジスタを互いに向き合わせて接合するＣＭＯＳ回路の製造方法を提供する。   The present invention also provides a method of manufacturing a CMOS circuit in which an N-channel transistor and a P-channel transistor are formed on different substrates, and the transistors on both substrates are bonded to face each other.

また、本発明は、上記ＣＭＯＳ回路が複数接続されたＣＭＯＳ回路の製造方法であって、Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士を、それぞれ基板面に沿った方向に隣り合うように並べて配置するＣＭＯＳ回路の製造方法を提供する。   The present invention is also a method for manufacturing a CMOS circuit in which a plurality of the above-mentioned CMOS circuits are connected, wherein regions where N-channel transistors are formed and regions where P-channel transistors are formed are respectively formed on the substrate surface. Provided is a method for manufacturing a CMOS circuit which is arranged side by side so as to be adjacent to each other in the direction along the line.

上記ＣＭＯＳ回路の製造方法では、前記領域の周囲を絶縁材で覆う。   In the CMOS circuit manufacturing method, the periphery of the region is covered with an insulating material.

また、本発明は、上記ＣＭＯＳ回路が複数接続されたＣＭＯＳ回路の製造方法であって、Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士を、それぞれ基板の厚さ方向に分離して配置するＣＭＯＳ回路の製造方法を提供する。   Further, the present invention is a method of manufacturing a CMOS circuit in which a plurality of the above-described CMOS circuits are connected, wherein the regions where N-channel transistors are formed and the regions where P-channel transistors are formed are respectively connected to the thickness of the substrate. Provided is a method for manufacturing a CMOS circuit which is arranged separately in the vertical direction.

本発明に係るＣＭＯＳ回路によれば、ＮチャネルトランジスタとＰチャネルトランジスタの間に寄生トランジスタによる電流パスが形成されないため、ラッチアップの発生を完全に防止できる。また、本発明に係るＣＭＯＳ回路の製造方法によれば、ラッチアップが発生しないＣＭＯＳ回路を製造できる。   According to the CMOS circuit of the present invention, since a current path due to a parasitic transistor is not formed between the N-channel transistor and the P-channel transistor, it is possible to completely prevent the occurrence of latch-up. In addition, according to the CMOS circuit manufacturing method of the present invention, a CMOS circuit that does not cause latch-up can be manufactured.

本発明の第１の実施形態を示す概念図The conceptual diagram which shows the 1st Embodiment of this invention 図１のＣＭＯＳ回路における寄生トランジスタの構成を示す概念図Schematic diagram showing the configuration of parasitic transistors in the CMOS circuit of FIG. 本発明の第１の実施形態におけるＣＭＯＳ回路のＮチャネルトランジスタ領域の断面図（ａ）及びＰチャネルトランジスタ領域の断面図（ｂ）Sectional view (a) of the N-channel transistor region and sectional view of the P-channel transistor region (b) of the CMOS circuit in the first embodiment of the present invention Ｎチャネルトランジスタ領域及びＰチャネルトランジスタ領域を互いに接合する直前の状態を示す断面図Sectional drawing which shows the state just before joining N channel transistor region and P channel transistor region mutually Ｎチャネルトランジスタ領域及びＰチャネルトランジスタ領域を互いに接合した状態を示す断面図Sectional drawing which shows the state which joined the N channel transistor area | region and the P channel transistor area | region mutually Ｎチャネルトランジスタ領域の斜視図（ａ）及びＰチャネルトランジスタ領域の斜視図（ｂ）Perspective view of N-channel transistor region (a) and perspective view of P-channel transistor region (b) Ｎチャネルトランジスタ領域及びＰチャネルトランジスタ領域を互いに接合する直前の状態を示す斜視図The perspective view which shows the state just before joining N channel transistor region and P channel transistor region mutually Ｎチャネルトランジスタ領域及びＰチャネルトランジスタ領域を互いに接合した状態を示す斜視図The perspective view which shows the state which mutually joined the N channel transistor area | region and the P channel transistor area | region. 各トランジスタ領域の配置を概念的に示した斜視図A perspective view conceptually showing the arrangement of each transistor region Ｐチャネルトランジスタ領域のウェルレイアウトを示す平面図（ａ）及びＮチャネルトランジスタ領域のウェルレイアウトを示す平面図（ｂ）A plan view showing a well layout of a P-channel transistor region (a) and a plan view showing a well layout of an N-channel transistor region (b) ＮＡＮＤ回路の回路図Circuit diagram of NAND circuit 本発明の第１の実施形態におけるＮＡＮＤ回路の構造を示す斜視図The perspective view which shows the structure of the NAND circuit in the 1st Embodiment of this invention 本発明の第２の実施形態におけるＣＭＯＳ回路のＮチャネルトランジスタ領域の断面図（ａ）及びＰチャネルトランジスタ領域の断面図（ｂ）Sectional view (a) of the N-channel transistor region and sectional view of the P-channel transistor region (b) of the CMOS circuit in the second embodiment of the present invention 本発明の第２の実施形態におけるＣＭＯＳ回路の各トランジスタ領域の配置を概念的に示した斜視図The perspective view which showed notionally arrangement | positioning of each transistor area | region of the CMOS circuit in the 2nd Embodiment of this invention 本発明の第３の実施形態におけるＣＭＯＳ回路の各トランジスタ領域の配置を概念的に示した斜視図The perspective view which showed notionally arrangement | positioning of each transistor area | region of the CMOS circuit in the 3rd Embodiment of this invention インバータ回路の回路図Circuit diagram of inverter circuit 従来のＣＭＯＳ構造のインバータ回路の概念図Conceptual diagram of conventional inverter circuit with CMOS structure 図１７のインバータ回路のＰＮ接合部に形成される寄生トランジスタを示す概念図17 is a conceptual diagram showing a parasitic transistor formed at the PN junction of the inverter circuit of FIG. 従来のスタンダードセルのウェル構造を示す断面図Sectional view showing the well structure of a conventional standard cell 従来のスタンダードセル方式によるウェルレイアウトを示す平面図Plan view showing well layout by conventional standard cell method

以下、本発明を実施するための形態を、図面を参照しつつ説明する。以下の実施形態では、本発明のＣＭＯＳ回路をインバータ回路に適用した例について説明する。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following embodiments, an example in which the CMOS circuit of the present invention is applied to an inverter circuit will be described.

（第１の実施形態）
図１は本発明の第１の実施形態を示す概念図である。図２は図１のＣＭＯＳ回路における寄生トランジスタの構成を示す概念図である。このＣＭＯＳ回路１０においては、Ｎチャネルトランジスタ１１とＰチャネルトランジスタ１２とが、それぞれ別の基板（Ｎ基板）１Ａ、１Ｂ上に形成されることにより、互いに分離されている。ＰＮ接合部によって形成されるトランジスタは、Ｔｒ５（図１８のＴｒ２に相当）及びＴｒ６（図１８のＴｒ４に相当）となる。図１８のＴｒ１及びＴｒ３に相当するトランジスタは、このＣＭＯＳ回路１０においては、Ｐウェル（ＰＷ）２とＮウェル（ＮＷ）３によるＰＮ接合部が互いに分離されているため形成されない。したがって、このＣＭＯＳ回路１０は、出力端子（Ｂ）から外部雑音が入った場合でも（丸囲み符号１）、ＶＤＤとＶＳＳの間に電流パスが形成されないため、ラッチアップを起こさない。 (First embodiment)
FIG. 1 is a conceptual diagram showing a first embodiment of the present invention. FIG. 2 is a conceptual diagram showing the configuration of parasitic transistors in the CMOS circuit of FIG. In this CMOS circuit 10, an N channel transistor 11 and a P channel transistor 12 are separated from each other by being formed on different substrates (N substrates) 1A and 1B. Transistors formed by the PN junction are Tr5 (corresponding to Tr2 in FIG. 18) and Tr6 (corresponding to Tr4 in FIG. 18). Transistors corresponding to Tr1 and Tr3 in FIG. 18 are not formed in the CMOS circuit 10 because the PN junctions of the P well (PW) 2 and the N well (NW) 3 are separated from each other. Therefore, even when external noise enters from the output terminal (B) (circled code 1), the CMOS circuit 10 does not cause a latch-up because a current path is not formed between VDD and VSS.

図３〜図５は、本発明の第１の実施形態におけるＣＭＯＳ回路の一連の製造工程を示す断面図である。この実施形態のＣＭＯＳ回路１０は、Ｎチャネルトランジスタ１１とＰチャネルトランジスタ１２とを各々別体として製造した後（図３）、両者を互いに重ね合わせて接合することにより製造される（図４、図５）。   3 to 5 are sectional views showing a series of manufacturing steps of the CMOS circuit according to the first embodiment of the present invention. The CMOS circuit 10 of this embodiment is manufactured by manufacturing the N-channel transistor 11 and the P-channel transistor 12 as separate bodies (FIG. 3) and then superimposing them on each other and bonding them (FIG. 4, FIG. 4). 5).

図３（ａ）及び図３（ｂ）は、それぞれ別体として製造されたＮチャネルトランジスタ１１及びＰチャネルトランジスタ１２を示している。Ｎチャネルトランジスタ１１のゲートＧ１、ソースＳ１、ドレインＤ１には、第一層配線６Ａが接続されている。第一層配線６Ａに形成された空間には絶縁材５Ａが注入されている。Ｐチャネルトランジスタ１２のゲートＧ２、ソースＳ２、ドレインＤ２には、第一層配線６Ｂが接続されている。第一層配線６Ｂに形成された空間には絶縁材５Ｂが注入されている。また、第一層配線６Ｂの上には第二層配線７が形成され、ゲートＧ２とドレインＤ２が第二層配線７の表面まで延在している。そして、第二層配線７の上に半田ペースト層８が設けられている。   FIGS. 3A and 3B show an N-channel transistor 11 and a P-channel transistor 12 that are manufactured separately. A first layer wiring 6A is connected to the gate G1, the source S1, and the drain D1 of the N-channel transistor 11. An insulating material 5A is injected into the space formed in the first layer wiring 6A. A first layer wiring 6B is connected to the gate G2, the source S2, and the drain D2 of the P-channel transistor 12. An insulating material 5B is injected into the space formed in the first layer wiring 6B. A second layer wiring 7 is formed on the first layer wiring 6B, and the gate G2 and the drain D2 extend to the surface of the second layer wiring 7. A solder paste layer 8 is provided on the second layer wiring 7.

図４はＮチャネルトランジスタ１１及びＰチャネルトランジスタ１２を互いに接合する直前の状態を示し、図５は両トランジスタを互いに接合した状態を示している。図４に示すように、Ｎチャネルトランジスタ１１とＰチャネルトランジスタ１２の電極が形成されている面同士を互いに向き合わせた状態で、図５に示すように、両トランジスタ１１、１２を互いに重ね合わせて接合することによりＣＭＯＳ回路１０が製造される。両トランジスタ１１、１２の配線同士は、Ｐチャネルトランジスタ１２の第二配線７上に形成された半田ペースト層８で接着されることにより互いに接続される。   4 shows a state immediately before the N-channel transistor 11 and the P-channel transistor 12 are joined to each other, and FIG. 5 shows a state in which both transistors are joined to each other. As shown in FIG. 4, with the surfaces on which the electrodes of the N-channel transistor 11 and the P-channel transistor 12 are formed facing each other, the transistors 11 and 12 are overlapped with each other as shown in FIG. The CMOS circuit 10 is manufactured by bonding. The wirings of both transistors 11 and 12 are connected to each other by being bonded with a solder paste layer 8 formed on the second wiring 7 of the P-channel transistor 12.

図６〜図８は、本発明の第１の実施形態におけるＣＭＯＳ回路の一連の製造工程を示す斜視図である。これらの図は、回路の立体構造を概念的に示したものである。図６（ａ）、（ｂ）は図３（ａ）、（ｂ）に対応し、図７は図４に対応し、図８は図５に対応している。なお、図６〜図８においては、両トランジスタ１１、１２同士の配線接続状態を分かりやすくするために、第一層配線６と第二層配線７の周囲の空間を埋める絶縁材は省略されている。   6 to 8 are perspective views showing a series of manufacturing steps of the CMOS circuit according to the first embodiment of the present invention. These drawings conceptually show the three-dimensional structure of the circuit. 6A and 6B correspond to FIGS. 3A and 3B, FIG. 7 corresponds to FIG. 4, and FIG. 8 corresponds to FIG. 6 to 8, in order to make it easy to understand the wiring connection state between the transistors 11 and 12, the insulating material that fills the space around the first layer wiring 6 and the second layer wiring 7 is omitted. Yes.

図５、図８のように両トランジスタ１１、１２を対応する電極同士を正確に位置合わせして重ね合わせることができるように、各トランジスタ１１、１２の四隅には、図９に示すように十字マークＰ１〜Ｐ４、Ｎ１〜Ｎ４が付されている。両トランジスタ１１、１２の対応する十字マーク同士、この例では、Ｐ１とＮ１、Ｐ２とＮ２、Ｐ３とＮ３、Ｐ４とＮ４をそれぞれ位置合わせして重ね合わせることによって、両トランジスタ１１、１２に形成されている配線同士が互いに正確に接続される。   As shown in FIG. 9, cross-sections are formed at the four corners of the transistors 11 and 12 so that the corresponding electrodes of the transistors 11 and 12 can be accurately aligned and overlapped as shown in FIGS. Marks P1 to P4 and N1 to N4 are attached. The corresponding cross marks of the transistors 11 and 12 are formed in the transistors 11 and 12 by aligning and overlapping P1 and N1, P2 and N2, P3 and N3, and P4 and N4 in this example. Wirings are connected to each other accurately.

以上の製造工程により、Ｎチャネルトランジスタ１１の基板１ＡとＰチャネルトランジスタ１２の基板１Ｂが互いに分離された構造のＣＭＯＳ回路１０が製造される。   Through the above manufacturing process, the CMOS circuit 10 having a structure in which the substrate 1A of the N-channel transistor 11 and the substrate 1B of the P-channel transistor 12 are separated from each other is manufactured.

次に、上記の構造のＣＭＯＳ回路のウェルレイアウトについて説明する。ＣＭＯＳ回路のレイアウトは、スタンダードセルを使用する手法が主流であるため、本実施形態では、スタンダードセル方式のウェルレイアウトを前提に説明する。   Next, the well layout of the CMOS circuit having the above structure will be described. Since the CMOS circuit layout is mainly based on a method using standard cells, this embodiment will be described on the premise of a standard cell type well layout.

図１９は従来のスタンダードセル方式におけるウェル構造を示す断面図である。Ｐウェル（ＰＷ）３０ＰとＮウェル（ＮＷ）３０Ｎは上下に重なり合っている。このスタンダードセルを複数並べて配置すると、ＰチャネルトランジスタとＮチャネルトランジスタとが混載されることにより、図２０に示すように、Ｐウェル（ＰＷ）３０Ｐ及びＮウェル（ＮＷ）３０Ｎも混載された構造になる。その結果、共通の基板制御用の電力が供給されるウェルであっても電力配線が分離されるため、電源配線が複雑化する。図２０の例では、ＶＳＳ用の配線９ＳとＶＤＤ用の配線９Ｄがそれぞれ複数に分離されて交互に配置されている。電源配線の複雑化により、信号配線の設計も複雑化することになる。   FIG. 19 is a sectional view showing a well structure in a conventional standard cell system. The P well (PW) 30P and the N well (NW) 30N overlap each other. When a plurality of standard cells are arranged side by side, a P-channel transistor and an N-channel transistor are mixedly mounted, so that a P-well (PW) 30P and an N-well (NW) 30N are also mounted together as shown in FIG. Become. As a result, since the power wiring is separated even in the well supplied with the common substrate control power, the power wiring is complicated. In the example of FIG. 20, the VSS wiring 9S and the VDD wiring 9D are separated into a plurality and alternately arranged. The complexity of power supply wiring also complicates signal wiring design.

これに対し、この実施形態のＣＭＯＳ回路構造を適用することにより、図１０（ａ）、図１０（ｂ）のようなウェルレイアウトとし、同一基板上にＰウェル（ＰＷ）２とＮウェル（ＮＷ）３とが混載されていないレイアウト構造とすることができる。その結果、基板制御用の配線設計を簡素化でき、それに伴い設計工数の削減が可能となり、他の配線領域を信号配線領域として有効活用できるようになるため開発効率が向上する。   On the other hand, by applying the CMOS circuit structure of this embodiment, the well layout as shown in FIGS. 10A and 10B is obtained, and the P well (PW) 2 and the N well (NW) are formed on the same substrate. ) 3 and a layout structure in which 3 is not mixedly mounted. As a result, the wiring design for board control can be simplified, and the design man-hours can be reduced accordingly, and other wiring areas can be effectively used as signal wiring areas, so that development efficiency is improved.

本実施形態のＣＭＯＳ回路１によれば、ラッチアップを防止することができるという効果に加えて、基板制御用の配線設計を簡素化できるという効果が得られる。ラッチアップを防止できるという効果に関しては、大電流に対応したＣＭＯＳアナログスイッチが製品化されていることから、薄膜を使用するＳＯＩでは解決できない製品等に特に効果的であるといえる。   According to the CMOS circuit 1 of the present embodiment, in addition to the effect that latch-up can be prevented, the effect that the wiring design for substrate control can be simplified can be obtained. With respect to the effect of preventing latch-up, it can be said that it is particularly effective for products that cannot be solved by SOI using a thin film, since CMOS analog switches corresponding to large currents have been commercialized.

なお、本発明のＣＭＯＳ回路のその他の適用例として、図１１に示すＮＡＮＤ回路を挙げることができる。図１２はインバータ回路と同様の製造プロセスにより製造したＮＡＮＤ回路の立体構造を示している。   As another application example of the CMOS circuit of the present invention, a NAND circuit shown in FIG. 11 can be cited. FIG. 12 shows a three-dimensional structure of a NAND circuit manufactured by the same manufacturing process as that of the inverter circuit.

（第２の実施形態）
図１３は本発明の第２の実施形態におけるＣＭＯＳ回路の内部構造を概念的に示した断面図である。図１３（ａ）はＮチャネルトランジスタの断面構造を、図１３（ｂ）はＰチャネルトランジスタの断面構造をそれぞれ示している。図１４は本発明の第２の実施形態におけるＣＭＯＳ回路の各トランジスタ領域の配置を概念的に示した斜視図である。この実施形態のＣＭＯＳ回路２０は、図１４に示すように、複数（この例では２つ）のＣＭＯＳ回路２１、２２を、伝導型が同一のトランジスタ領域同士を横方向すなわち基板面に沿った方向に隣り合うように並べて配置してなる。伝導型が同一であっても、基板制御によって制御する電圧値の異なるトランジスタ領域間は電気的導通を防止する必要があるため、図１３（ａ）、（ｂ）に示すように、各ＣＭＯＳ回路２１、２２を構成する各トランジスタ１１、１２の周囲はそれぞれ絶縁材５で覆われている。 (Second Embodiment)
FIG. 13 is a sectional view conceptually showing the internal structure of the CMOS circuit in the second embodiment of the present invention. FIG. 13A shows a cross-sectional structure of an N-channel transistor, and FIG. 13B shows a cross-sectional structure of a P-channel transistor. FIG. 14 is a perspective view conceptually showing the arrangement of the transistor regions of the CMOS circuit according to the second embodiment of the present invention. As shown in FIG. 14, the CMOS circuit 20 of this embodiment includes a plurality (two in this example) of CMOS circuits 21 and 22, in which the transistor regions having the same conductivity type are arranged in the lateral direction, that is, along the substrate surface. Are arranged next to each other. Even if the conductivity type is the same, since it is necessary to prevent electrical conduction between transistor regions having different voltage values controlled by substrate control, as shown in FIGS. The peripheries of the transistors 11 and 12 constituting the transistors 21 and 22 are each covered with an insulating material 5.

図１４に例示するＣＭＯＳ回路２０は、Ｎチャネルトランジスタ領域２１ＮとＰチャネルトランジスタ領域２１Ｐとで構成された第１のＣＭＯＳ回路２１と、Ｎチャネルトランジスタ領域２２ＮとＰチャネルトランジスタ領域２２Ｐとで構成された第２のＣＭＯＳ回路２２とからなり、各ＣＭＯＳ回路２１、２２単位で基板制御を行うものである。各トランジスタ領域２１Ｎ、２１Ｐ、２２Ｎ、２２Ｐの四隅には、十字マークＰ１〜Ｐ４、Ｎ１〜Ｎ４が付されている。Ｎチャネルトランジスタ領域２１Ｎ、２２ＮとＰチャネルトランジスタ領域２１Ｐ、２２Ｐの対応する十字マーク同士、この例では、Ｐ１とＮ１、Ｐ２とＮ２、Ｐ３とＮ３、Ｐ４とＮ４をそれぞれ位置合わせして重ね合わせることによって、Ｎチャネルトランジスタ領域２１Ｎ、２２Ｎに形成されている配線とＰチャネルトランジスタ領域２１Ｐ、２２Ｐに形成されている配線同士が正確に互いに接続される。   A CMOS circuit 20 illustrated in FIG. 14 includes a first CMOS circuit 21 configured by an N-channel transistor region 21N and a P-channel transistor region 21P, and an N-channel transistor region 22N and a P-channel transistor region 22P. The second CMOS circuit 22 is used to control the substrate in units of the CMOS circuits 21 and 22. Cross marks P1 to P4 and N1 to N4 are attached to the four corners of each of the transistor regions 21N, 21P, 22N, and 22P. The corresponding cross marks in the N channel transistor regions 21N, 22N and the P channel transistor regions 21P, 22P are aligned and overlapped in this example, P1 and N1, P2 and N2, P3 and N3, and P4 and N4, respectively. Thus, the wiring formed in the N channel transistor regions 21N and 22N and the wiring formed in the P channel transistor regions 21P and 22P are accurately connected to each other.

本実施形態の構成によれば、各ＣＭＯＳ回路２１、２２におけるラッチアップの発生を防止するとともに、各ＣＭＯＳ回路２１、２２ごとに基板制御電圧を調整することができる。   According to the configuration of the present embodiment, it is possible to prevent the latch-up from occurring in the CMOS circuits 21 and 22, and to adjust the substrate control voltage for each of the CMOS circuits 21 and 22.

（第３の実施形態）
図１５は本発明の第３の実施形態におけるＣＭＯＳ回路の各トランジスタ領域の配置を概念的に示した斜視図である。この実施形態のＣＭＯＳ回路３０は、Ｎチャネルトランジスタ領域３１Ｎ、３２Ｎ同士、Ｐチャネルトランジスタ領域３１Ｐ、３２Ｐ同士を、それぞれ基板の厚さ方向に分離して配置してなる。そして、Ｎチャネルトランジスタ領域３１ＮとＰチャネルトランジスタ領域３１Ｐとで構成された第１のＣＭＯＳ回路３１と、Ｎチャネルトランジスタ領域３２ＮとＰチャネルトランジスタ領域３２Ｐとで構成された第２のＣＭＯＳ回路３２とを、各ＣＭＯＳ回路３１、３２単位で基板制御を行うものである。各トランジスタ領域３１Ｎ、３１Ｐ、３２Ｎ、３２Ｐの四隅には、十字マークＰ１〜Ｐ４、Ｎ１〜Ｎ４が付されており、対応する十字マーク同士をそれぞれ位置合わせして重ね合わせることによって、上下に隣接するトランジスタ領域同士が正確に位置合わせされて接合される。第１のＣＭＯＳ回路３１を構成するＮチャネルトランジスタ領域３１ＮとＰチャネルトランジスタ領域３１Ｐは、対応する十字マーク同士をそれぞれ位置合わせして接合することにより、各領域３１Ｎ、３１Ｐに形成されている配線同士が正確に互いに接続される。一方、第２のＣＭＯＳ回路３２を構成するＮチャネルトランジスタ領域３２ＮとＰチャネルトランジスタ領域３２Ｐの間には、第１のＣＭＯＳ回路３１が存在するため、従来技術である特開２００３−９２３７５号公報を用いて、第１のＣＭＯＳ回路３１の基板にスルーホールなどを形成することにより、両トランジスタ領域３２Ｎ、３２Ｐ間の配線接続がなされる。 (Third embodiment)
FIG. 15 is a perspective view conceptually showing the arrangement of the transistor regions of the CMOS circuit according to the third embodiment of the present invention. In the CMOS circuit 30 of this embodiment, N-channel transistor regions 31N and 32N and P-channel transistor regions 31P and 32P are separated from each other in the thickness direction of the substrate. A first CMOS circuit 31 composed of an N-channel transistor region 31N and a P-channel transistor region 31P, and a second CMOS circuit 32 composed of an N-channel transistor region 32N and a P-channel transistor region 32P. The substrate is controlled in units of CMOS circuits 31 and 32. Cross marks P1 to P4 and N1 to N4 are attached to the four corners of each of the transistor regions 31N, 31P, 32N, and 32P, and are adjacent to each other by aligning and overlapping the corresponding cross marks. The transistor regions are accurately aligned and joined. The N-channel transistor region 31N and the P-channel transistor region 31P constituting the first CMOS circuit 31 are connected to each other in the regions 31N and 31P by aligning and joining the corresponding cross marks. Are precisely connected to each other. On the other hand, since the first CMOS circuit 31 exists between the N-channel transistor region 32N and the P-channel transistor region 32P constituting the second CMOS circuit 32, Japanese Patent Application Laid-Open No. 2003-92375 is disclosed. By using and forming a through hole or the like in the substrate of the first CMOS circuit 31, wiring connection between the transistor regions 32N and 32P is made.

本実施形態の構成によれば、各ＣＭＯＳ回路３１、３２におけるラッチアップの発生を防止するとともに、各ＣＭＯＳ回路３１、３２ごとに基板制御電圧を調整することができる。   According to the configuration of the present embodiment, it is possible to prevent the latch-up from occurring in each of the CMOS circuits 31 and 32, and to adjust the substrate control voltage for each of the CMOS circuits 31 and 32.

本発明は、ラッチアップの発生がないＣＭＯＳ回路等として有用である。   The present invention is useful as a CMOS circuit or the like that does not cause latch-up.

１Ａ 基板
１Ｂ 基板
２ Ｐウェル（ＰＷ）
３ Ｎウェル（ＮＷ）
５Ａ，５Ｂ 絶縁材
６Ａ，６Ｂ 第一層配線
７ 第二層配線
８ 半田ペースト層
１０ ＣＭＯＳ回路
１１ Ｎチャネルトランジスタ
１２ Ｐチャネルトランジスタ
２０ ＣＭＯＳ回路
２１ 第１のＣＭＯＳ回路
２１Ｎ Ｎチャネルトランジスタ領域
２１Ｐ Ｐチャネルトランジスタ領域
２２ 第２のＣＭＯＳ回路
３０ ＣＭＯＳ回路
３１ 第１のＣＭＯＳ回路
３１Ｎ Ｎチャネルトランジスタ領域
３１Ｐ Ｐチャネルトランジスタ領域
３２ 第２のＣＭＯＳ回路 1A Substrate 1B Substrate 2 P-well (PW)
3 N-well (NW)
5A, 5B Insulating material 6A, 6B First layer wiring 7 Second layer wiring 8 Solder paste layer 10 CMOS circuit 11 N channel transistor 12 P channel transistor 20 CMOS circuit 21 First CMOS circuit 21N N channel transistor region 21P P channel transistor Region 22 Second CMOS circuit 30 CMOS circuit 31 First CMOS circuit 31N N-channel transistor region 31P P-channel transistor region 32 Second CMOS circuit

Claims (8)

ＮチャネルトランジスタとＰチャネルトランジスタとがそれぞれ別の基板上に形成され、両基板上のトランジスタが互いに向き合わせて接続されていることを特徴とするＣＭＯＳ回路。   A CMOS circuit, wherein an N-channel transistor and a P-channel transistor are formed on different substrates, and the transistors on both substrates are connected to face each other. 請求項１に記載のＣＭＯＳ回路が複数接続されたＣＭＯＳ回路であって、
Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士が、それぞれ基板面に沿った方向に隣り合うように並べて配置されたことを特徴とするＣＭＯＳ回路。 A CMOS circuit in which a plurality of the CMOS circuits according to claim 1 are connected,
A CMOS circuit, wherein regions where N-channel transistors are formed and regions where P-channel transistors are formed are arranged side by side in a direction along the substrate surface. 請求項２に記載のＣＭＯＳ回路であって、
前記領域の周囲が絶縁材で覆われていることを特徴とするＣＭＯＳ回路。 A CMOS circuit according to claim 2, comprising:
A CMOS circuit, wherein the region is covered with an insulating material. 請求項１に記載のＣＭＯＳ回路が複数接続されたＣＭＯＳ回路であって、
Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士が、それぞれ基板の厚さ方向に分離して配置されたことを特徴とするＣＭＯＳ回路。 A CMOS circuit in which a plurality of the CMOS circuits according to claim 1 are connected,
A CMOS circuit, wherein regions where N-channel transistors are formed and regions where P-channel transistors are formed are arranged separately in the thickness direction of the substrate. ＮチャネルトランジスタとＰチャネルトランジスタとをそれぞれ別の基板上に形成し、両基板上のトランジスタを互いに向き合わせて接合することを特徴とするＣＭＯＳ回路の製造方法。   A method of manufacturing a CMOS circuit, wherein an N-channel transistor and a P-channel transistor are formed on different substrates, and the transistors on both substrates are bonded to face each other. 請求項１に記載のＣＭＯＳ回路が複数接続されたＣＭＯＳ回路の製造方法であって、
Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士を、それぞれ基板面に沿った方向に隣り合うように並べて配置することを特徴とするＣＭＯＳ回路の製造方法。 A method of manufacturing a CMOS circuit in which a plurality of the CMOS circuits according to claim 1 are connected,
A method of manufacturing a CMOS circuit, wherein regions where N channel transistors are formed and regions where P channel transistors are formed are arranged side by side in a direction along the substrate surface. 請求項６に記載のＣＭＯＳ回路の製造方法であって、
前記領域の周囲を絶縁材で覆うことを特徴とするＣＭＯＳ回路の製造方法。 A method of manufacturing a CMOS circuit according to claim 6,
A method of manufacturing a CMOS circuit, wherein the periphery of the region is covered with an insulating material. 請求項１に記載のＣＭＯＳ回路が複数接続されたＣＭＯＳ回路の製造方法であって、
Ｎチャネルトランジスタが形成されている領域同士、Ｐチャネルトランジスタが形成されている領域同士を、それぞれ基板の厚さ方向に分離して配置することを特徴とするＣＭＯＳ回路の製造方法。 A method of manufacturing a CMOS circuit in which a plurality of the CMOS circuits according to claim 1 are connected,
A method of manufacturing a CMOS circuit, wherein regions where N-channel transistors are formed and regions where P-channel transistors are formed are arranged separately in the thickness direction of the substrate.
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