JP2010245136A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device much more. <P>SOLUTION: The semiconductor device is provided with two semiconductor chips different in ground potential, an insulating substrate for loading the two semiconductor chips, and a mold insulating member which is arranged on a face side of the insulating substrate loading the semiconductor chips and performs molding to an end part of a face loading the semiconductor chips. The two semiconductor chips are disposed close to confronted sides of the insulating substrate by while being separated by 1 mm or above. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  In particular, the present invention relates to a semiconductor device mounting structure.

  As a conventional semiconductor device, a plurality of semiconductor chips and a connection terminal electrically connected to the semiconductor chip are mounted on a single insulated wiring board, and the insulated wiring board, the semiconductor chip, and the connection terminal are mounted. One having a molded member to be packaged is known. Furthermore, there is a technique in which the size of the contact area between the electrode solder and the insulated wiring board is changed according to the amount of warpage of the insulated wiring board during thermal stress (for example, Patent Document 1).

  However, further improvement of the reliability of the semiconductor device is required.

Japanese Patent Laid-Open No. 7-193162

  The problem to be solved by the present invention is to further improve the reliability of a semiconductor device.

  A semiconductor device according to the present invention is provided on two semiconductor chips having different ground potentials, an insulating substrate for mounting the two semiconductor chips, a surface side of the insulating substrate on which the semiconductor chip is mounted, and A mold insulating member for molding to the end of the surface on which the semiconductor chip is mounted, wherein the two semiconductor chips are separated from each other by 1 mm or more, and each semiconductor chip is placed on the insulating substrate. A semiconductor device disposed close to the opposite side.

  According to the present invention, the reliability of the semiconductor device can be further improved.

It is the figure which mounted the semiconductor device concerning this Embodiment on the external substrate. It is the figure by which the sheet | seat board | substrate has been arrange | positioned on the panel board | substrate concerning this Embodiment. It is the figure which mounted the semiconductor chip on the sheet | seat board | substrate concerning this Embodiment, and was molded with the mold insulation member. It is the figure which divided | segmented the semiconductor device concerning this Embodiment into the semiconductor device piece. It is a circuit diagram of a semiconductor device concerning this embodiment. It is the figure which the curvature generate | occur | produced with the heat | fever in the semiconductor device concerning this Embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. It is the graph which showed the grounds which ensure the area | region which does not arrange | position a semiconductor chip, a wiring pattern, and a wiring solid pattern 1 mm or more. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment. 1 is a structural diagram of a semiconductor device according to the present embodiment.

  The semiconductor device according to this embodiment can be applied to an MCM (Multi Chip Module) semiconductor device in which a semiconductor chip is mounted on an insulated wiring board and packaged by molding. As a representative example, a plurality of semiconductor devices are provided on an insulated wiring board. MAP (Mold Array Package) method in which the insulating wiring substrate and the plurality of semiconductor chips are collectively resin-molded and then divided into individual semiconductor device pieces, and the plurality of external terminals are spherical. A structure when assembled by a BGA (Ball Grid Array) method connected to an external substrate with solder will be described below with reference to the drawings.

  FIG. 1 is a structural diagram when the semiconductor device according to the present embodiment is mounted on an external substrate. In FIG. 1, the semiconductor device 100, the external substrate 200, the spherical solder 300, the insulating wiring substrate 400, and the mold insulating material 600 according to the present embodiment are shown, and the resistors and capacitor modules mounted on the external substrate 200 are omitted. ing.

  In the present embodiment, a plurality of spherical solders 300 arranged on the back surface of the insulated wiring board 400 are electrically connected to the external board 200, and therefore, compared with an LF (Lead Frame) type in which connector terminals are drawn from the side surface of the semiconductor device. In addition, space saving of the external substrate can be realized.

  FIG. 2 is a process diagram of the insulated wiring board 400 according to the present embodiment. The insulated wiring board 400 is cut out from the sheet substrate 404. The sheet substrate 404 is cut out from the panel substrate 405.

  3 and 4 are mounting structure diagrams of the semiconductor device according to the present embodiment. As shown in FIG. 3, the semiconductor device 100 according to the present embodiment has a plurality of semiconductor chips 500 mounted on an insulating wiring substrate 400, and the insulating wiring substrate 400 and the plurality of semiconductor chips 500 are molded and insulated. The material 600 is molded together. Thereafter, as shown in FIG. 4, since the semiconductor device is divided into 100 pieces, the tact time of the molding process can be shortened as compared with the case of molding in units of semiconductor devices. Such a manufacturing method is called a MAP (Mold Array Package) method. Note that a cut mark is formed at the ends of the insulating wiring substrate 400 and the mold insulating member of the semiconductor device 100 manufactured by the MAP method.

  However, since this MAP method resin-molds a plurality of semiconductor devices at once, the semiconductor device is warped in the cooling process after resin molding due to the difference between the linear expansion coefficient of the insulating wiring board and the linear expansion coefficient of the resin. It may occur, resulting in a drop in mountability when mounting an external substrate and a defect when transporting a semiconductor device.

  A semiconductor device manufactured by the MAP method is covered with a resin mold up to its end. That is, the semiconductor device tends to have a larger amount of resin mold than a semiconductor device manufactured by another method. Therefore, when thermal stress is applied to the semiconductor device, the semiconductor device is likely to warp due to the difference between the linear expansion coefficient of the insulating wiring substrate and the linear expansion coefficient of the resin. As a result, there is a risk that the connection terminal portion that electrically connects the semiconductor device and the external substrate or the electrical wiring inside the semiconductor device may be disconnected.

  On the other hand, if the area of the insulated wiring board is reduced in order to suppress the warp of the semiconductor device described above, when there are a plurality of circuits having different ground potentials on the insulated wiring board, a high withstand voltage is generated between the circuits. It becomes difficult to realize. Therefore, it is required to rationalize the production process of the semiconductor device, to suppress the warpage of the semiconductor device, and to simultaneously integrate a plurality of circuits having different ground potentials in the same semiconductor device.

  FIG. 5 is a circuit block diagram of the semiconductor device according to the present embodiment. The semiconductor device 100 according to the present embodiment communicates signals between a high potential side circuit 502 and a low potential side circuit 503 having different ground potentials, and signals between the high potential side circuit 502 and the low potential side circuit 503. The signal communication circuit 504 is configured. That is, the semiconductor device according to the present embodiment is configured to mount the high-potential side circuit 502 and the low-potential side circuit 503 having different ground potentials on the insulating wiring board 400, so that each insulation is ensured. Is a problem.

  FIG. 6 is a diagram illustrating a state in which the semiconductor device 100 is warped. In the cooling process after the resin mold forming when packaging with the mold insulating material 600, the semiconductor device 100 is warped due to the difference in the linear expansion coefficient between the insulating substrate 400 and the mold insulating material 600. There is a possibility that it may lead to a decrease in mountability and a defect during transportation of the semiconductor device.

  Further, due to the difference in coefficient of linear expansion between the insulating substrate 400 and the mold insulating material 600, the semiconductor device 100 is warped when a thermal stress is applied and when it is cooled, that is, when a thermal cycle is generated. There is a risk that the connection terminal portion for electrically connecting the two and the electric wiring inside the semiconductor device may be disconnected.

  Further, if the area of the insulating wiring substrate 400 of the semiconductor device 100 is reduced in order to suppress the warp of the semiconductor device 100, a sufficient space between the semiconductor devices cannot be secured due to layout restrictions, and the grounding in the semiconductor device is not possible. In a semiconductor device having circuits with different potentials, it is difficult to achieve a high breakdown voltage.

  FIG. 7A is a top view of the semiconductor device according to this embodiment, FIG. 7B is a side view, and FIG. 7C is a rear view. The semiconductor device 100 includes a spherical solder 300 that electrically connects the semiconductor device 100 to an external substrate, an insulated wiring substrate 400, a wiring pattern 401 in which an electrical conductor is wired inside the insulated wiring substrate 400, and the influence of noise and the like. In order to suppress the above, a wiring solid pattern 402 in which electrical conductors are spread over a wide area inside the insulated wiring board 400, the semiconductor chip 500 joined on the insulated wiring board 400 with an electrical joining material such as silver paste, A wire 501 and a mold insulating material 600 for electrically connecting the insulating wiring substrate 400 and the semiconductor chip 500 are provided. The insulated wiring board 400 has a region 1000 where the semiconductor chip 400, the wiring pattern 401, and the wiring solid pattern 402 are not mounted. The region is provided so as to be separated from the semiconductor chip 500 having a different potential by 1 mm or more.

  FIG. 8 is a graph showing the correlation between the amount of warpage of the semiconductor device and the spacing between the regions where the semiconductor chip, the wiring pattern 401, and the wiring solid pattern 402 are not arranged in a temperature 250 ° C. environment in the process of attaching the semiconductor device to the external substrate. . The abscissa indicates the interval between the regions where the semiconductor chip, the wiring pattern, and the wiring solid pattern are not disposed, and the ordinate indicates the amount of warping of the semiconductor device 100. As an example, when the warp amount of the semiconductor device needs to be 0.6 mm or less due to the restriction of the size of the spherical solder 300 that connects the semiconductor device 100 to the external substrate, the semiconductor chip, the wiring pattern, and the wiring solid It is necessary to secure 1 mm or more area where the pattern is not mounted. Here, the insulating wiring substrate 400 is made of glass base epoxy resin, the wiring pattern 401 and the wiring solid pattern 402 are made of copper, the semiconductor chip 500 is made of silicon, and the mold insulating material 600 is made of epoxy resin.

  When the difference in linear expansion coefficient between the insulating wiring substrate 400 and the mold insulating material 600 is reduced by changing the material, the area where the semiconductor chip, the wiring pattern, and the wiring solid pattern are not mounted can be made smaller than 1 mm. When the difference in linear expansion coefficient between the insulating wiring substrate 400 and the mold insulating material 600 is increased by changing the material, the area where the semiconductor chip, the wiring pattern, and the wiring solid pattern are not mounted must be larger than 1 mm. For example, when the linear expansion coefficient is reduced by using the insulating wiring substrate 400 as a ceramic base material, the linear expansion coefficient is reduced by adding a stress relaxation material to the epoxy resin of the mold insulating material 600.

  In addition, there is a concern that the semiconductor device 400 may exceed the allowable value of warpage due to a mixture of defects in the insulating wiring board 400, a large linear expansion coefficient, or warping from the initial state. That is, in the case where the semiconductor device 100 is manufactured by the MAP method in FIG. 3, there is a high possibility that the semiconductor device 100 around the defective semiconductor device 100 also has a defect. For this reason, in order to make it easy to apply feedback to the manufacturing process of the insulating wiring board 400, the insulating wiring board 400 removes the resist on the surface on which the spherical solder 300 is mounted, as shown in FIG. In this pattern, the position information of the sheet substrate 404 from which the insulated wiring board 400 is cut out and the position information of the sheet substrate 404 from the panel substrate 405 from which the sheet substrate 404 is cut out are printed with alphabets 301 and numbers 302. .

  FIG. 9A is a top view of the semiconductor device 100 according to this embodiment, and FIG. 9B is a side view. Since the semiconductor chip 500 having a linear expansion coefficient smaller than the linear expansion coefficient of the insulating wiring substrate 400 and the mold insulating material 600 is mounted across the region 1000 where the semiconductor chip 500 having a width of 1 mm or more is not mounted, it is affected by stress. Suppress warpage deformation. That is, since the semiconductor chip 500 whose linear expansion coefficient is closer to the insulating wiring substrate 400 than the mold insulating material 600 is disposed near the end of the semiconductor device 100 where warpage is likely to occur, the warpage from the end of the semiconductor device 100 is performed. Can be suppressed.

  In addition, when a circuit having a different ground potential is provided across the region 1000 on which the semiconductor chip 500 having a width of 1 mm or more is not mounted, a highly reliable semiconductor device with less risk of malfunction due to leakage current or noise can be realized. .

  FIG. 10A is a top view of the inner layer of the insulating substrate of the semiconductor device 100 according to this embodiment, and FIG. 10B is a side view. The wiring pattern 401 having a smaller linear expansion coefficient than the linear expansion coefficient of the insulating wiring substrate 400 and the mold insulating material 600 is configured not to provide the wiring pattern 401 in the region 1000 described above, and suppresses warping of the semiconductor device 100.

  In addition, in the case where circuits having different ground potentials are provided across a region 1000 having at least a width of 1 mm or less without a wiring pattern 401, a highly reliable semiconductor device with less risk of malfunction due to leakage current or noise can be realized.

  FIG. 11A is a top view of an insulating substrate inner layer of the semiconductor device 100 according to the present embodiment, and FIG. 11B is a side view. The wiring solid pattern 402 having a smaller linear expansion coefficient than the linear expansion coefficient of the insulating wiring substrate 400 and the mold insulating material 600 is configured not to provide the wiring solid pattern 402 in the region 1000 described above, and warping of the semiconductor device 100 is prevented. Suppress.

  Further, in the case where circuits having different ground potentials are provided across a region 1000 having no wiring solid pattern 402 having a width of 1 mm or more, a highly reliable semiconductor device with less risk of malfunction due to leakage current or noise can be realized.

  12A is a cross-sectional view of the semiconductor device 100 according to the present embodiment, and FIG. 12B is a rear view. In the present embodiment, the insulated wiring board 400 includes the position information from the sheet substrate 404 from which the insulated wiring board 400 is cut out in a pattern in which the resist is removed on the surface on which the spherical solder 300 is mounted, and the sheet board 404. The position information of the sheet substrate taken from the panel substrate 405 to be cut out is printed with alphabets 301 and numbers 302.

  As a result, when a defect such as a large amount of warpage of the insulating wiring substrate 400 or a low insulating performance of the insulating wiring substrate 400 occurs, it becomes easy to provide feedback to the manufacturing process of the insulating substrate, and the quality of the semiconductor device Improvement can be realized.

  Next, a semiconductor device 100 according to another embodiment will be described with reference to FIG.

  In the present embodiment, the insulated wiring board 400 has a conductor wiring pattern on the surface on which the spherical solder 300 is mounted, and the position information from the sheet board 404 that cuts out the insulated wiring board 400 and the panel board 405 that cuts out the sheet board 404. Information on the position of the sheet substrate 404 is printed with alphabets 303 and numbers 304.

  Since the information on the position where the sheet substrate 404 is taken from the panel substrate 405 and the information on the position where the insulated wiring substrate 400 is taken from the sheet substrate 404 are described, the amount of warping of the insulated wiring substrate 400 is large, or the insulated wiring substrate When a defect such as the low insulation performance of 400 occurs, it becomes easy to provide feedback to the manufacturing process of the insulated wiring board 400, and the quality of the semiconductor device can be improved.

  Further, a semiconductor device 100 according to another embodiment will be described with reference to FIG. 14 (a) cross-sectional view and (b) rear view.

  In this embodiment, the insulated wiring board 400 has a silk print pattern on the surface on which the spherical solder 300 is mounted, and information on the position taken from the sheet board 404 from which the insulated wiring board 400 is cut out, and the panel board from which the sheet board 404 is cut out. The position information of the sheet substrate 404 from 405 is printed with alphabets 305 and numbers 306.

  Since the information on the position where the sheet substrate 404 is taken from the panel substrate 405 and the information on the position where the insulated wiring substrate 400 is taken from the sheet substrate 404 are described, the amount of warping of the insulated wiring substrate 400 is large, or the insulated wiring substrate When a defect such as the low insulation performance of 400 occurs, it becomes easy to provide feedback to the manufacturing process of the insulated wiring board 400, and the quality of the semiconductor device can be improved.

  Further, a semiconductor device 100 according to another embodiment will be described with reference to FIG. 15A, a top perspective view, and FIG.

  In the present embodiment, the insulated wiring board 400 is provided on the surface on which the semiconductor chip 500 is mounted, the position information from the sheet board 404 that cuts out the insulated wiring board 400, and the sheet board from the panel board 405 that cuts out the sheet board 404. The position information 404 is printed with alphabets 307 and numerals 308 and can be read from the upper surface of the resin mold 600 by X-ray image recognition.

  Since the information on the position where the sheet substrate 404 is taken from the panel substrate 405 and the information on the position where the insulated wiring substrate 400 is taken from the sheet substrate 404 are described, the amount of warping of the insulated wiring substrate 400 is large, or the insulated wiring substrate When a defect such as the low insulation performance of 400 occurs, it becomes easy to provide feedback to the manufacturing process of the insulated wiring board 400, and the quality of the semiconductor device can be improved.

100 Semiconductor Device 200 External Substrate 300 Spherical Solder 301 Alphabet Printing with Resist Removal Pattern 302 Numeric Printing with Resist Removal Pattern 303 Alphabet Printing with Conductor Pattern 304 Numeric Printing with Conductor Pattern 305 Alphabet Printing with Silk Printing Pattern 306 Numeric Printing with Silk Printing Pattern 307 Alphabet printing by X-ray image recognition 308 Numeric printing by X-ray image recognition 400 Insulated wiring board 401 Wiring pattern 402 Wiring solid pattern 404 Sheet board 405 Panel board 500 Semiconductor chip 501 Wire 502 High potential side circuit 503 Low potential side circuit 504 Level Shift circuit 600 Mold insulating material 1000 Area for insulating circuits having different ground potentials

Claims (9)

Two semiconductor chips with different ground potentials,
An insulating substrate for mounting the two semiconductor chips;
A connection terminal portion disposed on the insulating substrate opposite to the surface on which the semiconductor chip is mounted and electrically connected to the semiconductor chip;
A mold insulating member provided on the surface side of the insulating substrate on which the semiconductor chip is mounted and for molding up to an end of the surface on which the semiconductor chip is mounted;
One semiconductor chip of the two semiconductor chips is disposed close to a predetermined side of the insulating substrate,
The semiconductor device in which the other semiconductor chip of the two semiconductor chips is arranged at a distance of 1 mm or more from the one semiconductor chip and close to one side facing the predetermined one side of the insulating substrate. The semiconductor device according to claim 1,
The semiconductor device is manufactured by a mold array package method. The semiconductor device according to claim 1,
A semiconductor device in which cut surfaces are formed at end portions of the insulating substrate and the mold insulating member. The semiconductor device according to claim 1,
A wiring pattern embedded in the insulating substrate and electrically connecting the semiconductor chip and the connection terminal portion;
The semiconductor device in which the wiring pattern is wired avoiding the inside of the insulating substrate formed between the one semiconductor chip and the other semiconductor chip. 5. The semiconductor device according to claim 1, wherein:
The external connection terminal is formed of spherical solder and is a semiconductor device formed on the insulating substrate side. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device in which the one semiconductor chip and the other semiconductor chip are electrically connected in series. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device is characterized in that first insulating position information from a sheet substrate from which the insulating substrate is cut out and second taking position information of the sheet substrate from a panel substrate from which the sheet substrate is cut out are printed on the insulating substrate. . The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein the first removal position information and the second removal position information are printed by any one of a resist removal pattern, a conductor pattern, and a silk pattern. The semiconductor device according to claim 7,
The semiconductor device in which the first taking position information and the second taking position information are printed on the surface on which the connection terminal portion is arranged.

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