JP2010238278A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device including a plurality of OTPs, and a function of a pseudo MTP having an access speed improved. <P>SOLUTION: The nonvolatile semiconductor memory device 100s includes a storage area 132s, a select decoder 131s, and a select address processing part 12s. The storage area 132s includes m+1 storage elements of an n bit width (n>1). The select decoder 131a selects one of other m storage elements according to a select address stored in one of the storage elements in the storage area 132s. The select address processing unit 12s updates the select addresses when wiring data in the storage area 132s, and outputs the updated select addresses to the select decoder 131s. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory device using a one-time programmable (OTP) nonvolatile memory element.

  Nonvolatile memories represented by EPROM (Electrically Programmable Read Only Memory) have been used for many purposes because information does not disappear even when the power is turned off. For example, a typical use of EPROM is used as a replacement for a mask ROM in a medium capacity mask ROM microcomputer. EPROM is erasable with UV light and can be rewritten multiple times. However, since a package using transparent glass is expensive, it can be sealed in an inexpensive plastic package and cannot be erased. OTP (One Time Programmable ROM) has become widespread. Furthermore, in recent years, there has been an increasing demand for embedded type so-called embedded logic memories in which a nonvolatile memory is incorporated in a part of a system LSI or logic IC. In particular, an OTP that requires only one writing does not require an erasing circuit for erasing written data, and only a writing circuit and a reading circuit are sufficient, and the circuit configuration can be simplified. Manufacturing costs can be reduced compared to Time Programmable ROM). In addition, demand for OTP is increasing because the mounting area can be reduced.

  By the way, a small-sized non-volatile memory of about several hundred bits to several kilobits is also required as an adjustment switch for tuning a high-precision analog circuit incorporated in an analog circuit. In applications, the demand for MTP (Multi Time Programmable ROM) capable of rewriting data multiple times is increasing. In response to such demand, there is a technique for configuring a pseudo MTP using a configuration including a plurality of OTPs (Patent Document 1).

JP 2006-323981 A

  However, in the technique described in Patent Document 1, in order to determine which data among a plurality of OTPs included in a memory device that is a pseudo MTP should be read, and when writing new data, In order to determine which of the OTPs should be written with data, it is necessary to read information indicating writing stored in each of the plurality of OTPs. Therefore, in order to perform the above-described determination, it takes time to read information indicating writing stored in each of the plurality of OTPs, and there is a problem that the access speed cannot be increased.

  The present invention has been made to solve the above problem, and an object of the present invention is to provide a nonvolatile semiconductor memory device having a plurality of OTPs and having a pseudo-MTP function with improved access speed.

  (1) In order to solve the above problem, the present invention provides a storage area including n + 1 (m> 1, n ≧ m) n storage element groups storing n-bit width (n> 1) data. A select decoder that selects any one of the other m memory element groups according to a select address stored in any one of the memory element groups in the storage area; and a select address processing unit that updates the select address and outputs the updated select address to the select decoder when data is written to any one of the m memory element groups. A nonvolatile semiconductor memory device.

  (2) Further, according to the present invention, in the above-described invention, each of m bits in the n bits of the storage element group storing the select address is written by the other m storage element groups. It is characterized by being associated with whether or not it has been made.

  (3) Further, the present invention is the above-described invention, wherein each of the n 1-bit width memory elements constituting the n-bit width storage element group is formed on a p-type semiconductor substrate. A first n-type diffusion layer that forms a drain, a channel region, and a second n-type diffusion layer that forms a source are arranged in series in this order, and the first n-type diffusion layer A first metal wiring connected to the mold diffusion layer via a contact, and connected to the second n-type diffusion layer via a contact in a horizontal direction perpendicular to the series direction. A second metal wiring disposed, an n-type well disposed at a constant interval in the horizontal direction with respect to the transistor formation region, a third n-type diffusion layer formed on the n-type well, Above the n-type well The fourth n-type diffusion layer to be formed, the third n-type diffusion layer, and the fourth n-type diffusion layer are connected to each other through contacts, and the control gates arranged in the horizontal direction are formed. And a third metal wiring, and a polysilicon arranged in parallel with the third metal wiring and covering the n-type well and a part of the channel region.

  (4) According to the present invention, in the above-described invention, when data is written to the memory element, a first voltage is applied to the drain, and a second voltage higher than the first voltage is applied to the control gate. And a ground potential is applied to the source, thereby forming a depletion layer near the drain and generating hot electrons, and injecting the hot electrons into the polysilicon forming the floating gate to set a threshold voltage. When data is read out from the memory element, the third voltage is applied to the drain, the control gate is lower than the third voltage, and the threshold value of the initial state before writing the memory element is changed. Whether a high voltage is applied, a ground potential is applied to the source, and current flows between the drain and the source Wherein the read data by.

  (5) Further, according to the present invention, in the invention described in the above, the memory area has the memory elements arranged in a matrix, and each of the arranged memory elements has a memory element adjacent to the row direction. The memory element adjacent to the column direction and the memory element adjacent to the column direction and the memory element adjacent to the row direction and the fourth n-type diffusion layer The memory elements shared and arranged in the same row direction share the second metal wiring and the third metal wiring, and the memory elements arranged in the same column direction One metal wiring is shared.

  (6) Further, the present invention includes a storage area including n + 1 (m> 1, n ≧ m) n storage element groups storing n (n> 1) bit width data, and the storage area includes A select address processing unit that reads out and stores a select address stored in one of the m + 1 storage element groups via the sense amplifier unit, and the select address input from the select address processing unit And a select decoder that selects one of the m + 1 storage element groups included in the storage area, and n bits output by the storage element group selected by the select decoder A sense amplifier that amplifies the width data and outputs the amplified data to the input / output terminal via the data input / output unit; and n-type input from the input / output terminal via the data input / output unit. A write amplifier unit that amplifies the n-bit width data and writes and stores the amplified n-bit width data in the storage element group selected by the select decoder; and when a read command is input from the outside, Control to output n-bit width data stored in one storage element group of the included m + 1 storage element groups from an input / output terminal via the sense amplifier and the data input / output unit; When a write command is input from the outside, the m + 1 storage element groups included in the storage area include n-bit width data input from the input / output terminal via the data input / output unit and the write amplifier unit. And an access control unit that performs control to be stored in one of the memory element groups.

  (7) Further, in the present invention described above, when the write command is input from the outside, the access control unit is configured to select the select address stored in the select address processing unit. N bits output from the input / output terminal via the data input / output unit and the write amplifier unit, and output to the decoder, causing the select decoder to select one storage element group according to the output select address Control is performed to output and store the width data to the storage element group selected by the select decoder, and then the access control unit stores the select address in the select address processing unit. A signal for selecting a storage element group is output to the select decoder, and the updated select address is stored in the memory. The device group is controlled to output the select address updated via the write amplifier unit and stored in the memory device group. Further, the access control unit stores the select address in the select address processing unit. A signal for selecting the storage element group is output to a select decoder, and the select address stored in the storage element group is read and stored via the sense amplifier, and the read command is externally transmitted. Is input, the access control unit outputs the select address stored in the select address processing unit to the select decoder, and stores the one select memory in the select decoder according to the output select address. Select an element group, and store n-bit width data stored in the selected storage element group. Via the sense amplifier portion and the data input-output unit out look, characterized in that the control output to the input and output terminals.

  (8) Further, in the present invention described above, the select address processing unit includes a counter that encodes and stores the select address. When the select address is updated, the counter stores And the select decoder decodes the value output by the counter of the select address processing unit and selects only one of the selection signals corresponding to each of the m memory element groups. And a decoder that outputs a selection signal for selecting the storage element group when a signal for selecting the storage element group for storing the selection address is input from the select address processing unit.

  (9) In the present invention described above, the select address processing unit includes a shift register that stores the select address, and the shift register stores the select address when the select address is updated. The select decoder shifts in the value and shifts in 1. The select decoder detects a boundary between the values 0 and 1 output from the shift register of the select address processing unit, and each of the m memory element groups is detected. A decoder for outputting a corresponding selection signal and outputting a selection signal for selecting the storage element group when a signal for selecting the storage element group for storing the selection address is input from the select address processing unit; It is characterized by.

  (10) Further, according to the present invention, there are provided a storage area including n + 1 (m> 1, n ≧ m) n storage element groups storing n (n> 1) bit width data, and the m + 1 storages. K (k> 1) storage block units each including a select decoder that decodes a select address for selecting one of the m storage element groups excluding one storage element group of the element groups; A row decoder that decodes a row address input from the outside and selects one of the k storage block units, and a row decoder selected from the k storage block units by the row decoder A sense amplifier unit that amplifies n-bit width data read from one of the m + 1 storage element groups included in the storage block unit and outputs the amplified data to a data input / output unit; and the data input unit Output section A write amplifier unit that amplifies the n-bit width data input from the row decoder and writes and stores the data in one storage element group among the m + 1 storage element groups included in the storage block unit selected by the row decoder; , Storing the select address corresponding to each of the k storage block units, and updating the corresponding select address when the k storage block units newly store n-bit width data. The select address processing unit that outputs the selected address to the select decoder of the storage block unit, and when a read command and the row address are input from the outside, the input row address is output to the row decoder. And outputting the select address stored in the select address processing unit, by the select decoder. The n-bit width data read from the selected storage element group is controlled to be output from the input / output terminal via the sense amplifier section and the data input / output section, and a write command, the row address, Is input to the select decoder included in the storage area selected by the row decoder via the data input / output unit and the write amplifier unit. And an access control unit that performs control to be stored in the selected memory element group.

  (11) Further, according to the present invention, a storage element is provided at each intersection of i sense amplifiers provided for each i (i> 1) data lines, a plurality of selection signal lines, and a plurality of bit lines. A memory cell array including i memory blocks which are arranged in a matrix with a direction and a column direction, and the storage elements are associated with the i data lines and divided in the column direction, and the memory cell array A select address processing unit that reads and stores a select address stored in a part of the memory, a plurality of bit lines of each of the i memory blocks, and a data line corresponding to each of the i memory blocks A plurality of switch elements for switching connection and one of the plurality of selection signal lines according to a select address stored in the select address processing unit A select decoder for activating a selection signal line; a plurality of column decoders for switching on / off of the plurality of switch elements in accordance with a select address stored in the select address processing unit; and the memory input from outside A data input conversion circuit for applying a voltage to the i data lines in accordance with data to be written in the cell array. Each of the storage elements comprises a transistor having a floating gate formed on a semiconductor substrate. The nonvolatile semiconductor memory device is characterized in that it is connected to the selection signal line, a drain is connected to the bit line, and a source is commonly connected to an erase control circuit.

  (12) Further, according to the present invention, a storage element is provided at each intersection of i sense amplifiers provided for each i (i> 1) data lines, a plurality of selection signal lines, and a plurality of bit lines. The memory elements are arranged in a matrix of directions and column directions, and the storage elements are divided into i pieces in the column direction for each of the i data lines, and each of them is k (k> 1) in the row direction. A memory cell array composed of i × k memory blocks divided into pieces, a select address processing unit for reading and storing a select address stored in a part of the memory cell array, and each of the i data lines A plurality of switch elements for switching connection of the memory blocks divided in the column direction corresponding to the data lines with the plurality of bit lines, and i memory blocks divided in the row direction. Provided in each memory block group consisting of: k select decoders for activating one select signal line among the plurality of select signal lines corresponding to the memory block group; and the select address processing unit storing the select signal lines. A plurality of column decoders for switching on / off of the plurality of switch elements according to the selected select address, and the k select decoders, and the k number of the decoder elements according to a row address inputted from the outside. A plurality of row decoders for selecting and operating one select decoder among the select decoders, and a data input conversion circuit for applying a voltage to the i data lines in accordance with data written to the memory cell array inputted from the outside Each of the storage elements includes a floating gate formed on a semiconductor substrate. A nonvolatile semiconductor memory device comprising: a transistor; a control gate connected to the selection signal line; a drain connected to the bit line; and a source commonly connected to an erase control circuit.

  (13) According to the present invention, in the invention described above, a first voltage is applied to a drain of the transistor that is the memory element, and a second voltage higher than the first voltage is applied to a control gate of the transistor. A write operation is performed by applying a voltage and setting the source of the transistor to the ground potential, and applying a fourth voltage higher than the second voltage to the drain of the transistor, and grounding the control gate of the transistor An erase operation is performed by setting the potential of the transistor open or applying a voltage higher than the ground potential and lower than the first voltage, and applying the ground potential or the fourth voltage to the drain of the transistor. Apply a ground potential or a third voltage to the control gate of the transistor, and ground the source of the transistor The first voltage is applied to the drain of the transistor, the ground potential is applied to the source of the transistor, and the voltage to be applied to the control gate of the transistor is preliminarily determined from the third voltage. The writing back operation is performed by gradually increasing the potential to a predetermined potential.

  (14) Further, in the invention described above, the erasing operation may be performed after performing a test to confirm that the threshold value exceeds a predetermined writing reference value by performing a writing operation on the memory element. At least once to verify whether or not the threshold value of the transistor as the storage element has been changed to an initial threshold value or less, and rewrite when the threshold value of the transistor is lower than a predetermined criterion value The operation is performed at least once, the operation of the memory element is verified by checking whether the threshold is equal to or lower than the initial threshold and equal to or higher than the determination reference value, and the erase operation is performed a predetermined number of times. If the threshold value of the transistor does not fall below the initial threshold value, it is determined that the memory element is defective, and even if the write-back operation is performed a predetermined number of times, the When the threshold value of the register is not said criterion above, characterized by determining said storage element defective.

  (15) Further, the present invention is characterized in that, in the above-described invention, the erase control circuit applies only a ground potential to the commonly connected sources of the plurality of storage elements.

  According to the present invention, the select address is stored in the storage element (OTP) included in the storage area, and the select decoder selects the storage element (OTP) corresponding to the select address, so that the OTP storing the select address is stored once. By reading the data, it is possible to detect the memory element that last stored the data. In addition, since the select address is updated when data is written, it is possible to detect the memory element to which data was last written. As a result, in data reading and data writing, the number of accesses can be reduced without sequentially reading the memory elements included in the storage area in order to detect the memory element in which the data has been written last. Can be improved.

1 is a schematic block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a first embodiment. 3 is a circuit diagram showing a configuration example of a select decoder and a select address processing unit in the same embodiment. FIG. It is a table | surface which shows the relationship of data D <7: 0>, A <2: 0>, and SEL <7: 0> in the embodiment. It is a circuit diagram which shows the structure of the select address process part and select decoder in 2nd Embodiment. It is a schematic block diagram which shows the structure of the non-volatile semiconductor memory device of 3rd Embodiment. It is a block diagram of the memory element used for an OTP array. It is a block diagram of the memory element used for an OTP array. It is a table which shows the operation | movement table | surface of a memory element. It is a graph which shows the change of the characteristic by each operation | movement of writing, erasing, and writing back of a memory element. It is a graph which shows the characteristic of weak writing of a memory element. It is a figure which shows the equivalent circuit of the coupling type | system | group of a memory element. It is the schematic which shows the structural example of the non-volatile semiconductor memory device of 1st Embodiment shown in FIG. 1 as OTP which has a matrix array (memory array) using the memory element in 4th Embodiment. FIG. 6 is a schematic block diagram showing a configuration of the nonvolatile semiconductor memory device of the third embodiment shown in FIG. 5 as an MTP having a matrix array (memory array) using memory elements in the fifth embodiment. It is a schematic block diagram which shows the structure of the non-volatile semiconductor memory device in 6th Embodiment. It is a schematic block diagram which shows the structure of the non-volatile semiconductor memory device in 7th Embodiment. It is the layout figure which showed the structural example of the memory block by the memory element in 8th Embodiment. It is a flowchart of the verification sequence which the non-volatile semiconductor memory device performs with respect to the erase operation and write-back operation of the memory element which the non-volatile semiconductor memory device in 9th Embodiment has. It is a flowchart of the verification sequence which the non-volatile semiconductor memory device performs with respect to the erase operation and write-back operation of the memory element which the non-volatile semiconductor memory device in 9th Embodiment has.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic block diagram showing the configuration of the nonvolatile semiconductor memory device 100s in the first embodiment. The non-volatile semiconductor memory device 100s includes an access control unit 11s, a select address processing unit 12s, an MTP block unit 13s, a write amplifier unit 14s, a sense amplifier unit 15s, a data input / output unit 16s, and an input / output terminal 17s.
The access control unit 11 s selects a select address processing unit 12 s, a write amplifier unit 14 s, a sense amplifier unit 15 s, and a data according to an externally input data read command and an externally input data write command. The operation order of each input / output unit 16s is controlled.

The select address processing unit 12s stores the select address read from the MTP block unit 13s, and outputs the stored select address to the MTP block unit 13s according to the information indicating the read operation output from the access control unit 11s. At the same time, the select address is updated according to the information indicating the write operation output from the access control unit 11s, and the updated select address is output to the MTP block unit 13s.
The MTP block unit 13s stores m + 1 (m> 1, n ≧ m) OTP arrays (storage element group) 133s-1 that store data of n-bit width (n is an integer satisfying n> 1). ,..., 133s- (m + 1) includes a data storage unit (storage area) 132s and a select decoder 131s. Here, m + 1 OTP arrays 133s-1,..., 133s- (m + 1) have the same configuration, and when one or all of them are shown as representatives, they are referred to as OTP arrays 133s.

  The OTP array 133s- (m + 1) is used to determine a select address that is information indicating the usage state of the MTP block unit 13s, that is, which OTP array 133s has already been written with data. Store information. Here, the OTP array 133s- (m + 1) is called a use state register, can store n-bit width data, and each bit corresponds to the OTP array 133s-1, ..., OTP array 133s-m. When the bit of data stored in the OTP array 133s- (m + 1) is “0”, the OTP array 133s corresponding to the bit indicates that data is not written, and the OTP array 133s- (m + 1) When the bit of the stored data is “1”, the OTP array 133s corresponding to the bit indicates that data has already been written.

Here, in the initial state, that is, in the state where data is not yet written in the nonvolatile semiconductor memory device 100s, the OTP array 133s- (m + 1) is “0”, and the OTP array 133s- (m + 1) As data is written in the order of 133 s-m, “1” is written in order from the first bit. For example, when the data stored in the OTP array 133s- (m + 1) is “1” from the first bit (bit 0) to the eighth bit (bit 7) and the ninth bit and subsequent bits are “0”, the OTP array Data from 133s-1 to the OTP array 133s-8 has already been written, and the last written data is data stored in the OTP array 133s-8.
Further, when all m bits of the n bits of the OTP array 133s- (m + 1) are “1”, the non-volatile semiconductor memory device 100s has no OTP array 133s for storing new data, and new data Indicates that it cannot be stored.

The select decoder 131s decodes the data indicating the usage state output from the select address processing unit 12s, and any one of the OTP arrays 133s-1,..., 133s- (m + 1) included in the data storage unit 132s. Select.
The OTP array 133s outputs n-bit width data to be stored to the sense amplifier unit 15s during a read operation, and reads and stores data output from the write amplifier unit 14s during a write operation.

  When the access control unit 11s outputs information indicating the write operation, the write amplifier unit 14s outputs the data output from the select address processing unit 12s or the data input / output unit 16s to the OTP array 133s of the MTP block unit 13s. When the access control unit 11s outputs information indicating a read operation, the sense amplifier unit 15s reads, amplifies, and outputs the data output from the OTP array 133s of the MTP block unit 13s to the data input / output unit 16s. When the access control unit 11s outputs information indicating a write operation, the data input / output unit 16s reads data input from the outside via the data input / output terminal 17s, and outputs the read data to the write amplifier unit 14s. When the access control unit 11s outputs information indicating a read operation, the data output by the sense amplifier unit 15s is read, and the read data is output to the outside through the input / output terminal 17s.

  Next, the operation of the nonvolatile semiconductor memory device 100s will be described.

(Initialization operation at the start of power supply)
First, when the supply of power to the nonvolatile semiconductor memory device 100s is started, the access control unit 11s reads the select address stored in the OTP array 133s- (m + 1) into the select address processing unit 12s. Control is performed so that the select address for selecting the OTP array 133s- (m + 1) is output to 131s- (m + 1) in the select decoder 131s in 12s. The access control unit 11s controls the sense amplifier unit 15s to read and output data output from the OTP array 133s- (m + 1) of the data storage unit 132s, and the select address processing unit 12s controls the sense amplifier unit 15s. Control to read and store data output from.

  The select decoder 131s decodes the address output by the select address processing unit 12s and outputs a read signal for selecting the OTP array 133s- (m + 1) to the OTP array 133s- (m + 1) of the data storage unit 132s. The OTP array 133s- (m + 1) outputs the stored data to the sense amplifier unit 15s in accordance with the read signal output from the select decoder 131s. The sense amplifier unit 15s reads the data output from the OTP array 133s- (m + 1), amplifies the read data, and outputs the amplified data to the select address processing unit 12s. The select address processing unit 12s stores the data output from the sense amplifier unit 15s. Here, the read signal is a signal indicating that any one of the OTP arrays 133s is selected and the data stored in the OTP array 133s is output.

  Through the above-described operation, the select address processing unit 12s stores, in the select address, information indicating the OTP array 133s in which data is written last in the OTP array 133s. With this operation, the select address processing unit 12s stores the select address, and the initialization operation is completed.

(Data write operation)
Next, a write operation for storing data in the nonvolatile semiconductor memory device 100s will be described.
First, in the nonvolatile semiconductor memory device 100 s, when a data write command is input from the outside, the access control unit 11 s stores the new data from the select address stored in the select address processing unit 12 s. A select address indicating 133s is generated and output to the select decoder 131s. The select decoder 131s decodes the select address output from the select address processing unit 12s and outputs a write signal to one OTP array 133s among the OTP arrays 133s-1, ..., 133s-m included in the data storage unit 132s. To do.

The OTP array 133s to which the write signal is input from the select decoder 131s reads and stores the data output from the write amplifier unit 14s. Here, the data output from the write amplifier unit 14s is n-bit width data input from the outside via the input / output terminal 17s and the data input / output unit 16s. Here, the write signal is a signal indicating that any one of the OTP arrays 133s is selected, and that the OTP array 133s reads and stores data output from the write amplifier unit 14s.
Through the above-described operation, data input from the outside is stored in the OTP array 133s. Subsequently, the access control unit 11s performs control to cause the select address processing unit 12s to output the updated select address to the write amplifier unit 14s and to store the updated select address in the OTP array 133s.

  When the operation for storing data input from the outside in the OTP array 133s is completed, the access control unit 11s outputs a select address for selecting the OTP array 133s- (m + 1) and performs select address processing. The unit 12s performs control to output the updated select address to the write amplifier unit 14s. In addition, the access control unit 11s performs control to output the select address input to the write amplifier unit 14s to the OTP array 133s.

  When the select address for selecting the OTP array 133s- (m + 1) output from the select address processing unit 12s is input, the select decoder 131s outputs a write signal to the OTP array 133s- (m + 1). When a write signal is input from the select decoder 131s, the OTP array 133s- (m + 1) reads and stores the updated select address output from the write amplifier unit 14s as data. As a result, the select address stored in the OTP array 133s- (m + 1) is updated.

Subsequently, the information indicating the use state of the nonvolatile semiconductor memory device 100s stored in the select address processing unit 12s is updated.
The access control unit 11s causes the select decoder 131s to output a select address for selecting the OTP array 133s- (m + 1) so that the select address processing unit 12s reads out the select address stored in the OTP array 133s- (m + 1). Take control. In addition, the access control unit 11s performs control so that the sense amplifier unit 15s reads data output from the OTP array 133s and outputs the data to the select address processing unit 12s.

  When the select address is input from the select address processing unit 12s, the select decoder 131s decodes the input select address and outputs a read signal to the OTP array 133s- (m + 1). When the read signal is input from the select decoder 131s, the OTP array 133s- (m + 1) outputs the stored data to the sense amplifier unit 15s. The sense amplifier unit 15s amplifies the data output from the OTP array 133s- (m + 1), and outputs the amplified data to the select address processing unit 12s. The select address processing unit 12s reads and stores the data output from the sense amplifier unit 15s, that is, the select address stored in the OTP array 133s- (m + 1).

As described above, the nonvolatile semiconductor memory device 100s includes a process for storing data input from the outside in the OTP array 133s, a process for updating the select address stored in the OTP array 133s- (m + 1), and the select The data write operation is performed by updating the select address stored in the address processing unit 12s and performing three processes of synchronizing with the select address stored in the OTP array 133s- (m + 1).
When there is no OTP array 133s for writing data, that is, when data has already been written to all the OPT arrays 133s-1 to 133s-m of the nonvolatile semiconductor memory device 100s, that is, new data Cannot be written, the select address processing unit 12s does not perform the data writing process. At this time, the select address processing unit 12s may output a signal notifying the outside that data cannot be written any further.

(Data read operation)
Next, a data read operation of the nonvolatile semiconductor memory device 100s will be described.
First, when a data read command is input from the outside, the access control unit 11s outputs the select address stored in the select address processing unit 12s to the select decoder 131s as a read select address. The select decoder 131s decodes the input select address and outputs a read signal to the OTP array 133s corresponding to the input select address. The OTP array 133s to which the read signal is input outputs the stored data to the sense amplifier unit 15s. The sense amplifier unit 15s reads and amplifies data output from the OTP array 133s, and outputs the amplified data to the data input / output unit 16s. The data input / output unit 16s outputs the data output from the sense amplifier unit 15s to the outside via the input / output terminal 17s.
As described above, the nonvolatile semiconductor memory device 100s performs a data read operation.

The non-volatile semiconductor memory device 100s has the above-described configuration, thereby storing one piece of n-bit width data, reading the stored data, and rewriting the n-bit width data m times as a pseudo MTP. Can be used.
The non-volatile semiconductor memory device 100s includes a select address processing unit 12s, and the select address processing unit 12s stores a select address indicating a use state, thereby storing the last written data in the OTP array 133s. Since the data can be read by specifying the OTP array 133s, that is, the OTP array 133s storing the latest data, the data can be read at a higher speed than the memory device that detects the state of each OTP array 133s and reads the data. It can be performed. Further, since the nonvolatile semiconductor memory device 100s performs the data write operation twice for writing data to the OTP array 133s and once for reading data from the OTP array 133s, the access speed is improved. Although not as much as reading, the access speed can be improved as compared with the case where each OTP array is accessed in order to detect a target to which data is written.

Next, FIG. 2 is a circuit diagram showing a configuration example of the select decoder 131s and the select address processing unit 12s. In FIG. 2, the case where the bit width of data stored in the OTP array 133s is 8 bits and the number of rewrites is 8 (m = n = 8) will be described. Data D <7: 0> is a select address.
The select address processing unit 12s includes flip-flops FF0 to FF2, exclusive OR gates XOR1 and 2, selectors SEL0 to SEL2, OR gate OR1, 4-input OR gate OR2, 2-input AND gates AND9, 12, and 3 inputs. It has an AND gate AND11, a 4-input AND gate AND10, inverters INV1 to INV3, and a buffer BUF1.

Data D <4> is input to the input A of the selector SEL2 via the buffer BUF1. The AND gate AND9 receives the signal obtained by inverting the data D <4> by the inverter INV1 and the data D <2>, and outputs the result of the AND operation to the OR gate OR1. The OR gate OR1 performs an OR operation on the output of the AND gate AND9 and the data D <6> and outputs the result to the input A of the selector SEL1.
The AND gate AND10 includes a signal obtained by inverting the data D <6> by the inverter INV3, a signal obtained by inverting the data D <4> by the inverter INV1, a signal obtained by inverting the data <D2> by the inverter INV2, Logical AND operation on data D <1> and OR gate OR2
Output to. The AND gate AND11 performs an AND operation on the signal obtained by inverting the data D <6> by the inverter INV3, the signal obtained by inverting the data D <4> by the inverter INV1, and the data D <3>. Output to the gate OR2. The AND gate AND12 performs an AND operation on the signal obtained by inverting the data D <6> by the inverter INV3 and the data D <5>, and outputs the result to the OR gate OR2. The OR gate OR2 performs an AND operation on the outputs of the AND gates AND10 to AND12 and the data D <7> and outputs the result to the input A of the selector SEL0.

The exclusive logic gate XOR1 receives the Q outputs of the flip-flops FF2 and FF1, and outputs the result of the exclusive OR operation to the input B of the selector SEL2. The exclusive OR gate XOR2 performs an exclusive OR operation on the outputs of the flip-flops FF1 and FF0Q, and outputs the result to the input B of the selector SEL1.
The inverted output QB of the flip-flop FF0 and the output of the OR gate OR2 are input to the input B of the selector SEL0, and the result of the exclusive OR operation is output to the input D of the flip-flop FF0.

When the selectors SEL0 to SEL2 read and store the data D <7: 0> input via the sense amplifier unit 15s, the selectors SEL0 to SEL2 output the signal from the input B to the inputs D of the flip-flops FF0 to FF2, and store the data. When a select address indicating the OTP array 133s to be written is generated, a signal from the input A is output to the inputs D of the flip-flops FF0 to FF2.
With the configuration described above, when the select address processing unit 12s stores the select address in the select address processing unit 12s in synchronization with the clock signal CLK output in accordance with the operation of the access control unit 11s, the input data D < 7: 0> is encoded into 3 bits and stored in flip-flops FF0 to FF2, and the stored data is output to select decoder 131s as address A <2: 0>, and the select address is updated and the data is written. In the case of pointing to 133s, the data stored in the flip-flops FF0 to FF2 is incremented by “+1” and output to the select decoder 131s as the address A <2: 0>. The select address processing unit 12s outputs a signal SEL8 for selecting the OTP array 133s-9 input from the access control unit 11s to the select decoder 131s.

As shown in the figure, the select decoder 131s has 3-input AND gates AND0 to AND8, and the encoded addresses A <2: 0> output from the select address processing unit 12s are stored in the AND gates AND0 to AND7. Entered.
The AND gate AND0 has an input address A <2: 0> = (0, 0, 0) (showing values of A <2>, A <1>, A <0> in order from the left). , A selection signal SEL <0> having a level of “1 (representing high)” for selecting the OTP array 133s-1 is output; otherwise, a selection signal SEL <0> having a level of “0 (representing low)” is output. Output. The AND gate AND1 outputs the “1” level selection signal SEL <1> for selecting the OTP array 133s-2 when the input address A <2: 0> = (0, 0, 1). In other cases, the selection signal SEL <1> of “0” level is output.

The AND gate AND2 outputs a “1” level selection signal SEL <2> for selecting the OTP array 133s-3 when the input address A <2: 0> = (0, 1, 0). In other cases, the selection signal SEL <2> of “0” level is output. The AND gate AND3 outputs a “1” level selection signal SEL <3> for selecting the OTP array 133s-4 when the input address A <2: 0> = (0, 1, 1). In other cases, the selection signal SEL <3> of “0” level is output.
The AND gate AND4 outputs a “1” level selection signal SEL <4> for selecting the OTP array 133s-5 when the input address A <2: 0> = (1, 0, 0). In other cases, the selection signal SEL <4> of “0” level is output. The AND gate AND5 outputs the “1” level selection signal SEL <5> for selecting the OTP array 133s-6 when the input address A <2: 0> = (1, 0, 1). In other cases, the selection signal SEL <5> of “0” level is output.

The AND gate AND6 outputs a “1” level selection signal SEL <6> for selecting the OTP array 133s-7 when the input address A <2: 0> = (1, 1, 0). In other cases, the selection signal SEL <6> of “0” level is output. The AND gate AND7 outputs a “1” level selection signal SEL <7> for selecting the OTP array 133s-8 when the input address A <2: 0> = (1, 1, 1). In other cases, the selection signal SEL <7> of “0” level is output.
When the selection signal D <8> for selecting the OTP array 133s-9 which is the “1” level use state register is input, the AND gate AND8 outputs the “1” level selection signal SEL <8>. When the “0” level selection signal D <8> is input, the “0” level selection signal SEL <8> is output.

FIG. 3 is a table showing the relationship between data D <7: 0>, address A <2: 0>, and SEL <7: 0>. As shown in the figure, the data D <7: 0> is rewritten from “0” to “1” in order from 0 bit each time data is written to the OTP array 133s. The select address processing unit 12s encodes and stores the input data D <7: 0> into a 3-bit address A <2: 0>, and outputs the address A <2: 0> to the select decoder 131s. . The select decoder 131s decodes the input address A <2: 0> and outputs a selection signal SEL <7: 0> corresponding to the value of the address A <2: 0> to the data storage unit 132s.
The nonvolatile semiconductor memory device 100 s can select the OTP array 133 s according to the number of times of writing by providing the select address processing unit 12 s and the select decoder 131 s as described above.

(Second Embodiment)
In the second embodiment, different configuration examples of the select address processing unit 12s and the select decoder 131s are shown. In the following description, it is assumed that m = n = 8, that is, the OTP array 133s stores 8-bit data, and the data storage unit 132s includes nine OTP arrays 133s-1 to 133s-9.
FIG. 4 is a circuit diagram showing a configuration of the select address processing unit 12sA and the select decoder 131sA in the second embodiment. The select address processing unit 12sA includes flip-flops FF20 to FF27 and selectors SEL20 to SEL27.

The selectors SEL20 to SEL27 output a signal input to the input A when storing the select address in the flip-flops FF20 to FF27, and are input to the input B when generating a select address indicating the OTP array 133s to which data is written. Output a signal.
In the selector SEL20, the data D <0> is input to the input A, the signal of the “1” level of the VDD potential is input to the input B, and one of the input signals is selected and the input D of the flip-flop FF20 is selected. Output to. In the selector SEL21, the data D <1> is input to the input A, the output Q of the flip-flop F20 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF21. .

In the selector SEL22, the data D <2> is input to the input A, the output Q of the flip-flop F21 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF22. . In the selector SEL23, data D <3> is input to the input A, the output Q of the flip-flop F22 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF23. .
In the selector SEL24, the data D <4> is input to the input A, the output Q of the flip-flop F23 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF24. . In the selector SEL25, data D <5> is input to the input A, the output Q of the flip-flop F24 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF25. .

  In the selector SEL 26, the data D <6> is input to the input A, the output Q of the flip-flop F25 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF26. . In the selector SEL27, data D <7> is input to the input A, the output Q of the flip-flop F25 is input to the input B, and one of the input signals is selected and output to the input D to the flip-flop FF26. .

  The flip-flops FF20 to FF27 receive the clock signal output from the access control unit 11s, store the signal input from the input D in synchronization with the clock signal, output the stored signal from the output Q, and store the signal. The inverted signal is output from the output QB. Each of the flip-flops FF20 to FF27 is connected in series via the selectors SEL20 to SEL27 to form a shift register. When the select address is stored, the data D <7: 0> is transmitted via the selectors SEL20 to SEL27. In the case of generating a select address for reading, storing and writing data, the stored data is shifted from the flip-flop FF20 toward the flip-flop FF27, and the data is shifted to the left in the drawing. The flip-flops FF20 to F27 operate to shift “1” into the flip-flop FF20 that stores the least significant bit when shifting data. Further, the select address processing unit 12sA outputs the output Q of the flip-flops FF20 to FF27 as data DT <7: 0> to the select decoder 131sA.

The select decoder 131sA has nine 2-input AND gates AND21 to AND29.
The AND gate AND21 selects the OTP array 133s-1 when the data DT <0: 1> = (0, 1) (indicating values of DT <0> and DT <1> in order from the left). The 1 ”level selection signal SEL <0> is output, otherwise the“ 0 ”level selection signal SEL <0> is output. The AND gate AND22 outputs the “1” level selection signal SEL <1> for selecting the OTP array 133s-2 when the data DT <1: 2> = (0, 1), and otherwise “ A selection signal SEL <1> of “0” level is output.

The AND gate AND23 outputs a selection signal SEL <2> of “1” level for selecting the OTP array 133s-3 when the data DT <2: 3> = (0, 1), and otherwise “ A selection signal SEL <2> of “0” level is output. The AND gate AND24 outputs the “1” level selection signal SEL <3> for selecting the OTP array 133s-4 when the data DT <3: 4> = (0, 1), and otherwise “ The selection signal SEL <3> of “0” level is output.
The AND gate AND25 outputs a “1” level selection signal SEL <4> for selecting the OTP array 133s-5 when the data DT <4: 5> = (0, 1), and otherwise “ The selection signal SEL <4> of “0” level is output. The AND gate AND26 outputs the selection signal SEL <5> of “1” level for selecting the OTP array 133s-6 when the data DT <5: 6> = (0, 1), and otherwise “ A selection signal SEL <5> of “0” level is output.

The AND gate AND27 outputs a selection signal SEL <6> of “1” level for selecting the OTP array 133s-7 when the data DT <6: 7> = (0, 1), and otherwise “ The selection signal SEL <6> of “0” level is output. The AND gate AND28 outputs a selection signal SEL <7> of “1” level for selecting the OTP array 133s-8 when the data DT <7> is “1” level, and “0” level otherwise. The selection signal SEL <7> is output.
When the selection signal D <8> of “1” level is input from the select address processing unit 12sA, the logic gate AND29 selects the “1” level selection signal SEL <that selects the OPT array 133s-8 storing the selection address. 8> is output. Otherwise, a selection signal SEL <8> of “0” level is output.
In the present embodiment, the select address processing unit 12sA and the select decoder 131sA can be configured with fewer logic elements than the select address processing unit 12s and the select decoder 131s of the first embodiment.

(Third embodiment)
FIG. 5 is a schematic block diagram showing the configuration of the nonvolatile semiconductor memory device 200s of the third embodiment. The nonvolatile semiconductor memory device 200s includes an access control unit 21s, a select address processing unit 22s, a row decoder 23s, a data storage unit 24s, a write amplifier unit 14s, a sense amplifier unit 15s, a data input / output unit 16s, and an input / output terminal 17s. Is provided.
The data storage unit 24s includes k MTP block units 13s-1 to 13s-k (an integer satisfying k> 1). The MTP block units 13s-1 to 13s-k have the same configuration as that of the MTP block unit 13s of the first embodiment illustrated in FIG. 1, and one or all of them are shown as representatives below. In this case, the MTP block unit 13s is referred to.

The select address processing unit 22s is information indicating the usage state of the nonvolatile semiconductor memory device 200s read from each of the MTP block units 13s-1,..., 13s-k, similarly to the select address processing unit 12s of the first embodiment. Information indicating a write operation output from the access control unit 21s while storing a certain k select addresses and outputting the select address to the MTP block unit 13s according to the information indicating the read operation output from the access control unit 21s. Accordingly, the select address is updated and output to the MTP block unit 13s.
Since the nonvolatile semiconductor memory device 200s is the same as the corresponding configuration of the first embodiment except for the access control unit 21s, the select address processing unit 22s, the row decoder 23s, and the data storage unit 24s, the same reference numerals (14s to 17s) are used. ) And description thereof is omitted.

  Similarly to the access control unit 11 s of the first embodiment, the access control unit 21 s selects the select address processing unit 22 s according to the data read command input from the outside and the data write command input from the outside. The operation order of each of the write amplifier unit 14s, the sense amplifier unit 15s, and the data input / output unit 16s is controlled. Further, a row address signal is input, and the row address is set to the row address in accordance with data reading and data writing. Output to the decoder 23s. The row decoder 23s decodes the input row address signal and selects any one of the MTP block units 13s corresponding to the row address signal from the k MTP block units 13s included in the data storage unit 24s. . In the read command, the MTP block unit 13s selected by the row decoder 23s outputs the stored data to the sense amplifier unit 15s. In the write instruction, data is input from the write amplifier unit 14s to the MTP block unit 13s selected by the row decoder 23s, and the data is stored.

  Compared to the operation of the nonvolatile semiconductor memory device 100s of the first embodiment, the nonvolatile semiconductor memory device 200s configured as described above receives the row address signal and the row address signal input by the row decoder 23s. The difference is that the corresponding MTP block unit 13s is selected and operated. The selected MTP block unit 13s reads and writes data by the same operation as in the first embodiment. Accordingly, the non-volatile semiconductor memory device 200s can store k n-bit width data, whereas the non-volatile semiconductor memory device 100s stores one n-bit width data. Separately, data can be read and rewritten. At this time, the row decoder 23s selects any one MTP block unit 13s from the k MTP block units 13s-1 to 13s-k according to a row address input from the outside.

Next, the nonvolatile memory element (memory element) 30 used in the nonvolatile semiconductor memory devices 100s and 200s will be described.
6 and 7 are configuration diagrams of the memory element 30 used in the OTP array 133s of the first to third embodiments described above. FIG. 6A is a diagram showing a layout of the memory element 30. FIG. 6B is a diagram illustrating an equivalent circuit of FIG. As shown in the drawing, the memory element 30 is a transistor T1 having a floating gate FG. FIG. 7A shows a cross-sectional view along AA ′ in FIG. 6A, and FIG. 7B shows a cross-sectional view along BB ′ in FIG. 6A.

Structurally, in FIGS. 6A and 6B and FIGS. 7A and 7B, the transistor T1 is formed (arranged) on the p-type semiconductor substrate 1. In the transistor T1, an n-type diffusion layer 5 (first n-type diffusion layer) that forms a drain, a channel region 4, and an n-type diffusion layer 7 (second n-type diffusion layer) that forms a source are arranged in series. The n-type diffusion layer 5 and the n-type diffusion layer 7 are arranged opposite to each other with the channel region 4 interposed therebetween to form a transistor formation region 8 of the transistor T1.
The n-type diffusion layer 5 is connected via a contact 10 to a metal wiring 12 (first metal wiring) that is a drain wiring arranged in series. The n-type diffusion layer 7 is connected via a contact 11 to a metal wiring 13 (second metal wiring) which is a source wiring arranged in the horizontal direction on the same plane orthogonal to the series direction.

An n-type well 2 is formed on the p-type semiconductor substrate 1 at a certain interval in the horizontal direction with respect to the transistor formation region 8, and an n-type diffusion layer 17 (third n-type diffusion) is formed on the n-type well 2. Layer) and p-type diffusion layer 15 (first p-type diffusion layer) are formed. The n-type diffusion layer 17 is connected via a contact 18 to a metal wiring 19 (third metal wiring) which is a control gate wiring arranged in the horizontal direction (second direction). The p-type diffusion layer 15 is connected to the metal wiring 19 through the contact 16 similarly to the n-type diffusion layer 17.
Polysilicon 9 arranged in parallel with metal wiring 19 forms floating gate FG, and forms part of n-type well 2 region or part of p-type diffusion layer 15 region and channel region 4. A capacitor is formed between the n-type well 2 and a capacitor with the channel region 4.
The region indicated by 20 and 21 is an isolation insulating oxide film.

  Next, FIG. 8 is a table showing an operation table of the memory element 30. FIG. 8A is an operation table when the memory element 30 is used as an OTP. In the write operation to the memory element 30, a voltage of 6V (second voltage) is applied to the control gate CG, a voltage of 5V (first voltage) is applied to the drain D, and a voltage of 0V is applied to the source S. . As a result, a depletion layer is formed in the vicinity of the drain D to which a high voltage is applied, and hot electrons are generated. The generated hot electrons are injected into the floating gate FG and accumulated. As a result, the threshold voltage of the floating gate transistor T1 of the memory element 30 changes to a voltage higher than the initial state, and a write state is entered.

  Next, in the read operation for the memory element 30, a voltage of 3V is applied to the control gate CG, a voltage of 1V (third voltage) is applied to the drain D, and a voltage of 0V is applied to the source S. At this time, whether an erase state or a write state is determined according to whether or not a current flows between the drain D and the source S of the memory element 30 and information is read. The threshold voltage in the initial state of the memory element 30 is about 1V, and when 3V is applied to the control gate CG, it is turned on and energized. On the other hand, in the write state, the threshold voltage of the memory element 30 is about 5 V when electrons are injected into the floating gate FG. Even if 3 V is applied to the control gate CG, it is in an off state and is not energized.

Next, FIG. 8B is an operation table when the memory element 30 is used as an MTP. Write and read operations on the memory element 30 are the same as those illustrated in FIG.
In the erasing operation on the memory element 30, a voltage of 0V is applied to the control gate CG, a voltage of 8V (fourth voltage) is applied to the drain D, and the source S is opened, or 2V is applied to the source S. A voltage of (fifth voltage) is applied. As a result, a high electric field is applied between the control gate CG and the drain D, an FN current flows, and electrons are emitted from the floating gate FG to the drain D. As a result, the memory device 30 enters an erased state in which the threshold voltage has changed to a voltage lower than the initial state, and data has been erased.

  Next, the threshold voltage may become negative in a state where the threshold voltage is lower than the threshold voltage in the initial state (over-erased state) by the erase operation of the memory element 30. In this case, the memory element 30 is always in an on state even when the control gate CG is 0 V. Therefore, when a voltage is applied to the drain D and the source S, a current always flows between the drain D and the source S. The selectivity due to the voltage applied to the gate CG is lost, and when it is incorporated in the memory array, it becomes defective. Therefore, a write-back operation is performed to return the threshold voltage that has become too low to the vicinity of the threshold voltage in the initial state. There are two write-back operations as shown below.

  In the first write-back operation (first write-back operation), as shown in the figure, a voltage of 0 V or 1 V (third voltage) is applied to the control gate CG, and 8 V (fourth voltage) is applied to the drain D. ) And a voltage of 0 V is applied to the source S. At this time, if the memory element 30 is over-erased, the memory element 30 is turned on, a channel current flows between the drain D and the source S, and a high voltage is applied to the drain D. Writing is performed in which hot electrons are generated and hot electrons are injected into the floating gate FG. As a result, the threshold voltage of the memory element 30 increases and becomes a positive threshold voltage. At this time, since a voltage lower than that in the write operation is applied to the control gate CG, the amount of hot electrons injected into the floating gate FG is smaller than that in the write operation. This writing is called weak writing (drain stress).

  The second write-back operation (second write-back operation) is basically a write operation, but since it is necessary to write gradually over time, the voltage applied to the control gate CG is about 1V. The threshold voltage is changed to a positive value of about 1V by gradually increasing the voltage from 1 to about 3V and performing writing a plurality of times. At this time, the voltage applied to the control gate CG may be gradually increased in a predetermined step, or may be increased linearly according to the voltage application time.

  Next, FIG. 9 is a graph showing changes in characteristics due to operations of writing, erasing, and writing back of the memory element 30, and a diagram showing the floating gate transistor T1 that is an equivalent circuit of the memory element 30. The vertical axis direction represents the drain current, and the horizontal axis direction represents the control gate voltage. The memory device 30 has a threshold voltage of 1V in the initial state, but the threshold voltage changes to 5V by the write operation. Thereafter, the threshold voltage of the memory element 30 can be changed to −1V by the erase operation and can be changed to 1V by the write-back operation. As described above, information can be stored in the memory element 30 by changing the threshold voltage of the memory element 30.

  Next, FIG. 10 is a graph showing the weak write characteristics of the memory element 30, and a diagram showing a voltage applied to the floating gate transistor T1 which is an equivalent circuit of the memory element 30. The vertical axis direction is the threshold voltage of the memory element 30, and the horizontal axis direction is the time for performing weak writing. For example, when weak writing is performed by applying a voltage of 0 V to the control gate CG, hot electrons having high energy are generated by a high electric field in the vicinity of the drain, and some of the hot electrons are injected into the floating gate FG to weakly write. Thus, the threshold voltage of the memory element 30 eventually self-converges to the initial threshold voltage. Here, when a voltage of 1V is applied to the control gate CG, the threshold voltage that converges in accordance with the voltage applied to the control gate CG shifts, so that the threshold voltage that converges can be controlled. By using this characteristic, the threshold voltage of the memory element 30 can be self-converged to a positive threshold voltage by writing back to the memory element 30 that has been over-erased by the erasing operation. Can be eliminated.

FIG. 11 is a diagram showing an equivalent circuit of the coupling system of the memory element 30. The potential applied to the control gate CG is VCG, the electrostatic capacity of the control gate CG and the floating gate FG is C (FC), the potential applied to the source S is VS, and the electrostatic potential between the source S and the floating gate FG. The capacitance is C (FS), the potential applied to the semiconductor substrate Sub is Vsub, the capacitance between the semiconductor substrate Sub and the floating gate FG is C (FB), the potential applied to the drain D is VD, and the drain D And the floating gate FG is C (FD), and the potential applied to the floating gate is VFG.
When the state of the floating gate FG is the initial state (neutral state), the total charge of this system is zero, so the following equation (1) holds.

  When the total capacitance of this system is CT, CT is expressed by the following equation (2).

  When Expression (1) is transformed with respect to VFG using Expression (2), it can be expressed as the following Expression (3).

  Here, assuming that C (FD) = C (FS) ≈0 and Vsub = VS = 0, Expression (3) is expressed as the following Expression (4).

  Here, when C (FG) / {C (FC)} + C (FB) = α (coupling ratio), Expression (4) is expressed by the following Expression (5).

  Normally, α≈0.6 is set, and the capacitance of the floating gate FG and the like is determined, and the nonvolatile semiconductor memory cell is designed.

  The memory element 30 described above is a memory element that can be manufactured by a standard CMOS process. The nonvolatile semiconductor memory device 100s according to the first embodiment and the nonvolatile semiconductor memory device 200s according to the second embodiment using the memory element 30 as a memory element can be mixedly mounted on a system LSI or the like without increasing the manufacturing process.

(Fourth embodiment)
FIG. 12 is a schematic diagram showing a configuration example of the nonvolatile semiconductor memory device 100s of the first embodiment shown in FIG. 1 as an OTP having a matrix array (memory array) using the memory elements 30 in the fourth embodiment. is there.
As shown in the figure, the memory array has memory at intersections of select signal lines (selection signal lines) SEL1 to SELm + 1 and bit lines BIT1-0,..., BITj-0, ..., BIT1-7, ..., BITj-7. An element 30 is arranged and configured. The memory array is configured to perform reading and writing in units of 8 bits, that is, configured to perform data input / output in units of 8 bits. The non-volatile semiconductor memory device 100s corresponds to a memory array and select decoder 131s composed of memory cells M11-0 to M11-7,..., M (m + 1) j-0 to M (m + 1) j-7, which are memory elements 30. Select decoder 2000, column decoders 300-1 to 300-j, data input conversion circuit 400, sense amplifiers 500-0 to 500-7 corresponding to sense amplifier unit 15s, and select address processing unit corresponding to select address processing unit 12s 600, switching elements CG1-0 to CGj-0,... CG1-7 to CGj-7 that are turned on / off according to the outputs of the column decoders 300-1 to 300-j.

The (m + 1) × j memory cells M11-0 to M (m + 1) j-0 storing data corresponding to the first bit constitute the memory block 100-0. The memory cells M11-1 to M (m + 1) j-1,..., M11-7 to M (m + 1) j-7 that store the data of the second to eighth bits are similar to the first bit in the memory block 100. -1, ..., 100-7.
In the memory block 100-0, the drain D of the memory cells M11-0 to M (m + 1) 1-0 is connected to the bit line BIT1-0. The drains D of the memory cells M12-0 to M (m + 1) j-0 are connected to the bit lines BIT2-0 to BITj-0 similarly to the memory cells M11-0 to M (m + 1) 1-0. Also in the memory blocks 100-1 to 100-7, similarly to the memory block 100-0, each of the memory cells M11-1 to M (m + 1) j-1,..., M11-7 to M (m + 1) j-7 Are connected to bit lines BIT1-1 to BITj-1,... BIT1-7 to BITj-7. Bit lines BIT1-0 to BITj-0,... BIT1-7 to BITj-7 are connected to data lines D0 to D7 via switch elements CG1-0 to CGj-0,... CG1-7 to CGj-7. Is done.

  The select decoder 2000 includes m + 1 select decoder circuits 200-1 to 200-m + 1. The select decoder circuits 200-1 to 200-m + 1 decode the select address output from the select address processing unit 600 and select the select address. Any one of the signal lines SEL1 to SELm + 1 is activated. The select signal line SEL1 is connected to the control gate CG of the memory cells M11-0 to M1j-0,..., M11-7 to M1j-7 included in each of the memory blocks 100-0 to 100-7 to read data or A memory cell to be written is selected. Like the select signal line SEL1, the select signal lines SEL2 to SELm + 1 are connected to the control gates CG of the memory cells included in the memory blocks 100-0 to 100-7, and select the memory cell from which data is read or written. To do. Each of the select decoder circuits 200-1 to 200-m + 1 includes an address decode circuit 201, an inverter 202, and a level shift circuit 203.

Each of the column decoders 300-1 to 300-j includes a column decoder circuit 301, an inverter 302, and a level shift circuit 303. The column decoders 300-1 to 300-j decode the select address output from the select address processing unit 600 and output the column lines COL1 to COLj. Any one column line is activated to select a bit line, and switching elements CG1-0 to CGj-0,..., CG1-7 to CGj-7 are turned on / off.
The data input conversion circuit 400 receives input data Din0 to Din7, outputs a high voltage Vp3 (5 V) corresponding to the write operation to the data lines D0 to D7, and outputs the column lines COL1 to COLj and the select signal line SEL1. Apply to the memory cell selected by ~ SELm + 1. The sense amplifiers 500-0 to 500-7 are connected to the data lines D0 to D7, amplify the data read from the memory cells selected by the column lines COL1 to COLj and the select signal lines SEL1 to SELm + 1, and output data Dout0. Output as ~ Dout7. The sources S of all the memory cells M11-0 to Mmj-7 are commonly connected and grounded.

Next, the operation of the nonvolatile semiconductor memory device 100s of this embodiment will be described.
In the write operation, for example, the select decoder circuit 200-1 and the column decoder 300-1 activate the select signal line SEL1 and the column line COL1 by the select address output from the select address processing unit 600. At this time, the voltage Vp1 (6V) is applied to the select signal line SEL1, and the voltage Vp1 (6V) is applied to the control gate CG of the memory cells M11-0 to M1j-0,..., M11-7 to M1j-7. Is done. The data input conversion circuit 400 applies a voltage Vp3 (5 V) to the data lines D0 to D7 according to the input data Din0 to Din7. Further, the column decoder 300-1 applies a voltage Vp2 higher than the voltage Vp3 to the column line COL1 by the level shift circuit 303 of the column decoder 300-1, and the switch elements CG1-0, CG1-1,. By turning on, the data lines D0 to D7 and the bit lines BIT1-0, BIT1-1,... BIT1-7 are connected, and the voltage Vp3 is applied to the drain D of the memory cell.

For example, when write data is input as Din0 = Din2 = Din4 = Din6 = “0” data (write), Din1 = Din3 = Din5 = Din7 = “1” (not write), the data lines D0, D2 , D4, D6 are applied with voltage Vp3, and data lines D1, D3, D5, D7 are applied with 0V voltage. Since the column line COL1 is selected, the voltage Vp3 (5V) is applied to the bit lines BIT1-0, BIT1-2, BIT1-4, BIT1-6, and the bit lines BIT1-1, BIT1-3, BIT1- 5, 0V is applied to BIT1-7. As a result, the memory cells M11-0, M11-2, M11-4, and M11-6 are written, and the memory cells M11-1, M11-3, M11-5, and M11-7 are written. I will not.
As described above, a memory cell is selected according to the select address, and data is stored in the selected memory cell.

In the read operation, a memory cell is selected according to the select address as described above, the sense amplifiers 500-0 to 500-7 detect the current flowing through the selected memory cell, and the detected current is amplified to obtain data. The voltage corresponding to “0” or “1” is detected and output as output data Dout0 to Dout7. At this time, if the memory cell is in the erased state (“1”; on), a current flows through the memory cell, and if the selected memory cell is in the written state (“0”; off), no current flows through the memory cell. .
In the first embodiment of FIG. 1, the configuration in which the n-bit width data is read and written at a time is shown. However, in the present embodiment, the nonvolatile semiconductor memory device 100s has n> 8 when n> 8. The n-bit width data is read and written every 8 bits a plurality of times, and the column decoders 300-1 to 300-j perform the switching a plurality of times. At this time, in order to control the order of data to be read or written, the select address processing unit 600 sequentially switches a part of the select address, for example, the upper bits of the select address, and reads and writes data for every 8 bits. Do.
Of course, the select address processing unit 600 may select an arbitrary column address according to the column address input from the external address terminal without sequentially switching a part of the select address.

(Fifth embodiment)
FIG. 13 is a schematic block diagram showing a configuration of the nonvolatile semiconductor memory device 200s of the third embodiment shown in FIG. 5 as an MTP having a matrix array (memory array) using the memory elements 30 in the fifth embodiment. is there. The non-volatile semiconductor memory device 200s is k n bits, whereas the fourth embodiment shown in FIG. 12 is an OTP that can rewrite one n-bit width (n = 8) data m times. The OTP can rewrite the width data m times. The non-volatile semiconductor memory device 200s includes k row decoders 700-1 to 700-k, k select decoders 2000-1 to 2000-k, and k × 8, as compared with the non-volatile semiconductor memory device 100s. The memory blocks 100-10 to 100-17,..., 100-k0 to 100-k7 are different from the memory blocks 100-10 to 100-17 in that a select address processing unit 601 is provided instead of the select address processing unit 600. The same components as those of the non-volatile semiconductor memory device 100s are denoted by the same reference numerals (300-1 to 300-j, 400, 500-0 to 500-7) as the corresponding components, and the description thereof is omitted.

One select address is stored in the memory block group including the memory blocks 100-10 to 100-17. Similarly, one select address is stored in each of seven memory block groups including memory blocks 100-20 to 27,..., Memory blocks 100-k0 to 100-k7, and k select addresses are stored in the memory block. 100-10 to 100-17, ..., 100-k0 to 100-k7.
The select address processing unit 601 corresponds to the select address processing unit 22s shown in FIG. 5, reads and stores k select addresses, and according to information indicating a read operation output by an access control unit (not shown). A select address corresponding to the memory block group from which data is read is output to select decoders 2000-1 to 2000-k, and the select corresponding to the memory block group to which data is written is output according to the information indicating the write operation output from the access control unit. The address is updated and output to the select decoders 2000-1 to 2000-k.

The row decoders 700-1 to 700-k are connected to the select decoders 2000-1 to 2000-k and the memory blocks 100-10 to 100-17, ..., 100-k0 to 100-k7 in association with each other. Is done. The select decoders 2000-1 to 2000-k have the same configuration and the same configuration as the select decoder 2000 of the fourth embodiment shown in FIG.
One of row decoders 700-1 to 700-k is activated by a row address input from the outside, and the activated row decoder selects and activates a corresponding select decoder and memory block, and The operations (writing, reading, erasing, writing back) described in the fourth embodiment are performed. The nonvolatile semiconductor memory device 200s includes the select address processing unit 601 and the row decoders 700-1 to 700-k, thereby storing and reading k pieces of data having an n-bit width. As a result, the non-volatile semiconductor memory device 200s can store k different pieces of data and can be used for OTPs that require a plurality of pieces of data.

(Sixth embodiment)
FIG. 14 is a schematic block diagram showing the configuration of the nonvolatile semiconductor memory device 101s in the sixth embodiment. The nonvolatile semiconductor memory device 101s is characterized in that each of the memory elements 30 included in the nonvolatile semiconductor memory device 100s of the fourth embodiment is used not as OTP but as MTP. In order to use the memory element 30 as an MTP, the non-volatile semiconductor memory device 101 s includes the erase control circuit 800 that applies a voltage for erase operation to the source S of the memory element 30. The configuration is the same as that of the nonvolatile semiconductor memory device 100 s of the embodiment, and the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  The erase control circuit 800 includes a level shift circuit, is connected to the sources S of all the memory elements 30 included in the nonvolatile semiconductor memory device 101s, and applies the voltage Vp4 used for the erase operation to the sources S of the memory elements 30. . The erase circuit 800 applies a ground potential of 0 V to the source S of the memory element 30 in the case of write, write-back, and erase operations, and applies the voltage Vp4 (2 V) to the source of the memory element 30 in the case of the erase operation. Apply to S. The applied potential is switched by a non-erasing signal EB input from the outside.

With this configuration, the non-volatile semiconductor memory device 101s can use not only a plurality of memory elements 30 that are OTPs but also a pseudo MTP that is used by switching, as well as a plurality of memory elements 30 that are OTPs. At this time, the memory element 30 can be switched and used in accordance with the reliability of whether or not the data stored in the memory element 30 that is an OTP can be correctly held.
Furthermore, there are the following advantages. The biggest problem with OTP is that a write test cannot be performed at the time of shipment. Since writing tests are not possible, there remains a problem with reliability. In the nonvolatile semiconductor memory device 101 s shown in the sixth embodiment in FIG. 14, after performing a write test at the time of shipment, erasing is performed last, thereby providing a highly reliable OTP whose operation has been verified by the write test. .

(Seventh embodiment)
FIG. 15 is a schematic block diagram showing the configuration of the nonvolatile semiconductor memory device 201s in the seventh embodiment. The non-volatile semiconductor memory device 201s is characterized in that each of the memory elements 30 included in the non-volatile semiconductor memory device 200s of the fifth embodiment shown in FIG. 13 is used as an MTP instead of an OTP. In order to use the memory element 30 as an MTP, the non-volatile semiconductor memory device 201s includes an erase control circuit 800-1 to 800-k that applies a voltage for an erase operation to the source S of the memory element 30. The configuration is the same as that of the nonvolatile semiconductor memory device 200 s of the fifth embodiment shown in FIG. 13, and the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  Erase control circuits 800-1 to 800-k are constituted by level shift circuits, are provided corresponding to the respective row decoders 700-1 to 700-k, and correspond to the respective row decoders 700-1 to 700-k. Commonly connected to the source S of the memory element 30 included in each of the connected memory blocks 100-10 to 100-k7. Erase control circuits 800-1 to 800-k have the same configuration, and non-erase signals EB1 to EBk for switching the potential applied to the source S of the memory element 30 are input to each.

With this configuration, the non-volatile semiconductor memory device 201s can use not only a plurality of memory elements 30 that are OTPs but also a pseudo MTP that is used by switching, as well as a plurality of memory elements 30 that are OTPs. At this time, the memory element 30 can be switched and used in accordance with the reliability of whether or not the data stored in the memory element 30 that is an OTP can be correctly held.
In this embodiment, a redundant memory OTP array (a memory array selected by SELm + 1) is provided as a row address storage unit. However, a redundant memory array unit (for example, SELm + 2 is selected as a column address storage unit). A memory array) may be provided.

(Eighth embodiment)
FIG. 16 is a layout diagram showing a configuration example of the memory block 100-0 by the memory element 30 in the fourth to seventh embodiments described above as the eighth embodiment.
In the memory block 100-0, the memory cells M11,..., Mmj which are the memory elements 30 are arranged in a matrix in the row direction and the column direction. In addition, the memory cells M11,..., Mmj adjacent in the vertical direction (column direction, series direction of transistor formation region) in the figure are arranged symmetrically with respect to the horizontal direction orthogonal to the serial direction and are adjacent to each other in the serial direction. One memory cell and the metal wiring 13 which is the source line (S1, S2) are shared.

Further, the memory cells M11,..., M (m + 1) j adjacent in the left-right direction (row direction, horizontal direction orthogonal to the series direction of the transistor formation region) in the figure are arranged symmetrically with respect to the horizontal direction. The n-type diffusion layer 17 and the contact 18 are shared with one memory cell adjacent in the vertical direction, and are connected and connected without providing a boundary between the n-type wells 2. Further, the memory cells in which the row directions of the memory cells M11,..., M (m + 1) j are the same share the metal wiring 19 that is the control gate line (SEL1, SEL2, SEL3, SEL4), and the source line (S1, The metal wiring 13 which is S2) is shared and arranged.
In this manner, the arrangement area can be reduced by arranging the memory cells M11,..., M (m + 1) j.

(Ninth embodiment)
As the ninth embodiment, the non-volatile semiconductor memory device 101s of the sixth embodiment described above has a threshold verification circuit inside or outside, and has two types of verification: an erase operation for the memory element 30 and a first write-back operation. The sequence will be described.
First, FIG. 17 is a flowchart of a verification sequence performed by the nonvolatile semiconductor memory device 101s for the erase operation and write-back operation of the memory element 30 included in the nonvolatile semiconductor memory device 101s described above as the ninth embodiment. Note that a threshold verification circuit (not shown) controls the following operations. The verification sequence is performed after the write test is performed. Here, the write test is verification performed by writing data to the memory element 30 and determining whether or not the threshold value is higher than a predetermined value.

  First, in the erase operation, the column decoders 300-1 to 300-j select a column line corresponding to the select address output from the select address processing unit 600. The data input conversion circuit 400 applies the voltage Vp3 (8 V) to the drain D of the selected memory element 30 through the data lines D0 to D7. The select decoder 2000 applies a voltage of 0 V to the control gate CG of the memory element 30 corresponding to the select address output from the select address processing unit 600. The erase control circuit 800 applies a voltage Vp4 (2 V) to the source line S to which the sources of the memory elements 30 are commonly connected. As a result, an erase state voltage is applied to each terminal of the selected memory element 30 to perform erasure (step S101).

By the erasing operation in step S101, the threshold verification circuit determines whether or not the threshold voltage is higher than 1V which is the threshold voltage in the initial state as a confirmation as to whether or not the erasure has been correctly performed (step S102).
In step S102, when the threshold voltage is higher than the threshold voltage in the initial state (step S102: Yes), the threshold verification circuit increments the erase count N in step S101 by “1”, and whether the erase count N is 100 or less. Is determined (step S103).
The erase count N is initialized to “0” at the start of the sequence.

When the number of erases is 100 or less (step S103; N ≦ 100), the threshold value verification circuit performs control to execute step S101.
On the other hand, if the number of erases exceeds 100 (step S103; N> 100), the threshold verification circuit determines that the memory element 30 to be tested has failed to be erased correctly and notifies the outside. (Step S108).
In step S102, when the threshold voltage is lower than the threshold voltage in the initial state (step S102; No), the threshold verification circuit determines whether or not the threshold voltage of the memory element 30 is 0.5 V or more (step S104). .
Whether or not the threshold voltage 0.5V as the determination criterion in step S104 has a margin for turning off the memory element 30 with respect to the voltage (0V) applied to the control gate CG in the non-selected state. It is a step which determines. Note that the threshold voltage 0.5 V as a determination reference is a determination reference value determined according to a process used for the memory element 30 and a voltage applied to the control gate CG of the memory element 30 in a non-selected state.

In step S104, when the threshold voltage is less than 0.5 V (step S104; No), the threshold verification circuit uses the data input conversion circuit 400 to connect the drain D of the selected memory element 30 via the data lines D0 to D7. The voltage Vp3 (8V) is applied to the memory cell 30, the select decoder 2000 applies a voltage of 1V to the control gate CG of the memory element 30 corresponding to the select address output from the select address processing unit 600, and the erase control circuit 800 Control is performed to apply the voltage Vp4 (0 V) to the source line S to which the sources of the elements 30 are commonly connected. Thereby, the voltage corresponding to the first write-back operation is applied to each terminal of the memory element 30 to be verified for 100 ms, and the write-back is performed (step S105).
The threshold verification circuit increments M, which counts the number of write-backs in step S105, by “1”, and determines whether the number of write-backs is 10 or less (step S106).

In step S106, when the number of write-back times is 10 or less (step S106; M ≦ 10), the threshold verification circuit performs control to execute step S104 again, and determines the threshold voltage of the memory element 30.
On the other hand, when the number of write-backs exceeds 10 in step S106 (step S106; M> 10), the threshold verification circuit determines that the memory element 30 to be tested has failed to be erased correctly and determines a failure. Notify the outside (step S108).
Note that M for counting the number of write-backs is initialized to “0” at the start of the sequence.
In step S104, when the threshold voltage is 0.5 V or more (step S104; Yes), the threshold verification circuit notifies the outside that the memory element 30 can correctly perform the erasing operation (step S107).
Through the above processing, the threshold verification circuit can verify that the memory element 30 operates correctly.

Next, as a different verification sequence, FIG. 18 is a flowchart of a verification sequence performed by the nonvolatile semiconductor memory device 101s for the erase operation and the write back operation of the memory element 30 included in the nonvolatile semiconductor memory device 101s.
First, in the erase operation, the column decoders 300-1 to 300-j select a column line corresponding to the select address output from the select address processing unit 600. The data input conversion circuit 400 applies the voltage Vp3 (8 V) to the drain D of the selected memory element 30 through the data lines D0 to D7. The select decoder 2000 applies a voltage of 0 V to the control gate CG of the memory element 30 corresponding to the select address output from the select address processing unit 600. The erase control circuit 800 applies a voltage Vp4 (2 V) to the source line S to which the sources of the memory elements 30 are commonly connected. In the threshold verification circuit, the data input conversion circuit 400, the select decoder 2000, and the erase control circuit 800 perform control to apply the above-described voltage, and erase is performed by applying a voltage to the selected memory element 30 for 10 ms. (Step S201).

Through the erasing operation in step S201, the threshold verification circuit determines whether or not the threshold voltage is higher than 1V which is the threshold voltage in the initial state as a check as to whether or not the erasure has been correctly performed (step S202).
In step S202, when the threshold voltage is higher than the threshold voltage in the initial state (step S202: Yes), the threshold verification circuit increments the number of erases N in step S201 by “1”, and whether the number of erases N is 1000 or less. Is determined (step S103).
The erase count N is initialized to “0” at the start of the sequence.

When the erase count is 1000 times or less (step S203; N ≦ 1000), the threshold value verification circuit performs control to execute step S201.
On the other hand, when the number of erases exceeds 1000 (step S203; N> 1000), the threshold verification circuit determines that the memory element 30 to be tested has not been correctly erased and notifies the outside of the failure. (Step S208).
In step S202, when the threshold voltage is lower than the threshold voltage in the initial state (step S202; No), the threshold verification circuit determines whether or not the threshold voltage of the memory element 30 is 0.5 V or more (step S204). .
Note that the determination in step S204 is a step of determining whether or not there is a margin for the memory element 30 to be in an off state with respect to the voltage (0 V) applied to the control gate CG in the non-selected state.

In step S204, when the threshold voltage is less than 0.5 V (step S204; No), the threshold verification circuit uses the drain D of the selected memory element 30 by the data input conversion circuit 400 via the data lines D0 to D7. Is applied with a voltage Vp3 (8V), and the select decoder 2000 applies a voltage of (1 + 0.5M) V to the control gate CG of the memory element 30 corresponding to the select address output from the select address processing unit 600 to control the erase. The circuit 800 performs control to apply the voltage Vp4 (0 V) to the source line S to which the sources of the memory elements 30 are commonly connected. As a result, a voltage corresponding to the first write-back operation is applied to each terminal of the memory element 30 to be verified for 1 ms, and the write-back is performed (step S205).
Note that M is a count value of the number of write-back times. Each time the write-back operation (step S205) is performed, the select decoder 2000 increases the voltage applied to the control gate CG and performs the write-back operation.
The threshold verification circuit increments M, which counts the number of write-backs in step S205, by “1”, and determines whether the number of write-backs is 5 or less (step S206).

In step S206, when the number of write-back times is 5 or less (step S206; N ≦ 5), the threshold value verification circuit performs control to execute step S204 again, and determines the threshold voltage of the memory element 30.
On the other hand, if the number of write-backs exceeds 5 in step S206 (step S206; N> 5), the threshold verification circuit determines that the memory element 30 to be tested has not been erased correctly and determines a failure. Notify the outside (step S208).
In step S204, when the threshold voltage is 0.5 V or higher (step S204; Yes), the threshold verification circuit notifies the outside that the memory element 30 can correctly perform the erase operation (step S207).

Through the above processing, the threshold verification circuit can verify that the memory element 30 operates correctly. In this sequence, the write back operation time is set longer than that in the verification sequence of FIG. 17, and an operation for preventing a failure in which the threshold voltage becomes a negative voltage due to over-erasing and is always on is performed. Occurrence can be reduced.
The two verification sequences described above are similarly performed in the nonvolatile semiconductor memory device 201s of the seventh embodiment illustrated in FIG.

The verification sequence performed in FIG. 17 and FIG. 18 described above is performed by the nonvolatile semiconductor memory device 101s. However, using a test device or the like, the threshold verification circuit and the erase control circuit are not provided, and the memory element 30 is replaced with the OTP. This can also be performed for the non-volatile semiconductor memory devices 100s and 200s used. As a result, a product that sufficiently guarantees the reliability of the memory element 30 can be shipped. In addition, the nonvolatile semiconductor memory devices 101s and 201s including the threshold value verification circuit for processing the above-described sequence and the erase control circuit 800 increase the circuit scale and increase the manufacturing cost. For example, the non-volatile semiconductor memory devices 100s and 200s that use the memory element 30 as the OTP and realize the pseudo MTP are suitable.
Further, unlike the OTP memory device using the antifuse type CMOS process, the nonvolatile semiconductor memory devices 100s and 200s do not use irreversible destruction by applying a high voltage to the oxide film forming the capacitor. Therefore, the threshold value can be verified as described above, and the reliability of the product can be improved.

100s, 200s, 101s, 201s ... Nonvolatile semiconductor memory device 11s ... Access control unit, 12s, 12sA ... Select address processing unit 13s, 13s-1, 13s-k ... MTP block unit 14s ... Write amplifier unit, 15s ... Sense amplifier Unit 16s ... Data input / output unit, 17s ... Input / output terminal 131s, 131sA ... Select decoder, 132s ... Data storage unit 133s, 133s-1, 133s- (m + 1) ... OTP array 21s ... Access control unit, 22s ... Select address processing Part, 23s ... row decoder 24s ... data storage part 1 ... p-type semiconductor substrate, 2 ... n-type well, 4 ... channel region 5, 7, 17 ... n-type diffusion layer, 15 ... p-type diffusion layer, 9 ... polysilicon 10, 11, 16, 18 ... contact 12, 13, 19 ... metal wiring 30 ... Memory elements 100-0, 100-1, 100-7, 100-10, 100-17 ... Memory blocks 100-20 to 100-27, 100-k0 to 100-k7 ... Memory blocks 200-1, 200-m + 1 ... Select decoder circuit 2000, 2000-1, 2000-k ... select decoder 300-1, 300-j ... column decoder, 400 ... data input conversion circuit 500-0, 500-7 ... sense amplifier, 600, 601 ... select address processing 700-1, 700-k, row decoder

Claims (15)

a storage area including n + 1 (m> 1, n ≧ m) n storage element groups storing n-bit width (n> 1) data;
A select decoder that selects any one of the other m memory element groups according to a select address stored in any one of the memory element groups in the storage area;
A select address processing unit that updates the select address and outputs the updated select address to the select decoder when data is written to any one of the other m memory element groups. A non-volatile semiconductor memory device. 2. Each of the m bits in the n bits of the storage element group that stores the select address is associated with whether or not the other m storage element groups have been written with data. The nonvolatile semiconductor memory device described. Each of the n 1-bit width memory elements constituting the n-bit width storage element group includes:
a MOS transistor formed on a p-type semiconductor substrate;
A transistor forming region in which a first n-type diffusion layer that forms a drain, a channel region, and a second n-type diffusion layer that forms a source are arranged in series,
A first metal wiring connected to the first n-type diffusion layer via a contact and disposed in the series direction;
A second metal wiring connected to the second n-type diffusion layer through a contact and disposed in a horizontal direction orthogonal to the series direction;
An n-type well disposed at a constant interval in the horizontal direction with the transistor formation region;
A third n-type diffusion layer formed on the n-type well;
A first p-type diffusion layer formed on the n-type well;
A third metal wiring that is connected to each of the third n-type diffusion layer and the first p-type diffusion layer via a contact, and forms a control gate disposed in the horizontal direction;
2. The device according to claim 1, further comprising: polysilicon arranged in parallel with the third metal wiring and covering the first p-type diffusions and a part of the channel region. 3. A nonvolatile semiconductor memory device according to 2. When writing data to the memory element,
A depletion layer is formed in the vicinity of the drain by applying a first voltage to the drain, applying a second voltage higher than the first voltage to the control gate, and applying a ground potential to the source. Generating hot electrons, injecting the hot electrons into the polysilicon forming the floating gate to change the threshold voltage high,
When reading data from the memory element,
A third voltage is applied to the drain, a voltage lower than the third voltage and higher than an initial threshold value before writing to the memory element is applied to the control gate, and a ground potential is applied to the source 4. The nonvolatile semiconductor memory device according to claim 3, wherein data is read based on whether or not a current flows between the drain and the source. 5. The storage area is
The memory elements are arranged in a matrix, and each of the arranged memory elements is arranged symmetrically with respect to the memory element adjacent in the row direction and in the column direction with the memory element adjacent in the column direction. Are symmetrically arranged,
Sharing the third n-type diffusion layer with one of the memory elements adjacent to the row direction;
The memory elements arranged in the same row direction share the second metal wiring and the third metal wiring,
The nonvolatile semiconductor memory device according to claim 4, wherein the memory elements arranged in the same column direction share the first metal wiring. a storage area including n + 1 (m> 1, n ≧ m) n storage element groups storing n (n> 1) bit width data;
A select address processing unit that reads out and stores a select address stored in one of the m + 1 storage element groups included in the storage area via the sense amplifier unit;
A select decoder that decodes the select address input from the select address processing unit to select one of the m + 1 storage element groups included in the storage area;
A sense amplifier unit that amplifies the n-bit width data output from the storage element group selected by the select decoder and outputs the amplified data to an input / output terminal via a data input / output unit;
A write amplifier unit that amplifies n-bit width data input from the input / output terminal via a data input / output unit, and writes and stores the amplified n-bit width data in the storage element group selected by the select decoder When,
When a read command is input from the outside, n-bit width data stored in one storage element group among the m + 1 storage element groups included in the storage area is input to the sense amplifier and the data input / output When a write command is input from the outside through the input / output terminal via the unit, n-bit width data input from the input / output terminal is passed through the data input / output unit and the write amplifier unit. A non-volatile semiconductor memory device, comprising: an access control unit that performs control of storing in one of the m + 1 storage element groups included in the storage area. When the write command is input from the outside,
The access control unit
The select address processing unit outputs the stored select address to the select decoder, causes the select decoder to select one storage element group according to the output select address, and the data input / output unit and N-bit width data input from the input / output terminal via the write amplifier unit is controlled to be output and stored in the storage element group selected by the select decoder;
Subsequently, the access control unit
The select address processing unit outputs a signal for selecting the storage element group storing the select address to the select decoder, and sends the updated select address to the storage element group via the write amplifier unit. Control to output and store the updated select address in the storage element group,
Furthermore, the access control unit
The select address processing unit outputs a signal for selecting the storage element group storing the select address to a select decoder, and the select address stored in the storage element group via the sense amplifier. Control to read and memorize,
When the read command is input from the outside,
The access control unit
The select address processing unit outputs the stored select address to the select decoder, causes the select decoder to select one storage element group according to the output select address, and selects the selected storage element The nonvolatile control according to claim 6, wherein n-bit width data stored in the group is read and output to the input / output terminal via the sense amplifier unit and the data input / output unit. Semiconductor memory device. The select address processing unit
A counter for encoding and storing the select address;
When updating the select address, the value stored in the counter is incremented by 1,
The select decoder
The value output by the counter of the select address processing unit is decoded to select only one selection signal corresponding to each of the m storage element groups, and the select address is selected from the select address processing unit. The nonvolatile semiconductor memory device according to claim 6, further comprising: a decoder that outputs a selection signal for selecting the storage element group when a signal for selecting the storage element group to be stored is input. . The select address processing unit
A shift register for storing the select address;
When updating the select address, shift the value stored in the shift register and shift in 1;
The select decoder
The boundary between the values 0 and 1 output from the shift register of the select address processing unit is detected, a selection signal corresponding to each of the m storage element groups is output, and the selection address processing unit outputs the selection signal. The nonvolatile memory according to claim 6, further comprising a decoder that outputs a selection signal for selecting the storage element group when a signal for selecting the storage element group for storing a select address is input. Semiconductor memory device. a storage region including n + 1 (m> 1, n ≧ m) memory storage groups each storing n (n> 1) bit width data, and one storage element among the m + 1 storage element groups K (k> 1) storage block units including a select decoder that decodes a select address for selecting one of the m storage element groups excluding the group;
A row decoder that decodes a row address input from the outside and selects one of the k storage block units;
Of the k storage block units, the n-bit width data read from one storage element group among the m + 1 storage element groups included in the storage block unit selected by the row decoder is amplified. And a sense amplifier unit that outputs to the data input / output unit,
The n-bit width data input from the data input / output unit is amplified and stored in one storage element group among the m + 1 storage element groups included in the storage block unit selected by the row decoder. A light amplifier section
The select address corresponding to each of the k storage block units is stored, and when the k storage block units newly store n-bit width data, the corresponding select address is updated and updated. A select address processing unit for outputting the select address to the select decoder of the storage block unit;
When a read command and the row address are input from the outside, the input row address is output to the row decoder, the select address stored in the select address processing unit is output, and the select decoder The n-bit width data read from the selected storage element group is controlled to be output from the input / output terminal via the sense amplifier section and the data input / output section, and a write command, the row address, Is input to the select decoder included in the storage area selected by the row decoder via the data input / output unit and the write amplifier unit. An access control unit that performs control to be stored in the selected memory element group. Equipment. i sense amplifiers provided for each of i (i> 1) data lines;
Storage elements are arranged in a matrix in a row direction and a column direction at intersections of a plurality of selection signal lines and a plurality of bit lines, and the storage elements are associated with the i data lines. A memory cell array composed of i memory blocks divided in a direction;
A select address processing unit for reading and storing a select address stored in a part of the memory cell array;
A plurality of switch elements for switching connection between a plurality of bit lines of each of the i memory blocks and the data lines corresponding to the i memory blocks;
A select decoder that activates one of the plurality of selection signal lines in accordance with a select address stored in the select address processing unit;
A plurality of column decoders for switching on / off the plurality of switch elements according to a select address stored in the select address processing unit;
A data input conversion circuit for applying a voltage to the i data lines in accordance with data written to the memory cell array input from the outside,
Each of the storage elements is
A transistor having a floating gate formed on a semiconductor substrate, wherein a control gate is connected to the selection signal line, a drain is connected to the bit line, and a source is commonly connected to an erase control circuit. Nonvolatile semiconductor memory device. i sense amplifiers provided for each of i (i> 1) data lines;
Storage elements are arranged in a matrix in a row direction and a column direction at intersections of a plurality of selection signal lines and a plurality of bit lines, and the storage elements are arranged in the column direction for each of the i data lines. A memory cell array composed of i × k memory blocks each divided into k (k> 1) in the row direction;
A select address processing unit for reading and storing a select address stored in a part of the memory cell array;
A plurality of switch elements for switching connection between each of the i data lines and the plurality of bit lines of the memory block divided in the column direction corresponding to the data lines;
K selections provided for each memory block group including i memory blocks divided in the row direction and activating one selection signal line among the plurality of selection signal lines corresponding to the memory block group. A decoder;
A plurality of column decoders for switching on / off the plurality of switch elements according to a select address stored in the select address processing unit;
A plurality of row decoders provided corresponding to the k select decoders, wherein one select decoder is selected from the k select decoders according to a row address inputted from the outside and operated;
A data input conversion circuit for applying a voltage to the i data lines in accordance with data written to the memory cell array input from the outside,
Each of the storage elements is
A transistor having a floating gate formed on a semiconductor substrate, wherein a control gate is connected to the selection signal line, a drain is connected to the bit line, and a source is commonly connected to an erase control circuit. Nonvolatile semiconductor memory device. By applying a first voltage to the drain of the transistor as the memory element, applying a second voltage higher than the first voltage to the control gate of the transistor, and setting the source of the transistor to the ground potential Write operation,
Further, a fourth voltage higher than the second voltage is applied to the drain of the transistor, the control gate of the transistor is set to the ground potential, and the source of the transistor is open or higher than the ground potential than the first voltage. Erase operation by applying a low voltage,
The ground potential or the fourth voltage is applied to the drain of the transistor, the ground potential or the third voltage is applied to the control gate of the transistor, and the ground potential is applied to the source of the transistor, or The first voltage is applied to the drain of the transistor, the ground potential is applied to the source of the transistor, and the voltage applied to the control gate of the transistor is gradually increased from the third voltage to a predetermined potential. The nonvolatile semiconductor memory device according to claim 11, wherein a write back operation is performed. After performing a write operation on the memory element and performing a test to confirm that the threshold value exceeds a predetermined write reference value, the erase operation is performed at least once, and the threshold value of the transistor serving as the memory element Whether or not the threshold value of the transistor is changed to a value equal to or lower than the initial threshold value, and when the threshold value of the transistor is lower than a predetermined criterion value, a write-back operation is performed at least once, and the threshold value is equal to or lower than the initial threshold value. And verifying the operation of the memory element depending on whether or not the determination reference value or more,
When the threshold value of the transistor does not fall below the initial threshold value even after performing the erasing operation a predetermined number of times, the memory element is determined to be defective,
14. The nonvolatile memory according to claim 13, wherein the memory element is determined to be defective when the threshold value of the transistor does not become equal to or higher than the determination criterion even if the write-back operation is performed a predetermined number of times. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 11, wherein the erase control circuit applies only a ground potential to a commonly connected source of the plurality of storage elements.

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