JP2010231249A - Information processor and memory control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor securing high reliability by safely switching from a current-use system to a stand-by system when a CPU of the current-use system malfunctions and to provide a memory control method for the information processor. <P>SOLUTION: The information processor has: a current-use system access controller for inhibiting or permitting write-in from the current-use system to a shared memory; a current-use system CPU for making the current-use system access controller permit write-in to the shared memory only when notification data which a stand-by system is notified are written in the shared memory, and for, when the notification data are written in the shared memory, notifying the stand-by system of write-in notification showing that the notification data has been already written in the shared memory; and a stand-by system CPU for, when being notified of the write-in notification by the current-use system CPU, reading the notification data from the shared memory, and for storing the notification data into the stand-by system memory, and for, when the current-use system is switched to the stand-by system, executing processing by using the notification data stored in the stand-by system memory. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a memory control method thereof.

  In recent years, an increasing number of information processing apparatuses adopt a redundant configuration so that operation can be continued even if a failure occurs. There are various types of redundant configurations depending on the application, but in general, an information processing device used in an environment where a momentary stoppage is not allowed is equipped with a plurality of CPUs, and the active CPU is When a failure occurs, the reliability is improved by switching to a standby CPU.

  In the information processing apparatus of the background art that adopts the redundant configuration, setting information for defining the operation of the information processing apparatus and information of data being processed are not shared between the active system and the standby system. For this reason, there is a problem that the operation of the information processing apparatus changes when the information processing apparatus is switched from the active system to the standby system. Further, when the information processing apparatus is used in a communication system, there is a problem that communication data being processed is lost when the information processing apparatus is switched from the active system to the standby system, and the continuity of the communication data is lost.

  In order to solve these problems, Patent Document 1 describes an information processing apparatus including a shared memory between an active CPU and a standby CPU. As a result, the active CPU accumulates a part of the data in the shared memory, and the standby CPU can read the data, so that the information processing apparatus can guarantee the continuity of the data.

Further, Patent Document 2 describes a method for preventing the data in the shared memory from being accidentally destroyed when the standby CPU operates.
JP-A-63-61338 JP-A-8-129508

  In Patent Document 1 and Patent Document 2 described above, when the active CPU runs away, incorrect data may be written to an unspecified area in the shared memory, and the data on the shared memory may be destroyed. In addition, when the active CPU stops while writing data to the shared memory, the data on the shared memory may become discontinuous. In such a case, the information processing apparatus operates based on the broken data when switching from the active system to the standby system, which may cause a serious problem such as abnormal operation or operation stop.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus and a memory control method therefor that can ensure high reliability and can safely switch from the active system to the standby system when an abnormality occurs in the active CPU. is there.

  In order to achieve the above object, an information processing apparatus of the present invention prohibits or permits a first shared memory accessible from an active system and a standby system, and writing from the active system to the first shared memory. A first access control device for the active system, a standby memory accessible only from the standby system, a standby interrupt controller for outputting an interrupt signal to the standby system in response to a request from the active system, and a standby system The active interrupt controller that outputs an interrupt signal to the active system in response to the request of the active system and the first access control device of the active system only when the notification data to be notified to the standby system is written to the first shared memory. When writing to the first shared memory is permitted and the notification data is written to the first shared memory, an interrupt signal is output to the standby interrupt controller. As a result, the active CPU that notifies the standby system of a write notification indicating that the notification data has been written to the first shared memory, and the write notification are notified from the active CPU. The notification data is read from the first shared memory, the notification data is stored in the standby memory, and an interrupt signal is output to the active interrupt controller, whereby the notification data is read from the first shared memory. A standby CPU that notifies the active system of a read notification indicating that it has been read from the shared memory, and executes processing using the notification data stored in the standby system memory when switching from the active system to the standby system Have

  According to the present invention, when an abnormality occurs in the active CPU of the information processing apparatus, it is possible to safely switch from the active system to the standby system, and to ensure high reliability.

  Next, the present invention will be described in detail with reference to the drawings.

  In the present invention, when the active CPU or standby CPU does not write to the shared memory, writing to the shared memory is prohibited. Further, the standby CPU preserves data by storing data notified from the active CPU in a standby memory that cannot be accessed by the active CPU.

(First embodiment)
Next, a first embodiment of the present invention will be described.

  FIG. 1 is a block diagram illustrating a configuration of the information processing apparatus according to the first embodiment.

  As shown in FIG. 1, the information processing apparatus 1 according to the first embodiment includes a CPU 10, a memory 11, a first access control device 12, and an interrupt controller 13 as an active system, and a CPU 20, It has a memory 21, a first access control device 22, and an interrupt controller 23, and has a recording medium 30, a recording medium interface unit 31, and a first shared memory 32 as common parts.

  The recording medium 30 stores an active program and a standby program for providing predetermined functions of the information processing apparatus 1. The recording medium 30 may be a magnetic disk, a semiconductor memory, an optical disk, or other recording medium.

  The working program recorded in the recording medium 30 is read into the working memory 11 by the working CPU 10 via the storage medium interface device 31. The CPU 10 executes processing according to the program read into the memory 11.

  On the other hand, the standby program recorded in the recording medium 30 is read by the standby CPU 20 into the standby memory 21 via the storage medium interface device 31. The CPU 20 executes processing according to the program read into the memory 21.

  The active memory 11 is a storage device for storing an active program and data processed by the active CPU 10. Only the active CPU 10 can access the memory 11, and the standby CPU 20 cannot access it.

  On the other hand, the standby memory 21 is a storage device for storing a standby program and data processed by the standby CPU 20. Only the standby CPU 20 can access the memory 21, and the active CPU 10 cannot access it.

  The first shared memory 32 is a memory used for information transmission between the active system and the standby system, and is accessible from both the CPU 10 and the CPU 20. As the first shared memory 32, for example, a RAM (Random Access Memory) having a multiport is used.

  The active first access control device 12 is a device for restricting the writing of the CPU 10 to the first shared memory 32, and can be realized by, for example, an LSI including various logic circuits. In the first access control device 12, the CPU 10 sets whether to allow or prohibit writing from the CPU 10 to the first shared memory 32. The first access control device 12 is normally set to prohibit writing to the first shared memory 32, and only when the CPU 10 writes to the first shared memory 32, the first shared memory 32 is set. 32 is set so as to allow writing to 32. When writing to the first shared memory 32 is permitted, when the CPU 10 accesses the first shared memory 32, the first access control device 12 sends a CS (chip select) signal to the first shared memory 32. Is output. Conversely, when writing to the first shared memory 32 is prohibited, the first access control device 12 fixes the CS signal to inactive, and the CPU 10 erroneously writes data to the first shared memory 32. To prevent that.

  On the other hand, the first access control device 22 of the standby system is a device for restricting writing to the first shared memory 32 of the CPU 20, and the method of realizing it is the same as that of the first access control device 12. .

  The standby interrupt controller 23 is a device that outputs an interrupt signal to the standby CPU 20 in response to a request from the active CPU 10. The active CPU 10 notifies the standby CPU 20 that data has been written to the first shared memory 32 by causing the standby controller 20 to output an interrupt signal to the interrupt controller 23.

  On the other hand, the active interrupt controller 13 is a device that outputs an interrupt signal to the active CPU 10 in response to a request from the standby CPU 20. The standby CPU 20 notifies the active CPU 10 that the data has been read from the first shared memory 32 by causing the interrupt controller 13 to output an interrupt signal to the active CPU 10.

  In the active system, the CPU 10, the recording medium 31, the memory 11, the first shared memory 32, the first access control device 12, and the interrupt controller 13 are connected via the internal bus 14.

  On the other hand, in the standby system, the CPU 20, the recording medium 31, the memory 21, the first shared memory 32, the first access control device 22 and the interrupt controller 23 are connected via the internal bus 24.

  Next, the data write processing procedure to the first shared memory 32 of the active CPU 10 shown in FIG. 1 will be described with reference to the flowchart of FIG.

  The CPU 10 executes the processing described below according to the working system program stored in the memory 11.

  When the process starts (step S1), the CPU 10 waits until data to be notified to the standby CPU 20 (hereinafter referred to as notification data) is generated (step S2). The notification data includes setting information for defining the operation of the information processing apparatus. When the setting information for defining the operation of the information processing apparatus is changed by the user, the information processing apparatus 1 stores the setting information in the working memory 11 so that the working CPU 10 can refer to the setting information. Further, the information processing apparatus 1 makes it possible for the standby CPU 20 to refer to the setting information in preparation for the occurrence of an abnormality in the active CPU 10 and switching to the standby system.

  When the notification data is generated, the CPU 10 determines whether or not the standby CPU 20 is reading data from the first shared memory 32 (step S3). Note that if the CPU 10 writes other notification data while the standby CPU 20 is reading the notification data, the notification data being read by the standby CPU 20 may be destroyed. Therefore, when the standby CPU 20 is reading the notification data from the first shared memory 32, the CPU 10 waits until the completion. In the first embodiment, the active CPU 10 informs the interrupt controller 23 to the standby CPU 20 that the notification data has been written to the first shared memory 32 (hereinafter referred to as write notification). Is output to the standby CPU 20. On the other hand, the standby CPU 20 indicates that the notification data has been read from the first shared memory 32 (hereinafter referred to as a read notification), and causes the interrupt controller 13 to output an interrupt signal to the active CPU 10. Notify the active CPU 10. Therefore, the standby CPU 20 receives data from the first shared memory 32 from the time when the standby CPU 20 notifies the standby CPU 20 of the write notification until the read notification is notified from the standby CPU 20. Is being read out. On the other hand, during other periods, it is determined that the standby CPU 20 is not reading data from the first shared memory 32.

  When the standby CPU 20 is not reading the notification data from the first shared memory 32, the CPU 10 sets the first access control device 12 to permit writing to the first shared memory 32 (step S4). . Subsequently, the CPU 10 writes the notification data to the first shared memory 32 (step S5). When the notification data is written to the first shared memory 32, the CPU 10 sets the first access control device 12 to prohibit writing to the first shared memory 32 (step S6).

  When the first access control device 12 is set to prohibit writing to the first shared memory 32, the CPU 10 causes the interrupt controller 23 to output an interrupt signal to the standby CPU 20, thereby sending a write notification to the standby system. The CPU 20 is notified (step S7). When the CPU 10 notifies the standby CPU 20 of the write notification, the CPU 10 proceeds to step S2 and waits until data to notify the standby system again occurs.

  Next, a data read processing procedure from the first shared memory 32 of the standby CPU 20 shown in FIG. 1 will be described with reference to the flowchart of FIG.

  The CPU 20 executes processing described below in accordance with a standby system program stored in the memory 21.

  When starting the processing (step S11), the CPU 20 first waits until a writing notification is notified from the active CPU 10 (step S12). Note that the write notification is made by receiving an interrupt signal from the interrupt controller 23.

  When the write notification is notified from the active CPU 10, the CPU 20 reads the notification data from the first shared memory 32 and stores the read notification data in the memory 21 (step S13). Since the standby CPU 20 does not write to the first shared memory 32, the first access control device 22 is set to always prohibit writing to the first shared memory 32. Subsequently, the CPU 20 causes the interrupt controller 13 to output an interrupt signal to the active CPU 10, thereby notifying the active CPU 10 of a read notification (step S14).

  When the CPU 20 notifies the active CPU 10 of the read notification, the CPU 20 proceeds to step S32 and waits again until the write notification is notified from the active CPU 10.

  The information processing apparatus according to the first embodiment restricts writing to the shared memory. When the active CPU or standby CPU is not writing data to the shared memory, writing to the shared memory is prohibited, so the possibility that the data in the shared memory is destroyed during operation is low.

  The standby CPU reads the data when the active CPU has finished writing the notification data to the shared memory, and stores the read data in the standby memory that cannot be accessed from the active system. When the active system is switched to the standby system, the standby CPU operates according to the data stored in the standby memory, not the data stored in the shared memory. If the active CPU is stopped while writing the notification data to the shared memory, the write notification is not notified to the standby CPU, and the standby CPU does not read the data from the shared memory. For this reason, there is no possibility that discontinuous data during writing is used in the standby system.

  The active CPU notifies the standby CPU of a write notification after prohibiting writing to the shared memory. That is, when the active CPU runs away and the notification data in the shared memory is destroyed, the write notification is not notified to the standby CPU, and the standby CPU does not read the data from the shared memory. For this reason, there is no possibility that the destroyed notification data is used in the standby system.

  As a result, the information processing apparatus according to the first embodiment can safely switch from the active system to the standby system when an abnormality occurs in the active CPU, thereby ensuring high reliability.

(Second Embodiment)
In the second embodiment, an information processing apparatus used in a communication system will be described.

  FIG. 4 is a block diagram illustrating a configuration of the information processing apparatus according to the second embodiment.

  As shown in FIG. 4, the information processing apparatus 1 according to the second embodiment includes a CPU 10, a memory 11, a first access control device 12, and an interrupt controller 13 as an active system, and a CPU 20, It has a memory 21, a first access control device 22, and an interrupt controller 23. As a common unit, a recording medium 30, a recording medium interface unit 31, a first shared memory 32, an external input / output device 34, and an external bus switch 35 Have

  CPU 10, memory 11, first access control device 12, interrupt controller 13, CPU 20, memory 21, first access control device 22, interrupt controller 23, recording medium 30, recording medium interface unit 31, first shared memory 32 The configuration is the same as that of the first embodiment.

  The external input / output device 34 is a device provided in a known communication device used in a communication system, which has a function of transmitting / receiving data to / from an external communication device. Examples of the external input / output device 34 include a LAN controller and a wireless LAN controller.

  The external bus switch 35 is a device that switches the connection destination of the external input / output device depending on whether the processing is performed in the active system or the standby system, and can be realized by an LSI including various logic circuits, for example.

  The external input / output device 34 and the external switch 35 are connected via an external bus 36.

  In the information processing apparatus according to the first embodiment, the example in which the setting information for defining the operation of the information processing apparatus is used as the notification data has been described. The information processing apparatus according to the second embodiment shows an example in which data received from an external communication device is used as notification data.

  When the information processing apparatus according to the second embodiment receives data from an external communication device, the information processing apparatus stores the received data in the memory 11, performs predetermined processing on the stored data, and performs the predetermined processing. Send the data to an external communication device. The predetermined process is a process that differs depending on the function of the information processing apparatus. For example, in order to transmit data received from an external communication device to another communication device, address information included in the data is changed. There is a process to rewrite.

  When the active CPU 10 receives data from an external communication device, it transmits the received data to the standby CPU 20 via the first shared memory 32. The standby CPU 20 stores the data received from the active CPU 10 in the memory 21.

  Further, when the active CPU 10 performs predetermined processing on the data received from the external communication device and transmits the data to the external communication device, the completion of the processing for the data is notified via the first shared memory 32. To the standby CPU 20. The standby CPU 20 erases the data notified of the completion of processing from the active CPU 10 from the memory 21.

  When an abnormality occurs in the active CPU 10, the information processing apparatus 1 switches from the active system to the standby system. When the information processing apparatus 1 is switched to the standby system, the standby CPU 20 switches the external bus switch 35 to the standby system. In addition, the standby CPU 20 performs a predetermined process on the data stored in the memory 21 and transmits the data subjected to the predetermined process to an external communication device.

  According to the second embodiment, when an information processing apparatus is used in a communication system, when an abnormality occurs in the active CPU, the continuity of communication data is reduced without losing data being processed. It becomes possible to keep.

(Third embodiment)
The information processing apparatus shown in the first embodiment uses an interrupt controller to notify the standby CPU that the active CPU has written the notification data to the shared memory. On the other hand, when the information processing apparatus has a plurality of shared memories, the standby CPU may be notified that the active CPU has written the notification data to the shared memory using the shared memory. In the third embodiment, a method of notifying the standby CPU that the active CPU has written the notification data to the shared memory using the shared memory without using the interrupt controller will be described.

  FIG. 5 is a block diagram illustrating a configuration of the information processing apparatus according to the third embodiment.

  As illustrated in FIG. 5, the information processing apparatus 1 according to the third embodiment includes a CPU 10, a memory 11, a first access control device 12, and a second access control device 15 as active systems, and a standby system. As a common unit, a recording medium 30, a recording medium interface unit 31, a first shared memory 32, and a second access control device 25 are included. A management shared memory 33 is included.

  The configurations of the CPU 10, the memory 11, the first access control device 12, the CPU 20, the memory 21, the first access control device 22, the recording medium 30, the recording medium interface unit 31, and the first shared memory 32 are the same as those in the first embodiment. The form is the same.

  The second shared memory 33 is a memory used to notify the standby CPU 20 that the active CPU 10 has written notification data to the first shared memory 32. The second shared memory 33 is accessible from both the CPU 10 and the CPU 20. As the second shared memory 33, for example, a RAM (Random Access Memory) having a multiport is used.

  The active second access control device 15 is a device for restricting writing to the second shared memory 33 by the CPU 10, and the method of realizing it is the same as that of the first access control device 12.

  On the other hand, the second access control device 25 of the standby system is a device for restricting writing to the second shared memory 33 by the CPU 20, and the method of realizing the same is the same as that of the first access control device 12. .

  In the active system, the CPU 10, the recording medium 31, the memory 11, the first shared memory 32, the first access control device 12, the second shared memory 33, and the second access control device 15 are connected via the internal bus 14. Is done.

  On the other hand, in the standby system, the CPU 20, the recording medium 31, the memory 21, the first shared memory 32, the first access control device 22, the second shared memory 33, and the second access control device 25 are connected via the internal bus 24. Connected.

  Next, the data write processing procedure to the first shared memory 32 of the active CPU 10 shown in FIG. 5 will be described with reference to the flowchart of FIG.

  The CPU 10 executes the processing described below according to the working system program stored in the memory 11.

  When starting the processing (step S21), the CPU 10 first waits until notification data is generated (step S22).

  When the notification data is generated, the CPU 10 determines whether or not the standby CPU 20 is reading data from the first shared memory 32 (step S23). In the information processing apparatus 1 according to the third embodiment, in order for the active CPU 10 to notify the standby CPU 20 that notification data has been generated, write information and read information are stored in the second shared memory 33. Prepare. Examples of write information and read information include a write counter and a read counter. The write counter and the read counter are initialized to 0 when the information processing apparatus is activated. The active CPU 10 counts up the write counter of the second shared memory 33 when the notification data is written in the first shared memory 32. On the other hand, when the standby CPU 20 reads the notification data from the first shared memory 32, it counts up the read counter of the second shared memory 33. When the value of the write counter is larger than the value of the read counter, the standby CPU 20 determines that notification data that has not been read exists in the first shared memory 32. Further, when the value of the write counter is larger than the value of the read counter, the active CPU 10 determines that the standby CPU 20 is reading the notification data from the first shared memory 32.

  When the standby CPU 20 is not reading the notification data from the first shared memory 32, the CPU 10 sets the first access control device 12 to permit writing to the first shared memory 32 (step S24). . Subsequently, the CPU 10 writes the notification data to the first shared memory 32 (step S25). When the notification data is written to the first shared memory 32, the CPU 10 sets the first access control device 12 to prohibit writing to the first shared memory 32 (step S26).

  Next, the CPU 10 sets the second access control device 15 to permit writing to the second shared memory 33 (step S27). Subsequently, the CPU 10 counts up the write counter of the second shared memory 33 (step S28). When the write counter of the second shared memory 33 is counted up, the CPU 10 sets the second access control device 15 to prohibit writing to the second shared memory 33 (step S29).

  When the CPU 10 sets the second access control device 15 to prohibit writing to the second shared memory 33, the CPU 10 proceeds to step S22 and waits again until notification data is generated.

  Next, a data read processing procedure from the first shared memory 32 of the standby CPU 20 shown in FIG. 5 will be described with reference to the flowchart of FIG.

  The CPU 20 executes processing described below in accordance with a standby system program stored in the memory 21.

  When starting the processing (step S31), the CPU 20 first waits until notification data is written in the first shared memory 32 by the active CPU 10 (step S32). Whether or not the notification data has been written to the first shared memory 32 by the active CPU 10 is determined by comparing the value of the write counter stored in the second shared memory 33 with the value of the read counter. To do.

  When the notification data is written in the first shared memory 32 by the active CPU 10, the CPU 20 reads the notification data from the first shared memory 32 and stores the read data in the memory 21 (step S33). Since the standby CPU 20 does not write to the first shared memory 32, the first access control device 22 is set to always prohibit writing to the first shared memory 32.

  Next, the CPU 20 sets the second access control device 25 to permit writing to the second shared memory 33 (step S34). Subsequently, the CPU 20 counts up the read counter of the second shared memory 33 (step S35). When the read counter of the second shared memory 33 is counted up, the CPU 20 sets the second access control device 25 to prohibit writing to the second shared memory 33 (step S36).

  When the CPU 20 sets the second access control device 25 to prohibit writing to the second shared memory 33, the CPU 20 proceeds to step S 32, and notification data is again sent to the first shared memory 32 by the active CPU 10. Wait until it is written.

  The information processing apparatus according to the third embodiment restricts writing to the shared memory. When the active CPU or standby CPU is not writing data to the shared memory, writing to the shared memory is prohibited, so the possibility that the data in the shared memory is destroyed during operation is low.

  The standby CPU reads the data when the active CPU has finished writing the notification data to the shared memory, and stores the read data in the standby memory that cannot be accessed from the active system. When the active system is switched to the standby system, the standby CPU operates according to the data stored in the standby memory, not the data stored in the shared memory. If the active CPU stops while writing notification data to the shared memory, the write information in the second shared memory is not updated, and the standby CPU does not read data from the shared memory. For this reason, there is no possibility that discontinuous data during writing is used in the standby system.

  Also, after the current CPU prohibits writing to the shared memory, it updates the write information of the second shared memory and notifies the standby CPU that the notification data has been written to the shared memory. That is, when the active CPU runs out of control and the notification data in the shared memory is destroyed, the write information in the second shared memory is not updated, and the standby CPU does not read data from the shared memory. For this reason, there is no possibility that the destroyed notification data is used in the standby system.

  That is, according to the third embodiment, it is possible to obtain the same effect as that of the information processing apparatus according to the first embodiment without using the interrupt controller shown in the first embodiment. . The information processing apparatus according to the third embodiment can safely switch from the active system to the standby system when an abnormality occurs in the active CPU, thereby ensuring high reliability.

(Fourth embodiment)
In the fourth embodiment, an information processing apparatus used in a communication system will be described.

  FIG. 8 is a block diagram illustrating the configuration of the information processing apparatus according to the fourth embodiment.

  As illustrated in FIG. 8, the information processing apparatus 1 according to the fourth embodiment includes a CPU 10, a memory 11, a first access control device 12, and a second access control device 15 as active systems, and a standby system. As a common unit, there are a recording medium 30, a recording medium interface unit 31, a first shared memory 32, a second access control unit 25, and a CPU 20, a memory 21, a first access control device 22 and a second access control device 25. A management shared memory 33, an external input / output device 34, and an external bus switch 35 are provided.

  CPU 10, memory 11, first access control device 12, second access control device 15, CPU 20, memory 21, first access control device 22, second access control device 25, recording medium 30, and recording medium interface unit The configurations of 31, the first shared memory 32 and the second shared memory 32 are the same as those of the third embodiment.

  The configurations of the external input / output device 34 and the external bus switch 35 are the same as those in the second embodiment.

  By adopting this configuration, the information processing apparatus according to the fourth embodiment has the same effects as the information processing apparatus according to the second embodiment without using the interrupt controller described in the second embodiment. Can be obtained. That is, in the information processing apparatus according to the fourth embodiment, when the information processing apparatus is used in a communication system, when an abnormality occurs in the active CPU, the communication data is not lost. Can be maintained.

It is a block diagram which shows the structure of the information processing apparatus of 1st Embodiment. 3 is a flowchart showing a data write processing procedure to a shared memory of an active CPU shown in FIG. 1. 3 is a flowchart showing a procedure for reading data from a shared memory of a standby CPU shown in FIG. 1. It is a block diagram which shows the structure of the information processing apparatus of 2nd Embodiment. It is a block diagram which shows the structure of the information processing apparatus of 3rd Embodiment. 6 is a flowchart showing a data write processing procedure to a shared memory of the active CPU shown in FIG. 5. 6 is a flowchart showing a data read processing procedure from a shared memory of a standby CPU shown in FIG. 5. It is a block diagram which shows the structure of the information processing apparatus of 4th Embodiment.

Explanation of symbols

1 Information processing apparatus 10, 20 CPU
11, 21 Memory 12, 22 First access control device 13, 23 Interrupt controller 14, 24 Internal bus 15, 25 Second access control device 30 Recording medium 31 Recording medium interface unit 32 First shared memory 33 Second Shared memory 34 External input / output device 35 External bus switch 36 External bus

Claims (5)

A first shared memory accessible from the active system and the standby system;
A first access control device for the working system that prohibits or permits writing to the first shared memory from the working system;
A standby memory accessible only from the standby system, and
A standby interrupt controller that outputs an interrupt signal to the standby system in response to a request from the active system;
An active interrupt controller that outputs an interrupt signal to the active system in response to a request from the standby system;
Only when the notification data to be notified to the standby system is written in the first shared memory, the active first access control device is allowed to write to the first shared memory, and the notification data is sent to the first shared memory. When writing to the shared memory, the standby interrupt controller outputs an interrupt signal to notify the standby system of a write notification indicating that the notification data has been written to the first shared memory. CPU,
When the write notification is notified from the active CPU, the notification data is read from the first shared memory, the notification data is stored in the standby memory, and an interrupt signal is sent to the active interrupt controller. Is output to the active system, and when the active system is switched to the standby system, the notification data is stored in the standby system memory. A standby CPU that executes processing using the notified data,
An information processing apparatus. A first shared memory that is accessible from the active system and the standby system, and stores notification data to be notified from the active system to the standby system;
A first access control device for the working system that prohibits or permits writing to the first shared memory from the working system;
A standby memory accessible only from the standby system, and
Write information indicating that the notification data has been written from the active system to the first shared memory and the notification data can be accessed from the active system and the standby system and read from the first shared memory in the standby system A second shared memory for storing read information indicating that it has been completed;
A second access control device for the working system that prohibits or permits writing to the second shared memory from the working system;
A second access control device for the standby system that prohibits or permits writing to the second shared memory from the standby system;
Only when the notification data is written to the first shared memory, the active first access control device is allowed to write to the first shared memory, and the write information is written to the second shared memory. The write information of the second shared memory is written only when the second access control device of the active system is allowed to write to the second shared memory and the notification data is written to the first shared memory. An active CPU that updates
Only when the read information is written to the second shared memory, the second access control device of the standby system is allowed to write to the second shared memory, and the write information is sent from the active CPU to the second shared memory. 2, the notification data is read from the first shared memory, the notification data is stored in the standby memory, the read information of the second shared memory is updated, When the system is switched from the standby system to the standby system, the standby system CPU executes processing using the notification data stored in the standby system memory;
An information processing apparatus. An external input / output device for transmitting / receiving data to / from an external communication device;
The information processing apparatus according to claim 1, further comprising: an external bus switch that switches a connection destination of the external input / output device depending on whether processing is performed in an active system or a standby system. A first shared memory accessible from the active system and the standby system;
A first access control device for the working system that prohibits or permits writing to the first shared memory from the working system;
A standby memory accessible only from the standby system, and
A standby interrupt controller that outputs an interrupt signal to the standby system in response to a request from the active system;
A memory control method for an information processing apparatus, comprising: an active interrupt controller that outputs an interrupt signal to an active system in response to a request from a standby system;
The active CPU is
Only when the notification data to be notified to the standby system is written to the first shared memory, the active first access control device is allowed to write to the first shared memory,
When the notification data is written to the first shared memory, a write notification indicating that the notification data has been written to the first shared memory is generated by causing the standby interrupt controller to output an interrupt signal. Notify the standby system,
The standby CPU
When the write notification is notified from the active CPU, the notification data is read from the first shared memory, the notification data is stored in the standby memory, and an interrupt signal is sent to the active interrupt controller. To notify the active system of a read notification indicating that the notification data has been read from the first shared memory,
A memory control method for executing a process using notification data stored in a memory of the standby system when the active system is switched to a standby system. A first shared memory that is accessible from the active system and the standby system, and stores notification data to be notified from the active system to the standby system;
A first access control device for the working system that prohibits or permits writing to the first shared memory from the working system;
A standby memory accessible only from the standby system, and
Write information indicating that the notification data has been written from the active system to the first shared memory and the notification data can be accessed from the active system and the standby system and read from the first shared memory in the standby system A second shared memory for storing read information indicating that it has been completed;
A second access control device for the working system that prohibits or permits writing to the second shared memory from the working system;
A second access control device for a standby system that prohibits or permits writing to the second shared memory from the standby system, and a memory control method for an information processing device, wherein the active CPU includes:
Only when the notification data is written to the first shared memory, the active first access control device is allowed to write to the first shared memory;
Only when the write information is written to the second shared memory, the second access control device of the active system is allowed to write to the second shared memory,
When the notification data is written to the first shared memory, the write information of the second shared memory is updated,
The standby CPU
Only when the read information is written to the second shared memory, the second access control device of the standby system is allowed to write to the second shared memory,
When the write information is written from the active CPU to the second shared memory, the notification data is read from the first shared memory, the notification data is stored in the standby memory, and the second Update the read information of the shared memory of
A memory control method for executing a process using notification data stored in a memory of the standby system when the active system is switched to a standby system.

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