JP2010226098A - Method of producing semiconductor device - Google Patents

Method of producing semiconductor device Download PDF

Info

Publication number
JP2010226098A
JP2010226098A JP2010037838A JP2010037838A JP2010226098A JP 2010226098 A JP2010226098 A JP 2010226098A JP 2010037838 A JP2010037838 A JP 2010037838A JP 2010037838 A JP2010037838 A JP 2010037838A JP 2010226098 A JP2010226098 A JP 2010226098A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bumps
adhesive film
insulating resin
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010037838A
Other languages
Japanese (ja)
Other versions
JP4984099B2 (en
Inventor
Kazunori Hamazaki
和典 濱崎
孝 ▲松▼村
Takashi Matsumura
Daisuke Sato
大祐 佐藤
Yasuhiro Suga
保博 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dexerials Corp
Original Assignee
Sony Chemical and Information Device Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemical and Information Device Corp filed Critical Sony Chemical and Information Device Corp
Priority to JP2010037838A priority Critical patent/JP4984099B2/en
Publication of JP2010226098A publication Critical patent/JP2010226098A/en
Application granted granted Critical
Publication of JP4984099B2 publication Critical patent/JP4984099B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/1623Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a pin of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29007Layer connector smaller than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2902Disposition
    • H01L2224/29034Disposition the layer connector covering only portions of the surface to be connected
    • H01L2224/29036Disposition the layer connector covering only portions of the surface to be connected covering only the central area of the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/3224Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/36Material effects
    • H01L2924/364Polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/381Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of producing a semiconductor device in which a semiconductor chip is flip-chip mounted on a board with a non-conductive resin film (NCF), wherein the method prevents the NCF from protruding at the time of hot pressing, prevents non-conductive resin and inorganic filler from entering the space between the bumps and the electrode pads, and wherein the acquired semiconductor device exhibits sufficient moisture/reflow resistance. <P>SOLUTION: The NCF has a size equivalent to 60 to 100% of the area of a region enclosed by a plurality of bumps 1 that are arranged at the periphery of the semiconductor chip 2 and has a minimum melt viscosity of 2×10<SP>2</SP>to 1×10<SP>5</SP>Pas. The NCF is temporarily bonded to a region enclosed by a plurality of electrodes 11 of the board 12 which correspond to the bumps 1. Next, the semiconductor chip 2 and the board 12 are positioned so that the bumps 1 and the corresponding electrodes 11 may face each other, and are hot pressed from the semiconductor chip 2 side. This causes the bumps 1 and the electrodes 11 to metallically bond, and melts and further thermally hardens the NCF. Consequently, a semiconductor device is acquired. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、ペリフェラル配置の複数のバンプを有する半導体チップを、絶縁性樹脂接着フィルムを介して基板にフリップチップ実装して半導体装置を取得する半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip having a plurality of peripherally arranged bumps is flip-chip mounted on a substrate via an insulating resin adhesive film to obtain a semiconductor device.

半導体チップを、導電粒子を含有する異方性導電接着フィルム(ACF)を用いて基板にフリップチップ実装して半導体装置を製造することが広く行われているが、配線ピッチのファイン化が進み、導電粒子の粒径と配線ピッチとの関係で、接続信頼性を確保することが困難になってきている。   Semiconductor devices are widely manufactured by flip-chip mounting a semiconductor chip on a substrate using an anisotropic conductive adhesive film (ACF) containing conductive particles. Due to the relationship between the particle size of the conductive particles and the wiring pitch, it has become difficult to ensure connection reliability.

このため、微細に作成可能な金スタッドバンプを半導体チップに設け、その半導体チップを、絶縁性樹脂接着フィルムを介して基板にフリップチップ実装することが行われるようになっている(特許文献1)。このような絶縁性樹脂接着フィルムを介してフリップチップ実装する場合、一般に、半導体チップと略同一の面積からわずかに大きな面積の絶縁性樹脂接着フィルムを基板に仮貼りした後、半導体チップと配線基板とを位置合わせし、半導体チップ側から熱プレスすることにより実装している。   For this reason, gold stud bumps that can be finely formed are provided on a semiconductor chip, and the semiconductor chip is flip-chip mounted on a substrate via an insulating resin adhesive film (Patent Document 1). . When flip-chip mounting is performed through such an insulating resin adhesive film, generally, an insulating resin adhesive film having a slightly larger area than a semiconductor chip is temporarily attached to the substrate, and then the semiconductor chip and the wiring board are mounted. And are mounted by hot pressing from the semiconductor chip side.

特開2008−203484号公報JP 2008-203484 A

しかしながら、特許文献1のようにフリップチップ実装した場合、図5に示すように、バンプ100を備えた半導体チップ101の外縁から、溶融した絶縁性樹脂接着フィルム(NCF)102がはみ出し、はみ出した樹脂が熱プレスボンダー103に付着し、熱プレスの際に圧力過大となり、意図した品質の半導体装置が得られない場合があるという問題があった。また、熱プレス後に、基板104の電極105と半導体チップ101のバンプ100との間から、絶縁性樹脂や無機フィラーを排除しきれないために、それらの間に満足の行く金属結合が形成できず、接続信頼性が大きく低下する場合があるという問題もあった。更に、吸湿リフロー後に、絶縁性樹脂接着フィルム102が外界に露出しているために、硬化不良や半導体チップ101の浮きの問題が生じ、この点からも接続信頼性が低下する場合があるという問題もあった。   However, when flip-chip mounting is performed as in Patent Document 1, as shown in FIG. 5, the melted insulating resin adhesive film (NCF) 102 protrudes from the outer edge of the semiconductor chip 101 including the bumps 100 and protrudes from the resin. Adheres to the hot press bonder 103 and the pressure becomes excessive during the hot pressing, and there is a problem that a semiconductor device of the intended quality may not be obtained. In addition, since the insulating resin and the inorganic filler cannot be completely excluded from between the electrode 105 of the substrate 104 and the bump 100 of the semiconductor chip 101 after hot pressing, a satisfactory metal bond cannot be formed between them. There is also a problem that connection reliability may be greatly reduced. Further, since the insulating resin adhesive film 102 is exposed to the outside after moisture absorption reflow, problems such as poor curing and floating of the semiconductor chip 101 occur, and the connection reliability may be lowered from this point as well. There was also.

本発明は、以上の従来の技術の課題を解決しようとするものであり、半導体チップと基板に絶縁性樹脂接着フィルムを使用してフリップチップ実装する半導体装置の製造方法において、熱プレスの際に、溶融した絶縁性樹脂接着フィルムのはみ出しと、バンプと電極パッドとの間に絶縁性樹脂や無機フィラーが介在することを防ぎ、得られる半導体装置が十分な耐吸湿リフロー性を示す製造方法を提供することを目的とする。   The present invention is intended to solve the above-described problems of the prior art, and in a method of manufacturing a semiconductor device in which a semiconductor chip and a substrate are flip-chip mounted using an insulating resin adhesive film, the heat pressing is performed. Providing a manufacturing method that prevents protrusion of molten insulating resin adhesive film and interposition of insulating resin and inorganic filler between bumps and electrode pads, and the resulting semiconductor device exhibits sufficient moisture absorption reflow resistance The purpose is to do.

本発明者は、半導体チップのペリフェラル配置された複数のバンプで囲まれた領域の面積に対する絶縁性樹脂接着フィルムの面積と絶縁性樹脂接着フィルムの最低溶融粘度とをそれぞれ特定範囲に設定することにより、上述の目的を達成できることを見出し、本発明を完成させるに至った。   The inventor sets the area of the insulating resin adhesive film and the minimum melt viscosity of the insulating resin adhesive film with respect to the area of the region surrounded by the plurality of bumps arranged on the periphery of the semiconductor chip to a specific range, respectively. The inventors have found that the above object can be achieved, and have completed the present invention.

即ち、本発明は、ペリフェラル配置の複数のバンプを有する半導体チップを、該バンプに対応した複数の電極を有する基板に、絶縁性樹脂接着フィルムを介してフリップチップ実装することにより半導体装置を製造する方法において、
半導体チップのペリフェラル配置された複数のバンプで囲まれた領域の面積の60〜100%に相当する大きさと、2×10〜1×10Pa・sの最低溶融粘度とを有する絶縁性樹脂接着フィルムを、該バンプに対応した基板の複数の電極で囲まれた領域に仮貼りし、該バンプとそれに対応する電極とが対向するように、半導体チップと基板とを位置合わせし、半導体チップ側から熱プレスすることにより、バンプと電極とを金属結合させ、絶縁性樹脂接着フィルムを溶融させ、更に熱硬化させることを特徴とする製造方法を提供する。
That is, the present invention manufactures a semiconductor device by flip-chip mounting a semiconductor chip having a plurality of peripherally arranged bumps on a substrate having a plurality of electrodes corresponding to the bumps via an insulating resin adhesive film. In the method
Insulating resin having a size corresponding to 60 to 100% of an area of a semiconductor chip surrounded by peripheral bumps and a minimum melt viscosity of 2 × 10 2 to 1 × 10 5 Pa · s An adhesive film is temporarily attached to a region surrounded by a plurality of electrodes on the substrate corresponding to the bump, and the semiconductor chip and the substrate are aligned so that the bump and the corresponding electrode face each other. Provided is a manufacturing method characterized in that bumps and electrodes are metal-bonded by hot pressing from the side, and the insulating resin adhesive film is melted and further thermally cured.

本発明の半導体装置の製造方法においては、半導体チップのペリフェラル配置された複数のバンプで囲まれた領域の面積の少なくとも60〜100%に相当する大きさと、2×10〜1×10Pa・sの最低溶融粘度とを有する絶縁性樹脂接着フィルムを、半導体チップの複数のバンプに対応する基板の複数の電極に囲まれた領域に仮貼りする。従って、半導体チップを基板に熱プレスした直後は、半導体チップのバンプとそれに対応した基板の電極パッドとの間には絶縁性樹脂接着フィルムが存在せず、また、半導体チップの外側に溶融した絶縁性樹脂接着フィルムがはみ出さないようにすることができる。更に、熱プレスの際、比較的低い圧力で行うことが可能となる。従って、すべてのバンプを対応する接続パッドに十分に金属結合させることができ、熱プレスボンダーへの溶融した樹脂の付着も防止できる。また、前述したように、熱プレス後に、樹脂のはみ出しを生じさせることなく、半導体チップのバンプと基板の電極との接合部を封止でき、耐吸湿リフロー性を向上させることが可能となる。よって、高い接続信頼性の半導体装置を得ることができる。 In the method of manufacturing a semiconductor device according to the present invention, a size corresponding to at least 60 to 100% of the area of a semiconductor chip surrounded by a plurality of peripherally arranged bumps and 2 × 10 2 to 1 × 10 5 Pa. An insulating resin adhesive film having a minimum melt viscosity of s is temporarily attached to a region surrounded by a plurality of electrodes of a substrate corresponding to a plurality of bumps of a semiconductor chip. Therefore, immediately after the semiconductor chip is hot-pressed on the substrate, there is no insulating resin adhesive film between the bumps of the semiconductor chip and the corresponding electrode pads of the substrate, and the insulation melted outside the semiconductor chip. The adhesive resin adhesive film can be prevented from protruding. Furthermore, it is possible to perform at a relatively low pressure during hot pressing. Accordingly, all the bumps can be sufficiently metal-bonded to the corresponding connection pads, and adhesion of the molten resin to the hot press bonder can be prevented. Further, as described above, after hot pressing, the junction between the bump of the semiconductor chip and the electrode of the substrate can be sealed without causing the resin to protrude, and the moisture absorption reflow resistance can be improved. Therefore, a semiconductor device with high connection reliability can be obtained.

バンプを備えた半導体チップの断面図である。It is sectional drawing of the semiconductor chip provided with bump. 半導体チップのバンプ側平面図である。It is a bump side top view of a semiconductor chip. 電極を備えた基板の断面図である。It is sectional drawing of the board | substrate provided with the electrode. 絶縁性樹脂接着フィルムを仮貼りした基板の断面図である。It is sectional drawing of the board | substrate which temporarily bonded the insulating resin adhesive film. 絶縁性樹脂接着フィルムを仮貼りした基板の絶縁性樹脂接着フィルム側平面図である。It is an insulating resin adhesive film side top view of the board | substrate which affixed the insulating resin adhesive film temporarily. 基板に半導体チップを熱プレスボンダーで熱プレス直後の説明図である。It is explanatory drawing immediately after heat-pressing a semiconductor chip to a board | substrate with a hot-press bonder. 基板に半導体チップを熱プレスボンダーで十分に熱プレスした後の説明図である。It is explanatory drawing after fully heat-pressing the semiconductor chip to a board | substrate with the hot press bonder. 従来技術のフリップチップ実装の説明図である。It is explanatory drawing of the flip chip mounting of a prior art.

本発明の半導体装置の製造方法を図面を参照しながら説明する。   A method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.

(1) まず、バンプ1を備えた半導体チップ2(図1A)と、電極11を備えた基板12(図2)と、絶縁性樹脂接着フィルム(NCF)とを用意する。 (1) First, a semiconductor chip 2 provided with bumps 1 (FIG. 1A), a substrate 12 provided with electrodes 11 (FIG. 2), and an insulating resin adhesive film (NCF) are prepared.

半導体チップ2において、バンプ1は半導体チップ2の外周縁近くにペリフェラル配置、即ち、一列のバンプ列として配置されている(図1B)。図1Bでは、一列のバンプ列であるが、二列以上のバンプ列であってもよい。   In the semiconductor chip 2, the bumps 1 are arranged near the outer periphery of the semiconductor chip 2 as a peripheral arrangement, that is, as a single row of bumps (FIG. 1B). In FIG. 1B, although it is one row of bumps, it may be two or more rows of bumps.

半導体チップ2やバンプ1としては特に制限はないが、バンプ1については、ファインピッチ化に高度に対応できる点から、金スタッドバンプを好ましく利用することができる。このような金スタッドバンプの大きさに関し、その高さは、好ましくは35〜100μm、より好ましくは35〜70μm、特に好ましくは35〜45μmである。また、その底径は、好ましくは10〜50μm、より好ましくは10〜40μm、特に好ましくは10〜20μmである。また、バンプ間ピッチは、好ましくは50〜200μm、より好ましくは50〜70μmである。   Although there is no restriction | limiting in particular as the semiconductor chip 2 and the bump 1, About the bump 1, the point which can respond | correspond highly to fine pitch can use a gold stud bump preferably. Regarding the size of such gold stud bumps, the height is preferably 35 to 100 μm, more preferably 35 to 70 μm, and particularly preferably 35 to 45 μm. The bottom diameter is preferably 10 to 50 μm, more preferably 10 to 40 μm, and particularly preferably 10 to 20 μm. Moreover, the pitch between bumps is preferably 50 to 200 μm, more preferably 50 to 70 μm.

半導体チップ2の外周縁とバンプ1との距離は、溶融した絶縁性樹脂のはみ出しを防ぐために、好ましくは0.07〜0.2mm、より好ましくは0.1〜0.15mmに設定する。   The distance between the outer peripheral edge of the semiconductor chip 2 and the bump 1 is preferably set to 0.07 to 0.2 mm, more preferably 0.1 to 0.15 mm in order to prevent the molten insulating resin from protruding.

基板12において、電極11は、接続すべき半導体チップ2のバンプ1(バンプ列)に対応するように配置される。そして、この複数の電極に囲まれた領域に絶縁性樹脂接着フィルム(NCF)が仮貼りされる。   In the substrate 12, the electrode 11 is arranged so as to correspond to the bump 1 (bump row) of the semiconductor chip 2 to be connected. Then, an insulating resin adhesive film (NCF) is temporarily attached to a region surrounded by the plurality of electrodes.

基板12や電極11としては、特に限定されず、例えば基板12としては、リジッド基板、フレキシブル基板、リジッドフレキシブル基板などを使用することができる。電極11としては、例えば、銅箔をランド状に成形し、表面にNi/Auメッキしたものを使用することができる。   The substrate 12 and the electrode 11 are not particularly limited, and for example, a rigid substrate, a flexible substrate, a rigid flexible substrate, or the like can be used as the substrate 12. As the electrode 11, for example, a copper foil formed into a land shape and Ni / Au plated on the surface can be used.

絶縁性樹脂接着フィルム(NCF)としては、半導体チップを基板に実装する際に使用される公知の絶縁性樹脂接着フィルムを使用することができ、例えば、エポキシ系硬化型樹脂組成物やアクリル系硬化型樹脂組成物をフィルム状に成形したものが挙げられる。これらは、熱硬化型のものを好ましく使用することができる。   As the insulating resin adhesive film (NCF), a known insulating resin adhesive film used when mounting a semiconductor chip on a substrate can be used. For example, an epoxy curable resin composition or an acrylic curable resin can be used. What formed the type | mold resin composition into the film form is mentioned. These are preferably thermosetting types.

エポキシ系熱硬化型樹脂組成物は、例えば、分子内に2つ以上のエポキシ基を有する化合物もしくは樹脂、エポキシ硬化剤、成膜成分等から構成される。   The epoxy thermosetting resin composition includes, for example, a compound or resin having two or more epoxy groups in the molecule, an epoxy curing agent, a film forming component, and the like.

分子内に2つ以上のエポキシ基を有する化合物もしくは樹脂としては、液状であっても、固体状であってもよく、ビスフェノールA型エポキシ樹脂やビスフェノールF型エポキシ樹脂などの二官能エポキシ樹脂、フェノールノボラック型エポキシ樹脂やクレゾールノボラック型エポキシ樹脂などのノボラック型エポキシ樹脂などを例示できる。また、3,4−エポキシシクロヘキセニルメチル−3´,4´−エポキシシクロヘキセンカルボキシレート等の脂環式エポキシ化合物も使用することができる。   The compound or resin having two or more epoxy groups in the molecule may be liquid or solid, bifunctional epoxy resin such as bisphenol A type epoxy resin or bisphenol F type epoxy resin, phenol, etc. Examples thereof include novolac type epoxy resins such as novolac type epoxy resins and cresol novolac type epoxy resins. In addition, alicyclic epoxy compounds such as 3,4-epoxycyclohexenylmethyl-3 ′, 4′-epoxycyclohexenecarboxylate can also be used.

エポキシ硬化剤としては、例えば、アミン系硬化剤、イミダゾール系硬化剤、酸無水物系硬化剤、スルホニウムカチオン系硬化剤等が挙げられる。硬化剤は潜在性であってもよい。   Examples of the epoxy curing agent include an amine curing agent, an imidazole curing agent, an acid anhydride curing agent, and a sulfonium cation curing agent. The curing agent may be latent.

成膜成分としては、例えば、エポキシ化合物やエポキシ樹脂と相溶するフェノキシ樹脂やアクリル樹脂を挙げることができる。   Examples of the film forming component include phenoxy resins and acrylic resins that are compatible with epoxy compounds and epoxy resins.

エポキシ系熱硬化型樹脂組成物は、必要に応じて公知の硬化促進剤、シランカップリング剤、金属捕捉剤、ブタジエンゴム等の応力緩和剤、シリカなどの無機フィラー、ポリイソシアネート系架橋剤、着色料、防腐剤、溶剤等を含有することができる。   The epoxy thermosetting resin composition is a known curing accelerator, silane coupling agent, metal scavenger, stress relaxation agent such as butadiene rubber, inorganic filler such as silica, polyisocyanate crosslinking agent, coloring as necessary. May contain additives, preservatives, solvents, and the like.

アクリル系熱硬化型樹脂組成物は、例えば、(メタ)アクリレートモノマー、成膜用樹脂、シリカなどの無機フィラー、シランカップリング剤、ラジカル重合開始剤等から構成される。   The acrylic thermosetting resin composition includes, for example, a (meth) acrylate monomer, a film-forming resin, an inorganic filler such as silica, a silane coupling agent, a radical polymerization initiator, and the like.

(メタ)アクリレートモノマーとしては、単官能(メタ)アクリレートモノマー、多官能(メタ)アクリレートモノマー、あるいはそれらにエポキシ基、ウレタン基、アミノ基、エチレンオキサイド基、プロピレンオキサイド基等を導入した変性単官能または多官能(メタ)アクリレートモノマーを使用することができる。また、本発明の効果を損なわない限り、(メタ)アクリレートモノマーとラジカル共重合可能な他のモノマー、例えば(メタ)アクリル酸、酢酸ビニル、スチレン、塩化ビニル等を併用することができる。   As the (meth) acrylate monomer, a monofunctional (meth) acrylate monomer, a polyfunctional (meth) acrylate monomer, or a modified monofunctional in which an epoxy group, a urethane group, an amino group, an ethylene oxide group, a propylene oxide group, or the like is introduced. Or a polyfunctional (meth) acrylate monomer can be used. Further, other monomers capable of radical copolymerization with the (meth) acrylate monomer, for example, (meth) acrylic acid, vinyl acetate, styrene, vinyl chloride and the like can be used in combination as long as the effects of the present invention are not impaired.

アクリル系熱硬化型樹脂組成物用の成膜用樹脂としては、フェノキシ樹脂、ポリビニルアセタール樹脂、ポリビニルブチラール樹脂、アルキル化セルロース樹脂、ポリエステル樹脂、アクリル樹脂、スチレン樹脂、ウレタン樹脂、ポリエチレンテレフタレート樹脂等が挙げられる。   Examples of the film-forming resin for the acrylic thermosetting resin composition include phenoxy resin, polyvinyl acetal resin, polyvinyl butyral resin, alkylated cellulose resin, polyester resin, acrylic resin, styrene resin, urethane resin, and polyethylene terephthalate resin. Can be mentioned.

ラジカル重合開始剤としては、ベンゾイルパーオキサイド、ジクミルパーオキサイド、ジブチルパーオキサイド等の有機過酸化物、アゾビスイソブチロニトリル、アゾビスバレロニトリル等のアゾビス系化合物を挙げることができる。   Examples of the radical polymerization initiator include organic peroxides such as benzoyl peroxide, dicumyl peroxide, and dibutyl peroxide, and azobis compounds such as azobisisobutyronitrile and azobisvaleronitrile.

アクリル系熱硬化型樹脂組成物は、必要に応じ、ブタジエンゴム等の応力緩和剤や、酢酸エチル等の溶剤、着色料、酸化防止剤、老化防止剤等を含有することができる。   The acrylic thermosetting resin composition can contain a stress relaxation agent such as butadiene rubber, a solvent such as ethyl acetate, a colorant, an antioxidant, an antioxidant, and the like, if necessary.

これらのエポキシ系熱硬化型樹脂組成物やアクリル系熱硬化型樹脂組成物から絶縁性樹脂接着フィルム(NCF)への成形は、公知の手法を使用して行うことができる。   Molding of these epoxy thermosetting resin compositions and acrylic thermosetting resin compositions into insulating resin adhesive films (NCF) can be performed using known methods.

以上説明した本発明で使用する絶縁性樹脂接着フィルム(NCF)については、その最低溶融粘度を2×10〜1×10Pa・s、好ましくは5×10〜5×10Pa・sに設定する必要がある。この範囲よりも低粘度となると、はみ出しが生ずる可能性が増加し、高粘度となるとバンプと電極との接合部を封止できなくなる可能性が増加するからである。 The insulating resin adhesive film (NCF) used in the present invention described above has a minimum melt viscosity of 2 × 10 2 to 1 × 10 5 Pa · s, preferably 5 × 10 2 to 5 × 10 4 Pa · s. s must be set. This is because if the viscosity is lower than this range, the possibility of the protrusion increases, and if the viscosity is high, the possibility that the joint between the bump and the electrode cannot be sealed increases.

また、絶縁性樹脂接着フィルム(NCF)の厚みは、薄すぎると取り扱い性が低下し、アンダーフィルの機能も果たせなくなり、厚すぎると熱プレスの際のはみ出しが生ずるので、好ましくは30〜70μm、より好ましくは35〜50μmである。   Further, if the thickness of the insulating resin adhesive film (NCF) is too thin, the handleability is deteriorated and the underfill function cannot be performed. If the thickness is too thick, the protrusion during hot pressing occurs, preferably 30 to 70 μm, More preferably, it is 35-50 micrometers.

(2) 次に、基板12に、2×10〜1×10Pa・sの最低溶融粘度を有する絶縁性樹脂接着フィルム(NCF)を仮貼りする(図3A)。この仮貼りの位置は、半導体チップ2のペリフェラル配置の複数のバンプ1で囲われた領域Rの内側に対応する位置である(図3B)。 (2) Next, an insulating resin adhesive film (NCF) having a minimum melt viscosity of 2 × 10 2 to 1 × 10 5 Pa · s is temporarily attached to the substrate 12 (FIG. 3A). This temporarily pasting position corresponds to the inside of the region R surrounded by the plurality of bumps 1 in the peripheral arrangement of the semiconductor chip 2 (FIG. 3B).

ここで、絶縁性樹脂接着フィルム(NCF)の大きさは、半導体チップ2のペリフェラル配置されたバンプ1で囲まれた領域Rの面積の60〜100%、好ましくは70〜90%に相当する大きさである。60%未満となると、半導体チップのバンプと基板の電極との接合部を封止できなくなる可能性が増大し、100%を超えるとバンプと電極との間に排除しきれない絶縁性樹脂や無機フィラーが残存するおそれがあり、しかも、熱プレス条件を低下させることができない。   Here, the size of the insulating resin adhesive film (NCF) corresponds to 60 to 100%, preferably 70 to 90%, of the area R of the semiconductor chip 2 surrounded by the peripherally arranged bumps 1. That's it. If it is less than 60%, the possibility that the joint between the bump of the semiconductor chip and the electrode of the substrate cannot be sealed increases, and if it exceeds 100%, an insulating resin or inorganic that cannot be completely excluded between the bump and the electrode. There is a possibility that the filler remains, and the hot press conditions cannot be lowered.

仮貼りの条件としては、絶縁性樹脂接着フィルムが実質的に硬化しないような条件で行うことが好ましく、具体的には、温度60〜70℃、圧力0.25〜1.0MPa、1〜3秒という条件を挙げることができる。   The temporary bonding is preferably performed under conditions such that the insulating resin adhesive film is not substantially cured. Specifically, the temperature is 60 to 70 ° C., the pressure is 0.25 to 1.0 MPa, and 1 to 3. The second condition can be mentioned.

(3) 次に、バンプ1とそれに対応する電極11とが対向するように、半導体チップ2と基板12とを位置合わせし、半導体チップ2側から、熱プレスボンダー30で熱プレスする(図4A)。この場合、まず、バンプ1と電極11とが、絶縁性樹脂接着フィルムを介さずに直接接触するので、両者の間に金属結合を形成させる。絶縁性樹脂接着フィルムについては、溶融させ、更に熱硬化させる。これにより、半導体装置を得ることができる。この熱プレスの際、溶融した絶縁性樹脂接着フィルムは、半導体チップ2の外縁に向かって拡がり、更に硬化する。硬化した絶縁性樹脂接着フィルムの周縁は、ペリフェラル配置の複数のバンプ1で囲まれた領域内のみに存在してもよいが、図4Bに示すように、ペリフェラル配置の複数のバンプ1と半導体チップ2の外縁との間に存在することが、バンプ1と電極11との接合部を封止できる点で好ましい。 (3) Next, the semiconductor chip 2 and the substrate 12 are aligned so that the bumps 1 and the corresponding electrodes 11 face each other, and are hot-pressed by the hot press bonder 30 from the semiconductor chip 2 side (FIG. 4A). ). In this case, first, since the bump 1 and the electrode 11 are in direct contact with each other without an insulating resin adhesive film, a metal bond is formed between them. The insulating resin adhesive film is melted and further thermally cured. Thereby, a semiconductor device can be obtained. During this hot pressing, the molten insulating resin adhesive film spreads toward the outer edge of the semiconductor chip 2 and is further cured. The peripheral edge of the cured insulating resin adhesive film may exist only in the region surrounded by the plurality of bumps 1 arranged in the peripheral, but as shown in FIG. 4B, the plurality of bumps 1 arranged in the peripheral and the semiconductor chip It is preferable that it exists between 2 outer edges at the point which can seal the junction part of the bump 1 and the electrode 11.

熱プレスボンダー30としては、従来よりフリップチップ実装の際に使用されている熱プレスボンダーを使用することができる。   As the hot press bonder 30, a hot press bonder conventionally used for flip chip mounting can be used.

このような熱プレスボンダー30を使用する本発明における熱プレス条件は、熱プレスの温度が好ましくは120〜270℃、より好ましくは170〜200℃である。圧力が好ましくは0.5〜2.5MPa、より好ましくは2.0〜2.5MPaである。特に、本発明の構成により、熱プレス時の圧力を、従来が10kg/ICであるところ、約1/3〜1/5の圧力に低減させることができる。   As for the hot press conditions in the present invention using such a hot press bonder 30, the temperature of the hot press is preferably 120 to 270 ° C, more preferably 170 to 200 ° C. The pressure is preferably 0.5 to 2.5 MPa, more preferably 2.0 to 2.5 MPa. In particular, according to the configuration of the present invention, the pressure during hot pressing can be reduced to about 1/3 to 1/5 of the conventional pressure of 10 kg / IC.

以上説明した本発明の製造方法により得られる半導体装置は、吸湿リフロー耐性を有する、優れた接続信頼性を示すものとなる。   The semiconductor device obtained by the manufacturing method of the present invention described above exhibits excellent connection reliability having moisture absorption reflow resistance.

以下、本発明を実施例により具体的に説明する。なお、以下の実施例において、NCF用組成物の最低溶融粘度は、コーン/プレート粘度計を用いて測定した。   Hereinafter, the present invention will be specifically described by way of examples. In the following Examples, the minimum melt viscosity of the NCF composition was measured using a cone / plate viscometer.

絶縁性樹脂接着フィルム(NCF)の製造例1〜5
表1の成分を均一に混合し、その混合物に、固形分濃度が60質量%となるようにトルエンを添加して混合してNCF用組成物を得た。得られた組成物を、バーコータを用いて剥離フィルム(ソニーケミカル&インフォメーションデバイス株式会社製)に塗布し、80℃のオーブン中で乾燥し、50μm厚の絶縁性樹脂接着フィルム(NCF)1〜5を得た。得られたNCFの最低溶融粘度(Pa・s)はコーン/プレート粘度計を使用して、昇温速度10℃/minにて測定し、得られた結果を表1に示す。なお、最低溶融粘度の観点から、本発明に適用可能な絶縁性樹脂接着フィルムはNCF2〜4である。
Production Examples 1 to 5 of Insulating Resin Adhesive Film (NCF)
The components in Table 1 were mixed uniformly, and toluene was added to the mixture so that the solid content concentration was 60% by mass to obtain an NCF composition. The obtained composition was applied to a release film (manufactured by Sony Chemical & Information Device Co., Ltd.) using a bar coater, dried in an oven at 80 ° C., and an insulating resin adhesive film (NCF) 1 to 5 having a thickness of 50 μm. Got. The minimum melt viscosity (Pa · s) of the obtained NCF was measured at a heating rate of 10 ° C./min using a cone / plate viscometer, and the obtained results are shown in Table 1. In addition, from the viewpoint of the minimum melt viscosity, the insulating resin adhesive film applicable to the present invention is NCF2-4.

Figure 2010226098
Figure 2010226098

実施例1〜7及び比較例1〜6
ペリフェラル配置の複数のAuスタッドバンプ(75〜85μm高;150μmピッチ)が設けられたられたLSIチップ(6.3mm角、0.1mm厚;バンプとLSIチップ周縁との平均距離0.1μm)の当該バンプに対応した電極(銅にニッケル/金メッキしたもの)を有する基板(MCL-E-679F、日立化成工業社)の電極に囲まれた領域に、表2に示すNCF面積率にカットしたNCF1〜5を、熱プレスボンダー(ソニーケミカル&インフォメーションデバイス社)で仮貼りした(温度60℃、圧力0.5MPa、加熱加圧時間3秒)。ここで、NCF面積率とは、複数のバンプで囲まれた領域の面積に対する切り出したNCFの面積の割合である。
Examples 1-7 and Comparative Examples 1-6
LSI chip (6.3 mm square, 0.1 mm thickness; average distance between bump and LSI chip periphery of 0.1 μm) provided with a plurality of peripheral Au stud bumps (75 to 85 μm high; 150 μm pitch) NCF1 cut into the NCF area ratio shown in Table 2 in the region surrounded by the electrode of the substrate (MCL-E-679F, Hitachi Chemical Co., Ltd.) having the electrode corresponding to the bump (nickel / gold plated copper) ˜5 were temporarily pasted with a hot press bonder (Sony Chemical & Information Device) (temperature 60 ° C., pressure 0.5 MPa, heating and pressing time 3 seconds). Here, the NCF area ratio is the ratio of the cut-out NCF area to the area of a region surrounded by a plurality of bumps.

(ボンダーへの樹脂付着の有無)
NCFを仮貼りした基板の電極面に対し、LSIチップのバンプ面を対向させ、位置合わせした後に、8mm角の熱プレスボンダー(ソニーケミカル&インフォメーションデバイス社)で熱プレス(本熱圧着:温度180℃、圧力2.5MPa、加熱加圧時間20秒)し、半導体装置を得た。得られた半導体装置について、熱プレスボンダーへの樹脂の付着の有無を目視にて観察した。得られた結果を表2に示す。
(Presence or absence of resin adhesion to the bonder)
The bump surface of the LSI chip is made to face and align with the electrode surface of the substrate on which NCF is temporarily attached, and then heat-pressed with an 8 mm square hot press bonder (Sony Chemical & Information Device Co., Ltd.). C., pressure 2.5 MPa, heating and pressing time 20 seconds) to obtain a semiconductor device. About the obtained semiconductor device, the presence or absence of adhesion of resin to a hot press bonder was observed visually. The obtained results are shown in Table 2.

(吸湿・リフロー耐性)
半導体装置を、温度85℃、湿度85%の条件下に168時間放置し、最高265℃のハンダリフロー炉に浸漬した後の導通抵抗値を測定し、0.13Ω未満をA、0.13Ω以上1.0Ω未満をB、1.0Ω以上をCと評価した。得られた結果を表2に示す。
(Hygroscopic / Reflow resistance)
The semiconductor device is left to stand for 168 hours at a temperature of 85 ° C. and a humidity of 85%, and after being immersed in a solder reflow furnace at a maximum of 265 ° C., the conduction resistance value is measured. A less than 0.13Ω is A, 0.13Ω or more Less than 1.0Ω was evaluated as B, and 1.0Ω or more was evaluated as C. The obtained results are shown in Table 2.

(初期導通抵抗及びPCT後の導通抵抗)
また、初期導通抵抗とPCT試験(121℃、湿度100%の環境下に120時間放置)後の導通抵抗を測定した。得られた結果(複数の測定結果のうちの最大の数値)を表2に示す。なお、1Ω以上の導通抵抗の場合をオープン(open)とした。実用上、導通抵抗は0.3Ω以下であることが望まれる。
(Initial conduction resistance and conduction resistance after PCT)
In addition, the initial conduction resistance and the conduction resistance after the PCT test (leaving for 120 hours in an environment of 121 ° C. and 100% humidity) were measured. Table 2 shows the obtained results (maximum numerical values among the plurality of measurement results). Note that the case of a conductive resistance of 1Ω or more was set to open. Practically, the conduction resistance is desired to be 0.3Ω or less.

Figure 2010226098
Figure 2010226098

表2からわかるように、NCF面積率が60〜100%に相当する大きさと、2×10〜1×10Pa・sの最低溶融粘度とを有するNCFを使用した実施例1〜7の半導体基板は、熱プレス時に絶縁性樹脂のはみ出しがなく、初期およびPCT試験後のそれぞれの時点での導電抵抗が低く、高い接続信頼性を実現していることがわかった。特に、実施例1〜3の場合、PCT試験後の導通抵抗が初期導通抵抗と大差なく、吸湿・リフロー耐性に優れていることがわかった。 As can be seen from Table 2, Examples 1 to 7 using NCF having a size corresponding to an NCF area ratio of 60 to 100% and a minimum melt viscosity of 2 × 10 2 to 1 × 10 5 Pa · s. It was found that the semiconductor substrate did not protrude the insulating resin at the time of hot pressing, had a low conductive resistance at each time after the initial stage and after the PCT test, and realized high connection reliability. In particular, in Examples 1 to 3, it was found that the conduction resistance after the PCT test was not significantly different from the initial conduction resistance and was excellent in moisture absorption and reflow resistance.

それに対し、比較例1、5の場合、NCFの最低溶融粘度が低すぎるため、比較例4の場合、NCFの面積率が高すぎるため、ボンダーへの樹脂の付着が観察され、吸湿・リフロー耐性も「C」評価であり、PCT後の導通抵抗も「open」であった。比較例4の場合、それらに加え、初期導通抵抗も「open」であった。比較例2、6の場合、NCFの最低溶融粘度が高すぎるため、吸湿・リフロー耐性が「C」評価であり、PCT後の導通抵抗が「open」であった。比較例3の場合、NCFの面積率が低すぎるため、吸湿・リフロー耐性が「C」評価であり、初期並びにPCT後の導通抵抗が共に「open」であった。   On the other hand, in the case of Comparative Examples 1 and 5, since the minimum melt viscosity of NCF is too low, in the case of Comparative Example 4, since the area ratio of NCF is too high, adhesion of the resin to the bonder is observed, and moisture absorption / reflow resistance is observed. Was also evaluated as “C”, and the conduction resistance after PCT was also “open”. In the case of Comparative Example 4, in addition to these, the initial conduction resistance was “open”. In Comparative Examples 2 and 6, since the minimum melt viscosity of NCF was too high, the moisture absorption / reflow resistance was evaluated as “C”, and the conduction resistance after PCT was “open”. In the case of Comparative Example 3, since the area ratio of NCF was too low, the moisture absorption / reflow resistance was “C” evaluation, and both the initial and post-PCT conduction resistances were “open”.

(低圧圧着性評価)
熱プレス時の圧力を0.5MPaに設定すること以外は、実施例1及び2の条件での測定をそれぞれ繰り返したところ、ボンダーへの樹脂の付着は観察されず、しかも、PCT試験後の導通抵抗も変化しなかった。従って、本発明の製造方法は、低圧圧着に適していることがわかった。
(Low-pressure crimping evaluation)
Except for setting the pressure during hot pressing to 0.5 MPa, the measurement under the conditions of Examples 1 and 2 was repeated. As a result, no adhesion of the resin to the bonder was observed, and conduction after the PCT test was performed. Resistance did not change. Therefore, it was found that the production method of the present invention is suitable for low-pressure crimping.

本発明の半導体装置の製造方法によれば、熱プレスの際に、NCFのはみ出しと、バンプと電極パッドとの間に絶縁性樹脂や無機フィラーが介在することを防ぎ、十分な耐吸湿リフロー性を示す半導体装置を提供することができる。   According to the method for manufacturing a semiconductor device of the present invention, it is possible to prevent an NCF from protruding and an insulating resin or an inorganic filler from interposing between a bump and an electrode pad during hot pressing, and sufficient moisture absorption reflow resistance. Can be provided.

1、100 バンプ
2、101 半導体チップ
11、105 電極
12、104 基板
30、103 熱プレスボンダー
NCF、102 絶縁性樹脂接着フィルム
R 領域
1, 100 Bump 2, 101 Semiconductor chip 11, 105 Electrode 12, 104 Substrate 30, 103 Hot press bonder NCF, 102 Insulating resin adhesive film R region

Claims (7)

ペリフェラル配置の複数のバンプを有する半導体チップを、該バンプに対応した複数の電極を有する基板に、絶縁性樹脂接着フィルムを介してフリップチップ実装することにより半導体装置を製造する方法において、
半導体チップのペリフェラル配置された複数のバンプで囲まれた領域の面積の60〜100%に相当する大きさと、2×10〜1×10Pa・sの最低溶融粘度とを有する絶縁性樹脂接着フィルムを、該バンプに対応した基板の複数の電極で囲まれた領域に仮貼りし、該バンプとそれに対応する電極とが対向するように、半導体チップと基板とを位置合わせし、半導体チップ側から熱プレスすることにより、バンプと電極とを金属結合させ、絶縁性樹脂接着フィルムを溶融させ、更に熱硬化させることを特徴とする製造方法。
In a method of manufacturing a semiconductor device by flip-chip mounting a semiconductor chip having a plurality of peripherally arranged bumps on a substrate having a plurality of electrodes corresponding to the bumps via an insulating resin adhesive film,
Insulating resin having a size corresponding to 60 to 100% of an area of a semiconductor chip surrounded by peripheral bumps and a minimum melt viscosity of 2 × 10 2 to 1 × 10 5 Pa · s An adhesive film is temporarily attached to a region surrounded by a plurality of electrodes on the substrate corresponding to the bump, and the semiconductor chip and the substrate are aligned so that the bump and the corresponding electrode face each other. A manufacturing method, wherein the bump and the electrode are metal-bonded by hot pressing from the side, the insulating resin adhesive film is melted, and further thermally cured.
半導体チップのペリフェラル配置されたバンプ列で囲まれた領域の面積の70〜90%を被覆するように、絶縁性樹脂接着フィルムを基板に仮貼りする請求項1記載の製造方法。   The manufacturing method according to claim 1, wherein the insulating resin adhesive film is temporarily attached to the substrate so as to cover 70 to 90% of the area of the region surrounded by the peripheral bump array of the semiconductor chip. 半導体チップのバンプが、高さ35〜100μmの金スタッドバンプである請求項1または2記載の製造方法。   The manufacturing method according to claim 1, wherein the bump of the semiconductor chip is a gold stud bump having a height of 35 to 100 μm. 絶縁性樹脂接着フィルムが、エポキシ系硬化型樹脂組成物またはアクリル系硬化型樹脂組成物を含有する請求項1〜3のいずれかに記載の製造方法。   The manufacturing method in any one of Claims 1-3 in which an insulating resin adhesive film contains an epoxy-type curable resin composition or an acryl-type curable resin composition. 絶縁性樹脂接着フィルムの厚みが、30〜70μmである請求項1〜4のいずれかに記載の製造方法。   The manufacturing method according to claim 1, wherein the insulating resin adhesive film has a thickness of 30 to 70 μm. 熱プレスの際に、溶融した絶縁性樹脂接着フィルムが、半導体チップの外縁に向かって拡がり、硬化した後にその周縁が、ペリフェラル配置の複数のバンプと半導体チップの外縁との間に存在する請求項1〜5のいずれかに記載の製造方法。   The molten insulating resin adhesive film spreads toward the outer edge of the semiconductor chip during hot pressing, and after being cured, the periphery thereof exists between the plurality of bumps in the peripheral arrangement and the outer edge of the semiconductor chip. The manufacturing method in any one of 1-5. 熱プレスの温度が120〜270℃であり、圧力が0.5〜2.5MPaである請求項1〜6のいずれかに記載の製造方法。   The temperature of hot press is 120-270 degreeC, and a pressure is 0.5-2.5 Mpa, The manufacturing method in any one of Claims 1-6.
JP2010037838A 2009-02-27 2010-02-23 Manufacturing method of semiconductor device Expired - Fee Related JP4984099B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010037838A JP4984099B2 (en) 2009-02-27 2010-02-23 Manufacturing method of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009045164 2009-02-27
JP2009045164 2009-02-27
JP2010037838A JP4984099B2 (en) 2009-02-27 2010-02-23 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2010226098A true JP2010226098A (en) 2010-10-07
JP4984099B2 JP4984099B2 (en) 2012-07-25

Family

ID=42665531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010037838A Expired - Fee Related JP4984099B2 (en) 2009-02-27 2010-02-23 Manufacturing method of semiconductor device

Country Status (7)

Country Link
US (2) US9368374B2 (en)
EP (1) EP2402985A4 (en)
JP (1) JP4984099B2 (en)
KR (1) KR101232409B1 (en)
CN (1) CN102334182B (en)
TW (1) TWI463575B (en)
WO (1) WO2010098324A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013035868A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Composition for electronic device
WO2013035869A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Underfill composition
WO2013035871A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Sealant composition for electronic device
WO2015037633A1 (en) * 2013-09-11 2015-03-19 デクセリアルズ株式会社 Underfill material and process for producing semiconductor device using same
US10043780B2 (en) 2016-07-06 2018-08-07 Samsung Electronics Co., Ltd. Semiconductor package
WO2023095184A1 (en) * 2021-11-23 2023-06-01 株式会社Fuji Circuit-forming method and circuit-forming apparatus

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102334182B (en) * 2009-02-27 2015-11-25 迪睿合电子材料有限公司 The manufacture method of semiconductor device
JP2012204631A (en) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd Semiconductor device, semiconductor device manufacturing method and electronic apparatus
JP6115060B2 (en) * 2012-09-21 2017-04-19 富士通株式会社 Manufacturing method of electronic device
JP6149223B2 (en) * 2013-04-18 2017-06-21 株式会社ディスコ How to stick a plate
US9496154B2 (en) 2014-09-16 2016-11-15 Invensas Corporation Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
US9929121B2 (en) * 2015-08-31 2018-03-27 Kulicke And Soffa Industries, Inc. Bonding machines for bonding semiconductor elements, methods of operating bonding machines, and techniques for improving UPH on such bonding machines
KR102366970B1 (en) 2017-05-16 2022-02-24 삼성전자주식회사 Semiconductor package
KR20200054747A (en) 2018-11-12 2020-05-20 삼성전자주식회사 Display module, display apparatus including the same and method of manufacturing display module
KR20210019323A (en) 2019-08-12 2021-02-22 삼성전자주식회사 Micro led display and manufacturing method thereof
KR102633142B1 (en) 2019-08-26 2024-02-02 삼성전자주식회사 Semiconductor package

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242208A (en) * 1997-02-25 1998-09-11 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH11233560A (en) * 1998-02-10 1999-08-27 Nitto Denko Corp Manufacture of semiconductor device
JP2003142522A (en) * 2001-10-31 2003-05-16 Nippon Avionics Co Ltd Ultrasonic mounting method for flip chip
JP2005264109A (en) * 2004-03-22 2005-09-29 Hitachi Chem Co Ltd Film-shaped adhesive and manufacturing method of semiconductor device using the same
JP2006265411A (en) * 2005-03-24 2006-10-05 Sekisui Chem Co Ltd Adhesive in sheet form or paste form, method for producing electronic component device and electronic component device
JP2007009022A (en) * 2005-06-29 2007-01-18 Sekisui Chem Co Ltd Sheet-like adhesive, method for producing electronic part device and electronic part device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
KR100443484B1 (en) * 1996-02-19 2004-09-18 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating the same
KR100502222B1 (en) * 1999-01-29 2005-07-18 마츠시타 덴끼 산교 가부시키가이샤 Electronic parts mounting method and device therefor
JP4097378B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
US6589802B1 (en) * 1999-12-24 2003-07-08 Hitachi, Ltd. Packaging structure and method of packaging electronic parts
DE60125999T2 (en) 2000-02-09 2007-11-08 Interuniversitair Micro-Elektronica Centrum Method for flip-chip mounting of semiconductor devices with adhesives
WO2001071854A1 (en) 2000-03-23 2001-09-27 Sony Corporation Electrical connection material and electrical connection method
JP2002184811A (en) 2000-12-11 2002-06-28 Sony Corp Electronic circuit device and its manufacturing method
JP4757398B2 (en) * 2001-04-24 2011-08-24 Okiセミコンダクタ株式会社 Manufacturing method of semiconductor device
TW558772B (en) * 2001-08-08 2003-10-21 Matsushita Electric Ind Co Ltd Semiconductor wafer, semiconductor device and fabrication method thereof
JP3886401B2 (en) * 2002-03-25 2007-02-28 ソニーケミカル&インフォメーションデバイス株式会社 Method for manufacturing connection structure
TWI317548B (en) * 2003-05-27 2009-11-21 Megica Corp Chip structure and method for fabricating the same
JP2004356150A (en) 2003-05-27 2004-12-16 Matsushita Electric Ind Co Ltd Method of mounting electronic component and electronic component package
US20050205981A1 (en) 2004-03-18 2005-09-22 Kabushiki Kaisha Toshiba Stacked electronic part
JP2008135719A (en) * 2006-10-31 2008-06-12 Sanyo Electric Co Ltd Semiconductor module, method for manufacturing semiconductor modules, and mobile device
JP5018117B2 (en) * 2007-02-15 2012-09-05 富士通セミコンダクター株式会社 Electronic component mounting method
JP2008203484A (en) 2007-02-20 2008-09-04 Epson Imaging Devices Corp Electrooptical device, package structure for flexible circuit board, and electronic equipment
JP5022756B2 (en) 2007-04-03 2012-09-12 オンセミコンダクター・トレーディング・リミテッド Mounting method of semiconductor chip
US20090230568A1 (en) * 2007-04-10 2009-09-17 Hiroyuki Yasuda Adhesive Film for Semiconductor and Semiconductor Device Therewith
JP2009032845A (en) 2007-07-26 2009-02-12 Sony Chemical & Information Device Corp Thermocompression bonding device and packaging method for electrical component
EP2206145A4 (en) * 2007-09-28 2012-03-28 Tessera Inc Flip chip interconnection with double post
CN102334182B (en) * 2009-02-27 2015-11-25 迪睿合电子材料有限公司 The manufacture method of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242208A (en) * 1997-02-25 1998-09-11 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH11233560A (en) * 1998-02-10 1999-08-27 Nitto Denko Corp Manufacture of semiconductor device
JP2003142522A (en) * 2001-10-31 2003-05-16 Nippon Avionics Co Ltd Ultrasonic mounting method for flip chip
JP2005264109A (en) * 2004-03-22 2005-09-29 Hitachi Chem Co Ltd Film-shaped adhesive and manufacturing method of semiconductor device using the same
JP2006265411A (en) * 2005-03-24 2006-10-05 Sekisui Chem Co Ltd Adhesive in sheet form or paste form, method for producing electronic component device and electronic component device
JP2007009022A (en) * 2005-06-29 2007-01-18 Sekisui Chem Co Ltd Sheet-like adhesive, method for producing electronic part device and electronic part device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9771500B2 (en) 2011-09-09 2017-09-26 Henkel Ag & Co. Kgaa Sealant composition for electronic device
WO2013035869A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Underfill composition
WO2013035871A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Sealant composition for electronic device
WO2013035868A1 (en) 2011-09-09 2013-03-14 ヘンケル・アクチェンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト・アウフ・アクチェン Composition for electronic device
KR101926899B1 (en) * 2011-09-09 2018-12-07 헨켈 아게 운트 코. 카게아아 Composition for electronic device
US9334429B2 (en) 2011-09-09 2016-05-10 Henkel Ag & Co. Kgaa Underfill sealant composition
US9576871B2 (en) 2011-09-09 2017-02-21 Henkel Ag & Co. Kgaa Composition for electronic device
WO2015037633A1 (en) * 2013-09-11 2015-03-19 デクセリアルズ株式会社 Underfill material and process for producing semiconductor device using same
US9957411B2 (en) 2013-09-11 2018-05-01 Dexerials Corporation Underfill material and method for manufacturing semiconductor device using the same
JP2015056500A (en) * 2013-09-11 2015-03-23 デクセリアルズ株式会社 Underfill material, and method for manufacturing semiconductor device using the same
US10043780B2 (en) 2016-07-06 2018-08-07 Samsung Electronics Co., Ltd. Semiconductor package
US10446525B2 (en) 2016-07-06 2019-10-15 Samsung Electronic Co., Ltd. Semiconductor package
WO2023095184A1 (en) * 2021-11-23 2023-06-01 株式会社Fuji Circuit-forming method and circuit-forming apparatus

Also Published As

Publication number Publication date
US20110237028A1 (en) 2011-09-29
CN102334182A (en) 2012-01-25
TW201041055A (en) 2010-11-16
EP2402985A1 (en) 2012-01-04
TWI463575B (en) 2014-12-01
CN102334182B (en) 2015-11-25
JP4984099B2 (en) 2012-07-25
US20160260683A1 (en) 2016-09-08
WO2010098324A1 (en) 2010-09-02
US9368374B2 (en) 2016-06-14
US9524949B2 (en) 2016-12-20
KR20110124262A (en) 2011-11-16
KR101232409B1 (en) 2013-02-12
EP2402985A4 (en) 2014-01-22
WO2010098324A9 (en) 2010-11-18

Similar Documents

Publication Publication Date Title
JP4984099B2 (en) Manufacturing method of semiconductor device
KR100932045B1 (en) Curable resin composition, adhesive epoxy resin paste, adhesive epoxy resin sheet, conductive connection paste, conductive connection sheet, and electronic component bonding body
KR101263623B1 (en) Adhesive film, connection method, and assembly
JP5509738B2 (en) Acrylic insulating adhesive
KR100467897B1 (en) A semiconductor device and a process for the production thereof
US7655107B2 (en) Method for establishing anisotropic conductive connection and anisotropic conductive adhesive film
JP2009041019A (en) Curable resin composition, adhesive epoxy resin paste, adhesive epoxy resin sheet, conductive connection paste, conductive connection sheet, and electronic component joined body
JP5944102B2 (en) Circuit connection material and connection structure using the same
JP6094884B2 (en) Manufacturing method of semiconductor device and acrylic resin composition for semiconductor sealing used therefor
CN101627465A (en) Adhesive film for semiconductor and semiconductor device using the adhesive film
JP6041463B2 (en) Epoxy resin composition, method for producing joined body using the same, and joined body
JP3911088B2 (en) Semiconductor device
JP6768188B2 (en) Adhesive composition for adhesive film and its manufacturing method
JP2000011760A (en) Anisotropic conductive composition and manufacture of anisotropic conductive member using it
JP2021093412A (en) Sheet-like resin composition for underfill and semiconductor device using the same
CN112154537A (en) Method for manufacturing semiconductor package
JP2017103304A (en) Adhesive for semiconductor, semiconductor device, and method for manufacturing the same

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120111

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120228

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120328

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120410

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150511

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees