JP2010226061A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Method of manufacturing semiconductor device, and semiconductor device Download PDF

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JP2010226061A
JP2010226061A JP2009074766A JP2009074766A JP2010226061A JP 2010226061 A JP2010226061 A JP 2010226061A JP 2009074766 A JP2009074766 A JP 2009074766A JP 2009074766 A JP2009074766 A JP 2009074766A JP 2010226061 A JP2010226061 A JP 2010226061A
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semiconductor
substrate
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supply amount
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JP5493421B2 (en
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Yusuke Matsukura
祐輔 松倉
Ryo Suzuki
僚 鈴木
Tetsuo Saito
哲男 齋藤
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Fujitsu Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem that conventional methods of hetero-bonding compound semiconductors find it difficult to obtain sufficient noise characteristics in a semiconductor device that deals with a minute signal current. <P>SOLUTION: A first semiconductor which is a III-V group compound semiconductor is grown on a substrate with a first substrate temperature. The growth of the first semiconductor is ceased, and the substrate temperature is changed to a second substrate temperature that is different from the first substrate temperature while a V group element material is supplied to the surface of the first semiconductor. A second semiconductor, which is a III-V group compound semiconductor different from the first semiconductor, is grown on the first semiconductor with the second substrate temperature. The process of changing the substrate temperature from the first substrate temperature to the second substrate temperature includes measuring the substrate temperatures and controlling supply amount to ensure that the supply amount of the V group element will be between a target lowest value and a target highest value of the supply amount at the measured substrate temperatures. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、基板上にIII族元素の原料とV族元素の原料とを供給して化合物半導体のヘテロ接合を含む半導体装置を製造する方法、及び半導体製造装置に関する。   The present invention relates to a method of manufacturing a semiconductor device including a heterojunction of a compound semiconductor by supplying a group III element source and a group V element source on a substrate, and a semiconductor manufacturing apparatus.

基板上に化合物半導体の膜を成長させる場合、化合物半導体の組成によって最適成長温度が異なる。このため、下層の膜を形成した後、一旦成長を中断させて、上層の膜の最適成長温度まで基板温度を変化させる。成長を中断させている期間、As等のV族元素の乖離を防止するために、V族元素の原料を供給しておくことが好ましい。   When a compound semiconductor film is grown on a substrate, the optimum growth temperature differs depending on the composition of the compound semiconductor. For this reason, after forming the lower layer film, the growth is temporarily interrupted, and the substrate temperature is changed to the optimum growth temperature of the upper layer film. In order to prevent the divergence of group V elements such as As during the period in which the growth is interrupted, it is preferable to supply a group V element raw material.

特開平4−164893号公報JP-A-4-164893 特開2003−51456号公報JP 2003-51456 A

従来の化合物半導体へテロ接合の製造方法では、微小な信号電流を扱う半導体装置において十分な雑音特性を得ることが困難である。信号電流が微小であるときの雑音特性を向上させることが求められている。   In a conventional method for manufacturing a compound semiconductor heterojunction, it is difficult to obtain sufficient noise characteristics in a semiconductor device that handles a minute signal current. There is a demand for improving noise characteristics when the signal current is very small.

上記課題を解決する半導体装置の製造方法は、
基板の上に、III−V族化合物半導体である第1の半導体を、第1の基板温度で成長させる工程と、
前記第1の半導体の成長を停止させ、該第1の半導体の表面に、V族元素の原料を供給しながら、前記基板の温度を、前記第1の基板温度とは異なる第2の基板温度に変化させる工程と、
前記第1の半導体の上に、該第1の半導体とは異なるIII−V族化合物半導体である第2の半導体を、前記第2の基板温度で成長させる工程と
を有し、
前記基板の温度を前記第1の基板温度から前記第2の基板温度に変化させる工程が、
前記基板の温度を測定する工程と、
V族元素の供給量が、測定された前記基板の温度における供給量の目標下限値と目標上限値との間に納まるように、該供給量を制御する工程と
を含む。
A method of manufacturing a semiconductor device that solves the above problems is as follows.
Growing a first semiconductor, which is a group III-V compound semiconductor, on a substrate at a first substrate temperature;
A second substrate temperature different from the first substrate temperature while stopping the growth of the first semiconductor and supplying a Group V element source to the surface of the first semiconductor. A process of changing to
Growing a second semiconductor, which is a group III-V compound semiconductor different from the first semiconductor, on the first semiconductor at the second substrate temperature;
Changing the temperature of the substrate from the first substrate temperature to the second substrate temperature;
Measuring the temperature of the substrate;
Controlling the supply amount so that the supply amount of the group V element falls within the target lower limit value and the target upper limit value of the supply amount at the measured substrate temperature.

上記課題を解決する半導体製造装置は、
成長用基板を収容するチャンバと、
前記チャンバ内に、III族元素の原料及びV族元素の原料を、制御された供給量で供給する原料供給装置と、
前記チャンバに収容された成長用基板の温度を測定する温度測定器と、
基板温度ごとに、V族元素の供給量の目標下限値及び目標上限値を記憶しており、前記温度測定器による測定結果に基づいて、V族元素の供給量が前記目標下限値及び目標上限値の間に納まるように、前記原料供給装置を制御する制御装置と
を有する。
A semiconductor manufacturing apparatus that solves the above problems
A chamber containing a growth substrate;
A raw material supply device for supplying a group III element raw material and a group V element raw material in a controlled supply amount into the chamber;
A temperature measuring device for measuring the temperature of the growth substrate housed in the chamber;
For each substrate temperature, the target lower limit value and the target upper limit value of the supply amount of the group V element are stored, and based on the measurement result by the temperature measuring device, the supply amount of the group V element is the target lower limit value and the target upper limit value. And a control device for controlling the raw material supply device so as to fall between the values.

基板温度を変化させる期間に、V族元素の供給量を上述のように制御することにより、雑音特性に優れた半導体装置が得られる。   By controlling the supply amount of the group V element as described above during the period of changing the substrate temperature, a semiconductor device having excellent noise characteristics can be obtained.

実施例で用いられるMBE装置の概略図である。It is the schematic of the MBE apparatus used in an Example. (2A)は、実施例1による方法で製造される半導体装置の断面図及び成長温度を示すグラフであり、(2B)は、基板温度ろAs供給量の好適な範囲との好適な範囲を示すグラフである。(2A) is a cross-sectional view of the semiconductor device manufactured by the method according to Example 1 and a graph showing the growth temperature, and (2B) shows a preferred range with a preferred range of substrate temperature and As supply amount. It is a graph. 実施例1による方法で製造された半導体装置の雑音特性の測定結果を、従来の方法で製造された同一構造の半導体装置の雑音特性と対比させて示すグラフである。It is a graph which compares the measurement result of the noise characteristic of the semiconductor device manufactured by the method by Example 1, with the noise characteristic of the semiconductor device of the same structure manufactured by the conventional method. 実施例2による半導体装置の製造方法の製造途中段階における断面図、及び完成時の断面図である。FIG. 6 is a cross-sectional view in the middle of manufacturing of a semiconductor device manufacturing method according to a second embodiment and a cross-sectional view when completed. 実施例3による半導体装置の製造方法の製造途中段階における断面図、及び完成時の断面図である。FIG. 10 is a cross-sectional view in the middle of manufacturing of a method for manufacturing a semiconductor device according to Example 3, and a cross-sectional view when completed.

図1に、実施例による半導体装置の製造方法で用いられる分子線エピタキシ(MBE)装置の概略図を示す。   FIG. 1 is a schematic diagram of a molecular beam epitaxy (MBE) apparatus used in a method for manufacturing a semiconductor device according to an embodiment.

チャンバ10内にステージ11が収容されている。チャンバ10内が、排気管14を介して真空排気される。ステージ11に、基板28が保持される。ステージ11内にヒータ16が配置されており、基板28を加熱することができる。温度測定器13が、基板28の温度を測定し、測定結果が制御装置25に入力される。温度測定器13には、例えば放射温度計(パイロメータ)が用いられる。また、ヒータ16は、制御装置25により制御される。   A stage 11 is accommodated in the chamber 10. The inside of the chamber 10 is evacuated through the exhaust pipe 14. A substrate 28 is held on the stage 11. A heater 16 is disposed in the stage 11 so that the substrate 28 can be heated. The temperature measuring device 13 measures the temperature of the substrate 28, and the measurement result is input to the control device 25. For the temperature measuring device 13, for example, a radiation thermometer (pyrometer) is used. The heater 16 is controlled by the control device 25.

ステージ11に対向する位置に原料供給装置20が取り付けられている。原料供給装置20には、例えばクヌードセンセル(Kセル)が用いられる。Al、Ga、In、As、Si等の原料ごとにKセルが準備される。供給量制御部21が、制御装置25からの指令を受けて各Kセルの温度を制御することにより、原料ごとに供給量を変化させることができる。   A raw material supply device 20 is attached at a position facing the stage 11. For the raw material supply device 20, for example, Knudsen cell (K cell) is used. A K cell is prepared for each raw material such as Al, Ga, In, As, and Si. The supply amount control unit 21 can change the supply amount for each raw material by receiving a command from the control device 25 and controlling the temperature of each K cell.

Kセルに代えて、バルブセルを用いてもよい。バルブセルを用いる場合には、バルブの開度を調節することにより、原料の供給量が制御される。成長用原料としてガスソースを用いる場合には、原料供給装置20にガスセルが用いられる。ガスセルを用いる場合には、バルブの開度やガスセル内の圧力を調節することにより、原料の供給量が制御される。   A valve cell may be used instead of the K cell. When using a valve cell, the supply amount of the raw material is controlled by adjusting the opening of the valve. When a gas source is used as the growth raw material, a gas cell is used for the raw material supply apparatus 20. When using a gas cell, the supply amount of the raw material is controlled by adjusting the opening of the valve and the pressure in the gas cell.

原料供給装置20から見てステージ11の後方にビーム強度計12が配置されている。ビーム強度計12には、例えば電離真空計が用いられる。ビーム強度計12は、ステージ11をビーム経路から退避させた状態で、分子線のビーム強度を測定することができる。ビーム強度計12による測定結果が制御装置25に入力される。分子線のビーム強度は、等価圧力に換算することができる。   A beam intensity meter 12 is disposed behind the stage 11 when viewed from the raw material supply device 20. For the beam intensity meter 12, for example, an ionization vacuum gauge is used. The beam intensity meter 12 can measure the beam intensity of the molecular beam with the stage 11 retracted from the beam path. A measurement result by the beam intensity meter 12 is input to the control device 25. The beam intensity of the molecular beam can be converted into an equivalent pressure.

チャンバ10に、反射高速電子回折(RHEED)測定器15が取り付けられている。RHEED測定器15は、電子銃15A及び回折ビーム検出器15Bを含む。RHEED用電子銃15Aは、基板28に電子ビームを入射させる。基板28で回折された電子ビームが、検出器15Bにより検出される。検出結果が制御装置25に入力される。   A reflection high energy electron diffraction (RHEED) measuring instrument 15 is attached to the chamber 10. The RHEED measuring instrument 15 includes an electron gun 15A and a diffracted beam detector 15B. The RHEED electron gun 15 </ b> A causes an electron beam to enter the substrate 28. The electron beam diffracted by the substrate 28 is detected by the detector 15B. The detection result is input to the control device 25.

図2A〜図3を参照して、実施例1による半導体装置の製造方法について説明する。   With reference to FIGS. 2A to 3, a method of manufacturing a semiconductor device according to the first embodiment will be described.

GaAs基板30の上に、基板温度Tの条件で、MBEによりAlGaAs層31を成長させる。温度Tは、例えば600℃である。その後、AlGaAs層31の成長を停止させ、As原料を供給した状態で、基板温度をTまで低下させる。温度Tは、例えば500℃である。 On a GaAs substrate 30, substrate temperature of T 2, growing the AlGaAs layer 31 by MBE. Temperature T 2 is, for example, 600 ° C.. Thereafter, the growth of the AlGaAs layer 31 is stopped, and the substrate temperature is lowered to T 1 while the As raw material is supplied. Temperatures T 1 is, for example, 500 ° C..

基板温度Tの条件で、InGaAs層32をMBEにより成長させる。さらに、AlGaAs層33を成長させる。その後、As原料を供した状態で、基板温度をTまで上昇させる。基板温度Tの条件で、AlGaAs層34を、MBEにより成長させる。 Substrate temperature of T 1, an InGaAs layer 32 is grown by MBE. Further, an AlGaAs layer 33 is grown. Thereafter, the substrate temperature is raised to T 2 with the As raw material provided. Substrate temperature of T 2, the AlGaAs layer 34 is grown by MBE.

これらの層の成長時に、Al、Ga、In、及びAsの原料として、例えば固体原料を用いる。AlGaAs層33は、基板温度を600℃近傍まで上昇させたときのInGaAs層32内のInの乖離を防止するために配置される。従って、AlGaAs層33の厚さは、下地のInGaAs層32内のInの乖離を防止するのに十分な厚さ、例えば5nm程度であればよい。なお、InGaAs層32の上の層の成長条件によっては、AlGaAs層33を形成しなくてもよい。   During the growth of these layers, for example, solid materials are used as materials for Al, Ga, In, and As. The AlGaAs layer 33 is disposed to prevent the separation of In in the InGaAs layer 32 when the substrate temperature is raised to around 600 ° C. Therefore, the thickness of the AlGaAs layer 33 may be a thickness sufficient to prevent the separation of In in the underlying InGaAs layer 32, for example, about 5 nm. Depending on the growth conditions of the layer on the InGaAs layer 32, the AlGaAs layer 33 may not be formed.

図2Bに、基板表面にAlGaAsが露出している状態で成長を中断しているときの、基板温度とAs供給量との好適な範囲を示す。横軸はAsの供給量を表し、縦軸は基板温度を表す。成長中断中における基板温度とAs供給量とを「中断中条件」ということとする。細い実線37L及び37Uが、それぞれ好適な中断中条件のAs供給量下限値及び上限値に対応する。以下、As供給量下限値の対応する線37L及びAs供給量上限値に対応する線37Uの決定方法について説明する。   FIG. 2B shows a preferred range of the substrate temperature and the As supply amount when the growth is interrupted with AlGaAs exposed on the substrate surface. The horizontal axis represents the supply amount of As, and the vertical axis represents the substrate temperature. The substrate temperature and As supply amount during the growth interruption are referred to as “interruption conditions”. The thin solid lines 37L and 37U correspond to the As supply amount lower limit value and the upper limit value, respectively, of the preferred interrupting conditions. Hereinafter, a method of determining the line 37L corresponding to the As supply amount lower limit value and the line 37U corresponding to the As supply amount upper limit value will be described.

図1に示したMBE装置のステージ11に評価用の基板28を装着する。基板28にAlGaAs層を形成する。基板温度をTに保ち、As供給量を変化させながら、RHEED測定器15でAlGaAs層の結晶状態を測定する。測定結果から、AlGaAs層の表層部の結晶状態を評価することができる。 An evaluation substrate 28 is mounted on the stage 11 of the MBE apparatus shown in FIG. An AlGaAs layer is formed on the substrate 28. Maintaining the substrate temperature T 1, while changing the As feed rate to measure the crystalline state of the AlGaAs layer in RHEED measurement instrument 15. From the measurement result, the crystal state of the surface layer portion of the AlGaAs layer can be evaluated.

基板温度をTから、ある刻み幅ΔTだけ上昇させて、同様の評価を行う。この評価を、基板温度がTになるまで繰り返す。この評価により、AlGaAs層の結晶状態が良好と判断された領域が、As供給量下限値に対応する線37LとAs供給量上限値に対応する線37Uの間の領域に相当する。As供給量下限値に対応する線37LよりもAs供給量が少ない状態、または基板温度が高い状態、すなわちAs供給量下限値に対応する線37Lの左上の領域では、Asの乖離が進み、AlGaAs層の結晶状態が悪くなる。また、As供給量上限値に対応する線37UよりもAs供給量が多い状態、または基板温度が低い状態、すなわちAs供給量上限値に対応する線37Uの右下の領域では、Asが過剰になるために、AlGaAs層を半導体装置に応用する観点から、その表面状態が好ましくない状態になる。 The same evaluation is performed by raising the substrate temperature from T 1 by a certain step size ΔT. This evaluation is repeated until the substrate temperature is T 2. The region in which the crystal state of the AlGaAs layer is determined to be good by this evaluation corresponds to the region between the line 37L corresponding to the As supply amount lower limit value and the line 37U corresponding to the As supply amount upper limit value. In a state where the As supply amount is lower than the line 37L corresponding to the As supply amount lower limit value, or in a state where the substrate temperature is high, that is, in the upper left region of the line 37L corresponding to the As supply amount lower limit value, the As divergence proceeds. The crystalline state of the layer becomes poor. In the state where the As supply amount is higher than the line 37U corresponding to the As supply amount upper limit value or the substrate temperature is low, that is, in the lower right region of the line 37U corresponding to the As supply amount upper limit value, As is excessive. Therefore, from the viewpoint of applying the AlGaAs layer to a semiconductor device, the surface state is not preferable.

AlGaAs層31は、基板温度T、As供給量Sの条件(図2Bに示した成膜条件31Pに相当)で成膜され、InGaAs層32は、基板温度T、As供給量Sの条件(図2Bに示した成膜条件32Pに相当)で成膜される。基板温度を昇降させる際に、基板温度及びAs供給量が、As供給量下限値に対応する線37LとAs供給量上限値に対応する線37Uとの間に納まるように、中断中条件を制御することが好ましい。なお、プロセスマージンを考慮すると、中断中条件の制御目標値を、As供給量下限値に対応する線37LとAs供給量上限値に対応する線37Uとで挟まれた領域よりも内側に設定することが好ましい。 The AlGaAs layer 31 is formed under the conditions of the substrate temperature T 2 and the As supply amount S 2 (corresponding to the film formation condition 31P shown in FIG. 2B), and the InGaAs layer 32 is the substrate temperature T 1 and As supply amount S 1. The film is formed under the conditions (corresponding to the film forming condition 32P shown in FIG. 2B). When raising or lowering the substrate temperature, the suspended condition is controlled so that the substrate temperature and the As supply amount fall between the line 37L corresponding to the As supply amount lower limit value and the line 37U corresponding to the As supply amount upper limit value. It is preferable to do. When the process margin is taken into consideration, the control target value for the interruption condition is set inside the region sandwiched between the line 37L corresponding to the As supply amount lower limit value and the line 37U corresponding to the As supply amount upper limit value. It is preferable.

実施例1では、中断中条件が、As供給量の目標下限値に対応する線36Lと目標上限値に対応する線36Uとの間に納まるように、中断中条件を制御する。As供給量の目標下限値に対応する線36Lは、As供給量下限値に対応する線37LよりもややAs過剰側に設定され、目標上限値に対応する線36Uは、As供給量上限値に対応する線37UよりもややAs過少側に設定される。   In the first embodiment, the interrupting condition is controlled so that the interrupting condition falls between the line 36L corresponding to the target lower limit value of the As supply amount and the line 36U corresponding to the target upper limit value. The line 36L corresponding to the target lower limit value of the As supply amount is set slightly on the As excess side than the line 37L corresponding to the As supply amount lower limit value, and the line 36U corresponding to the target upper limit value is set to the As supply amount upper limit value. It is set slightly on the As underside from the corresponding line 37U.

以下、中断中条件の具体的な制御方法の一例について説明する。AlGaAs層31の成膜を停止させた後、As供給量をSに維持したまま、基板温度を低下させる。図2Bにおいて、中断中条件が、成膜時の条件31Pを始点として下方に移動する。基板温度の低下中に、常時、またはある時間間隔で基板温度を測定する。 Hereinafter, an example of a specific control method for the interruption condition will be described. After stopping the formation of the AlGaAs layer 31, while maintaining the As feed amount S 2, the substrate temperature is lowered. In FIG. 2B, the interruption condition moves downward starting from the film formation condition 31P. While the substrate temperature is decreasing, the substrate temperature is measured constantly or at certain time intervals.

中断中条件が、As供給量の目標上限値に対応する線36Uまで達したら、目標下限値に対応する線36Lに達するまで、As供給量を低下させる。すなわち、As供給量をS21まで低下させる。基板温度がさらに低下し、再度、中断中条件が目標上限値に対応する線36Uに達したら、目標下限値に対応する線36Lに達するまで、As供給量をさらに低下させる。 When the suspended condition reaches the line 36U corresponding to the target upper limit value of the As supply amount, the As supply amount is decreased until the line 36L corresponding to the target lower limit value is reached. In other words, reducing the As feed amount to S 21. When the substrate temperature further decreases and the interruption condition reaches the line 36U corresponding to the target upper limit value again, the As supply amount is further decreased until the line 36L corresponding to the target lower limit value is reached.

中断中条件が目標上限値に対応する線36Uに達する前に、基板温度がTに達したら、基板温度をTに維持した状態で、As供給量をSまで低下させる。 Before suspending conditions reach line 36U corresponding to the target upper limit value, when the substrate temperature reaches T 1, while maintaining the substrate temperature to T 1, reducing the As supply amount to S 1.

このように、中断中条件が、As供給量の目標上限値に対応する線36Uに達する度に、目標下限値に対応する線36Lに達するまでAs供給量を低下させる。この制御により、Asの供給量は、測定された基板温度におけるAs供給量の目標下限値と目標上限値との間に納まる。このため、成長中断時におけるAlGaAs層31の表面の結晶状態の劣化を防止することができる。   Thus, every time the interrupted condition reaches the line 36U corresponding to the target upper limit value of the As supply amount, the As supply amount is decreased until the line 36L corresponding to the target lower limit value is reached. With this control, the supply amount of As falls between the target lower limit value and the target upper limit value of the As supply amount at the measured substrate temperature. For this reason, it is possible to prevent the deterioration of the crystal state of the surface of the AlGaAs layer 31 when the growth is interrupted.

AlGaAs層33を成長させた後、基板温度をTからTまで上昇させる際には、図2Bにおいて、中断中条件を、成膜時の条件32Pから条件31Pまで移動させる。具体的には、As供給量をSに維持したまま、基板温度を上昇させる。中断中条件が、As供給量の目標下限値に対応する線36Lに達する度に、目標上限値に対応する線36Uに達するまでAs供給量を上昇させる。基板温度がTまで達すると、基板温度をTに維持したまま、As供給量をSまで増加させる。このように、中断中条件を制御することにより、基板温度上昇時にも、AlGaAs層31の結晶状態の劣化を防止することができる。 After the AlGaAs layer 33 is grown, when increasing the substrate temperature from T 1 to T 2 are, in FIG. 2B, the interruption condition, moves from the condition 32P at the time of film formation until the condition @ 31 P. Specifically, while maintaining the As feed amount S 1, to raise the substrate temperature. Each time the suspended condition reaches the line 36L corresponding to the target lower limit value of the As supply amount, the As supply amount is increased until reaching the line 36U corresponding to the target upper limit value. When the substrate temperature reaches T 2, while maintaining the substrate temperature at T 2, increases the As supply amount to S 2. In this way, by controlling the interruption condition, it is possible to prevent the deterioration of the crystal state of the AlGaAs layer 31 even when the substrate temperature rises.

なお、中断中条件を、図2Bにおいて、条件31Pから32Pまで、またはその逆に移動させる経路は、上記具体例で説明した経路に限定されない。中断中条件が、As供給量の目標下限値に対応する線36Lと目標上限値に対応する線36Uとの間に納まるように、中断中条件を変化させればよい。例えば、As供給量を、基板温度の変化に応じて連続的に変化させてもよい。   In addition, the path | route which moves conditions during interruption from condition 31P to 32P in FIG. 2B, or the reverse is not limited to the path | route demonstrated in the said specific example. The suspended condition may be changed so that the suspended condition falls between the line 36L corresponding to the target lower limit value of the As supply amount and the line 36U corresponding to the target upper limit value. For example, the As supply amount may be continuously changed according to changes in the substrate temperature.

従来、成長中断中におけるAsの乖離を防止するために、成長中断中にAs原料を供給しておくことは公知であった。ところが、図2Bにおいて、基板温度をTからTまで低下させる際に、As供給量をSに維持したまま基板温度をTまで低下させると、中断中条件が、As供給量上限値に対応する線37Uを横切って、好適な範囲から外れてしまう。実施例1では、中断中条件が、好適な範囲から外れることを防止できる。 Conventionally, it has been known that an As raw material is supplied during a growth interruption in order to prevent a deviation of As during the growth interruption. However, in Figure 2B, when the substrate temperature is lowered from T 2 to T 1, when the As supply amount to lower the substrate temperature maintained in the S 2 to T 1, interrupted condition, As the supply amount upper limit value Crossing the line 37U corresponding to is out of the preferred range. In the first embodiment, the interruption condition can be prevented from deviating from the preferred range.

図3に、実施例1による方法で作製した評価用の光伝導型光検出器の雑音特性の測定結果を、従来の方法で作製した同一構造の検出器の雑音特性の測定結果と比較して示す。横軸は、評価用試料に流した電流を単位「A」で表し、縦軸は、規格化雑音電流強度を単位「A/Hz」で表す。図中の白抜き記号が、従来の方法で作製した光検出器の測定結果を示し、黒ベタ記号が、実施例1の方法で作製した光検出器の測定結果を示す。光伝導型光検出器は、n型AlGaAs層と受光層とを交互に繰り返し成長させることにより作製した。n型AlGaAs層は、基板温度600℃で成長させ、受光層は、基板温度400℃で成長させた。規格化雑音電流強度は、検出器に光を照射しない状態で電流Iを流したときの単位周波数あたりのホワイトノイズ電力をInとしたとき、In/Iで定義される。 In FIG. 3, the measurement result of the noise characteristic of the photoconductive photodetector for evaluation manufactured by the method according to Example 1 is compared with the measurement result of the noise characteristic of the detector having the same structure manufactured by the conventional method. Show. The horizontal axis represents the current passed through the evaluation sample in the unit “A”, and the vertical axis represents the normalized noise current intensity in the unit “A / Hz”. The white symbols in the figure indicate the measurement results of the photodetector produced by the conventional method, and the solid black symbols indicate the measurement results of the photodetector produced by the method of Example 1. The photoconductive photodetector was produced by repeatedly growing n-type AlGaAs layers and light-receiving layers alternately. The n-type AlGaAs layer was grown at a substrate temperature of 600 ° C., and the light receiving layer was grown at a substrate temperature of 400 ° C. The normalized noise current intensity is defined as In 2 / I, where In 2 is the white noise power per unit frequency when the current I is passed without irradiating the detector with light.

実施例1による方法で作製した光検出器の雑音特性は、従来の方法で作製した光検出器に比べて、素子電流が1×10−6A以下の微小な電流領域で、特に優れていることがわかる。このように、雑音特性が優れているのは、成長中断中に露出していた半導体表面に、深い不純物準位や不純物汚染が導入され難いためと考えられる。 The noise characteristics of the photodetector manufactured by the method according to Example 1 are particularly excellent in a small current region where the element current is 1 × 10 −6 A or less, compared to the photodetector manufactured by the conventional method. I understand that. Thus, it is considered that the noise characteristics are excellent because it is difficult to introduce deep impurity levels or impurity contamination into the semiconductor surface exposed during the interruption of growth.

実施例1では、成長中断中の表面にAlGaAsが露出していたが、他の化合物半導体が露出している場合にも、基板温度と原料の供給量とを、好適な範囲内で変化させる制御を行うことが有効である。特に、V族元素としてAsを含む化合物半導体が露出している場合に、基板温度とAs供給量とを制御することが有効である。中断中条件の好適な範囲は、中断中に露出している表面の材料に依存する。このため、図2Bに示した中断中条件の好適な範囲は、予め、材料ごとに決定しておくことが好ましい。   In Example 1, AlGaAs was exposed on the surface where the growth was interrupted. However, even when other compound semiconductors are exposed, control is performed to change the substrate temperature and the supply amount of the raw material within a preferable range. It is effective to do. In particular, it is effective to control the substrate temperature and the As supply amount when a compound semiconductor containing As as a group V element is exposed. The preferred range of interrupting conditions depends on the surface material that is exposed during the interruption. For this reason, it is preferable to determine the suitable range of the interruption condition shown in FIG. 2B for each material in advance.

また、化合物半導体の表面に、S−Kモード等により量子ドットを形成するとき、及び量子ドット上に半導体層を成長させるときにも、成長の中断を行い、基板温度を変化させる。この場合にも、基板温度とV族元素の供給量とを、上記実施例1のように制御することが有効である。   Also, when quantum dots are formed on the surface of a compound semiconductor by the SK mode or when a semiconductor layer is grown on the quantum dots, the growth is interrupted and the substrate temperature is changed. Also in this case, it is effective to control the substrate temperature and the supply amount of the group V element as in the first embodiment.

実施例1では、図2Bに示したように、基板温度ごとに、As供給量の目標下限値と目標上限値とを設定しておいたが、成長中断中に、常時またはある時間間隔で、RHEED測定器で半導体層を観察し、観察結果に基づいてAsの供給量を制御してもよい。   In Example 1, as shown in FIG. 2B, the target lower limit value and the target upper limit value of the As supply amount were set for each substrate temperature. However, during the growth interruption, always or at a certain time interval, The semiconductor layer may be observed with a RHEED measuring instrument, and the supply amount of As may be controlled based on the observation result.

また、実施例1では、MBEにより化合物半導体層を形成したが、他の方法、例えば有機金属化学気相成長(MOCVD)により化合物半導体層を形成する場合にも、実施例1と同様の手法が有効である。MOCVDにおいては、As供給量は、As原料、例えばアルシン(AsH)の流量に相当する。 In Example 1, the compound semiconductor layer is formed by MBE. However, when the compound semiconductor layer is formed by another method, for example, metal organic chemical vapor deposition (MOCVD), the same method as in Example 1 is used. It is valid. In MOCVD, the As supply amount corresponds to the flow rate of As raw material, for example, arsine (AsH 3 ).

図4A〜図4Cを参照して、実施例2による半導体装置(光伝導型光検出素子)の製造方法について説明する。   With reference to FIGS. 4A to 4C, a method of manufacturing a semiconductor device (photoconductive photodetection element) according to Example 2 will be described.

図4Aに示すように、GaAs基板40の上に、厚さ100nmのGaAsバッファ層41を形成する。さらにn型GaAsの下部コンタクト層42を形成する。下部コンタクト層42の上に、多重量子井戸層43を形成する。多重量子井戸層43の上に、n型GaAsの上部コンタクト層44を形成する。下部コンタクト層42及び上部コンタクト層44の各々の厚さは500nmであり、n型不純物であるSiの濃度は1×1018cm−3である。なお、n型不純物として、Si以外の不純物を用いてもよい。 As shown in FIG. 4A, a GaAs buffer layer 41 having a thickness of 100 nm is formed on a GaAs substrate 40. Further, a lower contact layer 42 of n-type GaAs is formed. A multiple quantum well layer 43 is formed on the lower contact layer 42. An n-type GaAs upper contact layer 44 is formed on the multiple quantum well layer 43. The thickness of each of the lower contact layer 42 and the upper contact layer 44 is 500 nm, and the concentration of Si that is an n-type impurity is 1 × 10 18 cm −3 . An impurity other than Si may be used as the n-type impurity.

図4Bに、多重量子井戸層43の断面図を示す。多重量子井戸層43は、AlGaAsバリア層43AとInGaAs量子井戸層43Bとが交互に積層された積層構造を有する。量子井戸層43Bの上面は、AlGaAs被覆層43Cで被覆されている。最も上には、バリア層43Aが配置される。積層構造の繰り返し回数は、例えば量子井戸層43Bが10層になるようにする。   FIG. 4B shows a cross-sectional view of the multiple quantum well layer 43. The multiple quantum well layer 43 has a stacked structure in which AlGaAs barrier layers 43A and InGaAs quantum well layers 43B are alternately stacked. The upper surface of the quantum well layer 43B is covered with an AlGaAs coating layer 43C. At the top, the barrier layer 43A is disposed. The number of repetitions of the laminated structure is, for example, 10 quantum well layers 43B.

一例として、最も下のバリア層43Aの厚さは50nmであり、量子井戸層43Bの厚さは5nmである。被覆層43Cの厚さは5nmであり、それに接するバリア層43Aの厚さは45nmである。バリア層43A及び被覆層43CのAlの組成比は、例えば0.15である。   As an example, the lowermost barrier layer 43A has a thickness of 50 nm, and the quantum well layer 43B has a thickness of 5 nm. The thickness of the covering layer 43C is 5 nm, and the thickness of the barrier layer 43A in contact with the covering layer 43C is 45 nm. The Al composition ratio of the barrier layer 43A and the coating layer 43C is, for example, 0.15.

バリア層43Aの成長温度は、例えば600℃であり、量子井戸層43B及び被覆層43Cの成長温度は、例えば500℃である。バリア層43Aよりも低い温度で成長される被覆層43Cは、量子井戸層43B中のInの乖離を防止するためにである。従って、量子井戸層43Bの上に成長させるべき半導体層の成長温度を、Inの乖離を引き起こさない程度に設定する場合には、被覆層43Cを形成する必要はない。   The growth temperature of the barrier layer 43A is, for example, 600 ° C., and the growth temperature of the quantum well layer 43B and the covering layer 43C is, for example, 500 ° C. The coating layer 43C grown at a temperature lower than that of the barrier layer 43A is for preventing the In dissociation in the quantum well layer 43B. Therefore, when the growth temperature of the semiconductor layer to be grown on the quantum well layer 43B is set to a level that does not cause the In dissociation, it is not necessary to form the covering layer 43C.

量子井戸層43Bに、電子供給のために、n型不純物であるSiを8.5×1017cm−3程度ドープしてもよい。 The quantum well layer 43B may be doped with about 8.5 × 10 17 cm −3 of Si, which is an n-type impurity, for supplying electrons.

バリア層43Aの成長後、量子井戸層43Bの成長前の成長中断時に、基板温度を600℃から500℃まで低下させる。被覆層43Cの成長後、バリア層43Aの成長前の成長中断時に、基板温度を500℃から600℃まで上昇させる。基板温度の昇降時に、実施例1と同様に、中断中条件を、図2Bに示したAs供給量の目標下限値に対応する線36Lと目標上限値に対応する線36Uとの間の領域に納まるように制御する。   After the growth of the barrier layer 43A, the substrate temperature is lowered from 600 ° C. to 500 ° C. when the growth is interrupted before the growth of the quantum well layer 43B. After the growth of the covering layer 43C, the substrate temperature is raised from 500 ° C. to 600 ° C. when the growth is interrupted before the growth of the barrier layer 43A. When raising or lowering the substrate temperature, the interruption condition is set in a region between the line 36L corresponding to the target lower limit value of As supply amount and the line 36U corresponding to the target upper limit value shown in FIG. Control to fit.

図4Cに示すように、多重量子井戸層43及び上部コンタクト層44の一部をエッチングすることにより、下部コンタクト層42の一部を露出させる。上部コンタクト層44及び下部コンタクト層42の露出した領域に、それぞれ電極45及び46を形成する。電極45及び46には、例えばAuGeが用いられる。   As shown in FIG. 4C, a part of the lower contact layer 42 is exposed by etching a part of the multiple quantum well layer 43 and the upper contact layer 44. Electrodes 45 and 46 are formed in the exposed regions of the upper contact layer 44 and the lower contact layer 42, respectively. For the electrodes 45 and 46, for example, AuGe is used.

実施例2による光伝導型光検出器は、赤外線の波長域に感度を有する。成長中断時に、実施例1の場合と同様に、基板温度とAs供給量とを、好適な範囲から外れないように制御しているため、成長中断時に露出していた半導体表面の不純物に起因する雑音特性の低下を抑制することができる。   The photoconductive photodetector according to Example 2 has sensitivity in the infrared wavelength region. When the growth is interrupted, the substrate temperature and the As supply amount are controlled so as not to depart from the preferred ranges, as in the case of the first embodiment, and this is caused by impurities on the semiconductor surface exposed when the growth is interrupted. A decrease in noise characteristics can be suppressed.

実施例2では、光吸収層に量子井戸を用いた多重量子井戸構造を有する光検出器の製造に、実施例1による基板温度とAs供給量との制御方法を適用した。電極から光吸収層へのキャリアの輸送過程を利用する他の構造の光検出器、例えば、量子ドット構造や量子細線構造を有する光検出器においても、実施例1による制御方法が有効である。   In Example 2, the method for controlling the substrate temperature and As supply amount according to Example 1 was applied to the manufacture of a photodetector having a multiple quantum well structure using quantum wells in the light absorption layer. The control method according to the first embodiment is also effective in a photodetector having another structure that uses the transport process of carriers from the electrode to the light absorption layer, for example, a photodetector having a quantum dot structure or a quantum wire structure.

図5A及び図5Bを参照して、実施例3による半導体装置(高電子移動度トランジスタ:HEMT)の製造方法について説明する。   With reference to FIG. 5A and FIG. 5B, the manufacturing method of the semiconductor device (high electron mobility transistor: HEMT) by Example 3 is demonstrated.

図5Aに示すように、GaAs基板50をMBE装置の準備室に搬入し、脱ガス処理を行う。その後、図1に示したMBE装置のチャンバ10内に搬入し、ステージ11に搭載する。As雰囲気下でGaAs基板50を加熱することにより、表面の酸化膜を除去する。   As shown in FIG. 5A, the GaAs substrate 50 is carried into the preparation chamber of the MBE apparatus, and degassing processing is performed. Thereafter, it is carried into the chamber 10 of the MBE apparatus shown in FIG. By heating the GaAs substrate 50 in an As atmosphere, the oxide film on the surface is removed.

GaAs基板50の上に、GaAsバッファ層51を成長させる。成長時の基板温度は600℃とし、バッファ層51の厚さは、例えば100nmとする。バッファ層51を成長させることにより、表面の平坦性が改善される。   A GaAs buffer layer 51 is grown on the GaAs substrate 50. The substrate temperature during growth is 600 ° C., and the thickness of the buffer layer 51 is, for example, 100 nm. By growing the buffer layer 51, the flatness of the surface is improved.

バッファ層51を形成した後、成長を一時中断し、基板温度を500℃まで低下させる。このとき、基板温度とAs供給量とを、実施例1の場合と同様に制御する。具体的には、基板温度とAs供給量とが、図2Bに示した好適な範囲、すなわちAs供給量の目標下限値に対応する線36Lと目標上限値に対応する線36Uとの間の領域に納まるように、両者を制御する。   After forming the buffer layer 51, the growth is temporarily interrupted, and the substrate temperature is lowered to 500 ° C. At this time, the substrate temperature and As supply amount are controlled in the same manner as in the first embodiment. Specifically, the substrate temperature and the As supply amount are in a preferable range shown in FIG. 2B, that is, a region between the line 36L corresponding to the target lower limit value of the As supply amount and the line 36U corresponding to the target upper limit value. Both are controlled so as to fit in

基板温度500℃の条件で、アンドープのInGaAsチャネル層52を成長させる。チャネル層52の厚さは、例えば15nmとする。チャネル層52の上に、アンドープのAlGaAs被覆層53を形成する。被覆層53の厚さは、例えば5nmとする。被覆層53の形成後、成長を一時中断させ、基板温度を600℃まで上昇させる。この中断中に、実施例1の場合と同様に、基板温度とAs供給量とを制御する。   An undoped InGaAs channel layer 52 is grown at a substrate temperature of 500 ° C. The thickness of the channel layer 52 is, for example, 15 nm. An undoped AlGaAs covering layer 53 is formed on the channel layer 52. The thickness of the coating layer 53 is 5 nm, for example. After the formation of the covering layer 53, the growth is temporarily interrupted, and the substrate temperature is raised to 600 ° C. During this interruption, the substrate temperature and As supply amount are controlled in the same manner as in the first embodiment.

基板温度600℃の条件で、n型AlGaAs障壁層54を成長させる。例えば、障壁層54のn型不純物の濃度は2×1016cm−3とし、厚さは40nmとする。障壁層54の上に、n型GaAsキャップ層55を成長させる。キャップ層55には、電子濃度が2×1018cm−3になるようにn型不純物がドープされる。キャップ層55の厚さは、例えば10nmとする。 The n-type AlGaAs barrier layer 54 is grown under the condition of the substrate temperature of 600 ° C. For example, the concentration of the n-type impurity in the barrier layer 54 is 2 × 10 16 cm −3 and the thickness is 40 nm. An n-type GaAs cap layer 55 is grown on the barrier layer 54. The cap layer 55 is doped with an n-type impurity so that the electron concentration is 2 × 10 18 cm −3 . The thickness of the cap layer 55 is 10 nm, for example.

図5Bに示すように、キャップ層55に開口55Aを形成し、障壁層54を露出させる。開口55Aの両側のキャップ層55の上に、それぞれAuGeのオーミック電極56を形成する。開口55A内に露出している障壁層54の上に、Alのショットキゲート電極57を形成する。一対のオーミック電極56をソース及びドレインとするHEMTが得られる。   As shown in FIG. 5B, an opening 55A is formed in the cap layer 55, and the barrier layer 54 is exposed. AuGe ohmic electrodes 56 are respectively formed on the cap layers 55 on both sides of the opening 55A. An Al Schottky gate electrode 57 is formed on the barrier layer 54 exposed in the opening 55A. A HEMT having a pair of ohmic electrodes 56 as a source and a drain is obtained.

InGaAsチャネル層52を成長させる前の成長中断時、及び障壁層54を成長させる前の成長中断時に、実施例1の場合と同様の方法で、基板温度とAs供給量とが制御されている。このため、中断時に露出している表面の不純物に起因する素子性能の低下を抑制することができる。   When the growth is interrupted before the InGaAs channel layer 52 is grown, and when the growth is interrupted before the barrier layer 54 is grown, the substrate temperature and the As supply amount are controlled in the same manner as in the first embodiment. For this reason, it is possible to suppress degradation in device performance due to surface impurities exposed at the time of interruption.

以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。   Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

10 チャンバ
11 ステージ
13 温度測定器
14 排気管
15A RHEED用電子銃
15B 回折ビーム検出器
16 ヒータ
20 原料供給装置
21 供給量制御部
25 制御装置
28 成長用基板
30 GaAs基板
31 AlGaAs層
31P、32P 成膜条件
32 InGaAs層
33、34 AlGaAs層
36U As供給量の目標上限値に対応する線
36L As供給量の目標下限値に対応する線
37U As供給量の上限値に対応する線
37L As供給量の下限値に対応する線
40 GaAs基板
41 バッファ層
42 下部コンタクト層
43 多重量子井戸層
43A バリア層
43B 量子井戸層
43C 被覆層
44 上部コンタクト層
45、46 電極
50 GaAs基板
51 バッファ層
52 チャネル層
53 被覆層
54 障壁層
55 キャップ層
56 オーミック電極
57 ショットキゲート電極
DESCRIPTION OF SYMBOLS 10 Chamber 11 Stage 13 Temperature measuring device 14 Exhaust pipe 15A RHEED electron gun 15B Diffraction beam detector 16 Heater 20 Raw material supply apparatus 21 Supply amount control part 25 Control apparatus 28 Growth substrate 30 GaAs substrate 31 AlGaAs layers 31P and 32P Film formation Condition 32 InGaAs layer 33, 34 AlGaAs layer 36U Line 36L corresponding to the target upper limit value of As supply amount Line 37U corresponding to the target lower limit value of As supply amount Lower limit of line 37L As supply amount corresponding to the upper limit value of As supply amount Line 40 corresponding to the value GaAs substrate 41 Buffer layer 42 Lower contact layer 43 Multiple quantum well layer 43A Barrier layer 43B Quantum well layer 43C Cover layer 44 Upper contact layer 45, 46 Electrode 50 GaAs substrate 51 Buffer layer 52 Channel layer 53 Cover layer 54 Barrier layer 55 Cap layer 56 Oh Click electrode 57 Schottky gate electrode

Claims (7)

基板の上に、III−V族化合物半導体である第1の半導体を、第1の基板温度で成長させる工程と、
前記第1の半導体の成長を停止させ、該第1の半導体の表面に、V族元素の原料を供給しながら、前記基板の温度を、前記第1の基板温度とは異なる第2の基板温度に変化させる工程と、
前記第1の半導体の上に、該第1の半導体とは異なるIII−V族化合物半導体である第2の半導体を、前記第2の基板温度で成長させる工程と
を有し、
前記基板の温度を前記第1の基板温度から前記第2の基板温度に変化させる工程が、
前記基板の温度を測定する工程と、
V族元素の供給量が、測定された前記基板の温度における供給量の目標下限値と目標上限値との間に納まるように、該供給量を制御する工程と
を含む半導体装置の製造方法。
Growing a first semiconductor, which is a group III-V compound semiconductor, on a substrate at a first substrate temperature;
A second substrate temperature different from the first substrate temperature while stopping the growth of the first semiconductor and supplying a Group V element source to the surface of the first semiconductor. A process of changing to
Growing a second semiconductor, which is a group III-V compound semiconductor different from the first semiconductor, on the first semiconductor at the second substrate temperature;
Changing the temperature of the substrate from the first substrate temperature to the second substrate temperature;
Measuring the temperature of the substrate;
And a step of controlling the supply amount of the group V element so that the supply amount falls within a target lower limit value and a target upper limit value of the supply amount at the measured substrate temperature.
前記第1の半導体及び第2の半導体が、V族元素としてAsを含み、前記基板の温度を前記第1の基板温度から前記第2の基板温度に変化させる工程において、As供給量を制御する請求項1に記載の半導体装置の製造方法。   The first semiconductor and the second semiconductor contain As as a group V element, and the As supply amount is controlled in the step of changing the temperature of the substrate from the first substrate temperature to the second substrate temperature. A method for manufacturing a semiconductor device according to claim 1. 前記第1の半導体及び第2の半導体を成長させる工程において、分子線エピタキシにより該第1の半導体及び第2の半導体を成長させる請求項1または2に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of growing the first semiconductor and the second semiconductor, the first semiconductor and the second semiconductor are grown by molecular beam epitaxy. 前記基板の温度を前記第1の基板温度から前記第2の基板温度に変化させる工程は、As供給量が、測定された基板温度におけるAs供給量の目標上限値に達したら、As供給量を低下させる工程を含む請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。   The step of changing the temperature of the substrate from the first substrate temperature to the second substrate temperature is performed when the As supply amount reaches a target upper limit value of the As supply amount at the measured substrate temperature. The manufacturing method of the semiconductor device of any one of Claim 1 thru | or 3 including the process to reduce. 成長用基板を収容するチャンバと、
前記チャンバ内に、III族元素の原料及びV族元素の原料を、制御された供給量で供給する原料供給装置と、
前記チャンバに収容された成長用基板の温度を測定する温度測定器と、
基板温度ごとに、V族元素の供給量の目標下限値及び目標上限値を記憶しており、前記温度測定器による測定結果に基づいて、V族元素の供給量が前記目標下限値及び目標上限値の間に納まるように、前記原料供給装置を制御する制御装置と
を有する半導体製造装置。
A chamber containing a growth substrate;
A raw material supply device for supplying a group III element raw material and a group V element raw material in a controlled supply amount into the chamber;
A temperature measuring device for measuring the temperature of the growth substrate housed in the chamber;
For each substrate temperature, the target lower limit value and the target upper limit value of the supply amount of the group V element are stored, and based on the measurement result by the temperature measuring device, the supply amount of the group V element is the target lower limit value and the target upper limit value. A semiconductor manufacturing apparatus having a control device for controlling the raw material supply device so as to fall between values.
基板の上に、III−V族化合物半導体である第1の半導体を、第1の基板温度で成長させる工程と、
前記第1の半導体の成長を停止させ、前記第1の半導体の表面に、V族元素の原料を供給しながら、前記基板の温度を、前記第1の基板温度とは異なる第2の基板温度に変化させる工程と、
前記第1の半導体の上に、該第1の半導体とは異なるIII−V族化合物半導体である第2の半導体を、前記第2の基板温度で成長させる工程と
を有し、
前記基板の温度を前記第1の基板温度から前記第2の基板温度に変化させる工程において、前記第1の半導体を反射高速電子回折法により観察しながら、観察結果に基づいてV族元素の原料の供給量を制御する半導体装置の製造方法。
Growing a first semiconductor, which is a group III-V compound semiconductor, on a substrate at a first substrate temperature;
While the growth of the first semiconductor is stopped and the source of the group V element is supplied to the surface of the first semiconductor, the temperature of the substrate is set to a second substrate temperature different from the first substrate temperature. A process of changing to
Growing a second semiconductor, which is a group III-V compound semiconductor different from the first semiconductor, on the first semiconductor at the second substrate temperature;
In the step of changing the temperature of the substrate from the first substrate temperature to the second substrate temperature, while observing the first semiconductor by a reflection high-energy electron diffraction method, based on the observation result, a group V element material Of manufacturing a semiconductor device for controlling the supply amount of the semiconductor.
成長用基板を収容するチャンバと、
前記チャンバ内に、III族元素の原料及びV族元素の原料を、制御された供給量で供給する原料供給装置と、
前記チャンバ内に収容された成長用基板の上に形成された半導体膜を反射高速電子回折法により測定する半導体膜測定器と、
前記半導体膜測定器の測定結果に基づいて、前記原料供給装置を制御する制御装置と
を有する半導体製造装置。
A chamber containing a growth substrate;
A raw material supply device for supplying a group III element raw material and a group V element raw material in a controlled supply amount into the chamber;
A semiconductor film measuring instrument for measuring a semiconductor film formed on a growth substrate housed in the chamber by reflection high energy electron diffraction;
A semiconductor manufacturing apparatus comprising: a control device that controls the raw material supply device based on a measurement result of the semiconductor film measuring instrument.
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