JP2010225600A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique capable of suppressing, in the process of grinding the reverse surface of a semiconductor wafer, intermingling of grinding dusts occurring while grinding the reverse surface into the principal surface of the semiconductor wafer by improving adhesion with a protective tape in an outer peripheral part of the semiconductor wafer. <P>SOLUTION: In a dicing region DR (end part), a negative type photosensitive polyimide resin film EPI is buried in an opening part OP2, therefore the negative type photosensitive polyimide resin film EPI, which is buried, and an adhesive ADH are tightly bonded together. Namely, the negative type photosensitive polyimide resin film EPI is buried in the opening part OP2 in the dicing region DR (end part), and the negative type photosensitive polyimide resin film EPI and the adhesive ADH are tightly bonded together, as a result, any gap does not occur in the dicing region DR (end part). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a process of grinding a back surface of a semiconductor wafer.

  Japanese Patent Application Laid-Open No. 2003-197723 (Patent Document 1) describes a technique for preventing the grinding pad and grinding water from entering and preventing deterioration and contamination of the electrode pad surface during backside grinding of a semiconductor wafer.

JP 2003-197723 A

  In a manufacturing process of a semiconductor device, there is a process of grinding a back surface opposite to a main surface of a semiconductor wafer on which semiconductor elements and multilayer wiring are formed. This back grinding process is a process performed to reduce the thickness of the semiconductor wafer. Specifically, in the back surface grinding process, a protective tape is applied to the entire main surface of the semiconductor wafer via an adhesive, and then the semiconductor wafer is turned over, and a grinder is pressed against the back surface of the semiconductor wafer to cover the back surface of the semiconductor wafer. Grinding. In this way, the back surface of the semiconductor wafer is ground, but polishing scraps are generated when grinding.

  Here, the main surface of the semiconductor wafer is formed with a plurality of chip regions and a dicing region in which grooves for dicing are formed. In order to protect the surface of the plurality of chip regions, for example, a surface protective film made of a polyimide resin film is formed. At this time, since the pads are formed in the plurality of chip regions, the surface protective film is formed so as to expose the pads. On the other hand, a groove is formed in the dicing region that divides the plurality of chip regions, and the polyimide resin film formed in the dicing region in which the groove is formed is removed. That is, the polyimide resin film is not formed in the dicing region, and the groove is exposed. A protective tape is attached to the main surface of the semiconductor wafer thus configured via an adhesive in the back surface grinding step. However, there are a plurality of chip regions where a polyimide resin film is formed and a dicing region where no polyimide resin film is formed and grooves are formed on the main surface of the semiconductor wafer. That is, the main surface of the semiconductor wafer is uneven. This unevenness is also present at the outer periphery of the semiconductor wafer.

  In this case, as a result of the unevenness in the outer peripheral portion of the semiconductor wafer, a situation occurs in which the protective tape attached to the main surface of the semiconductor wafer is not firmly adhered. In other words, the chip area where the polyimide resin film is formed and the dicing area where the polyimide resin film is removed and the grooves are formed on the outer periphery of the semiconductor wafer. Concavities and convexities will be generated by that amount. For this reason, the protective tape to be attached to the main surface of the semiconductor wafer does not firmly adhere to the unevenness formed on the outer peripheral portion of the semiconductor wafer, and a gap is generated. Then, grinding waste generated in the back surface grinding process enters the inside of the semiconductor wafer from the gap between the protective tape and the main surface of the semiconductor wafer. In some cases, grinding scraps that enter the inside of the semiconductor wafer may adhere to the pads formed in the chip region.

  If the grinding scraps adhere to the pad, there arises a problem that the bonding strength between the pad and the wire is lowered in the subsequent bonding process.

  The object of the present invention is to improve the adhesion with the protective tape at the outer peripheral portion of the semiconductor wafer in the back grinding process of the semiconductor wafer, so that grinding waste generated during back grinding is mixed into the main surface of the semiconductor wafer. It is to provide a technology that can be suppressed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to a representative embodiment includes: (a) a plurality of chip regions and a plurality of chip regions of a semiconductor wafer having a divided region that divides the plurality of chip regions on a main surface side; And (b) forming a multilayer wiring layer on the MISFET formed in the plurality of chip regions, and forming a pad on the uppermost layer of the multilayer wiring layer. And (c) forming a groove in the divided region of the semiconductor wafer, and (d) forming a surface protective film on the plurality of chip regions and the divided regions in which the pads of the semiconductor wafer are formed. Is provided. (E) In the plurality of chip regions, the surface protection film is processed so as to expose the pads, and the surface protection film is left in an end region within a predetermined range from the outer periphery of the semiconductor wafer. And (f) attaching a protective tape to the entire main surface of the semiconductor wafer via an adhesive. Next, (g) a step of grinding the back surface opposite to the main surface of the semiconductor wafer to which the protective tape is attached is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the back grinding process of the semiconductor wafer, it is possible to improve the adhesion with the protective tape at the outer peripheral portion of the semiconductor wafer, and it is possible to suppress the grinding waste generated during the back grinding from being mixed into the main surface of the semiconductor wafer.

It is a top view which shows the surface of a semiconductor wafer. It is a figure for demonstrating the edge part area | region of a semiconductor wafer. FIG. 2 is an enlarged view in which a partial region of the semiconductor wafer shown in FIG. 1 is enlarged. It is the figure cut | disconnected by the AA line | wire of FIG. 3, and is sectional drawing for demonstrating the subject of a prior art. It is sectional drawing for demonstrating the subject of the prior art following FIG. FIG. 2 is an enlarged view in which a partial region of the semiconductor wafer shown in FIG. 1 is enlarged. It is sectional drawing which shows the manufacturing process of the semiconductor device in Embodiment 1 of this invention. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; It is a figure which shows a mode that a 1st exposure process is implemented to a semiconductor wafer. It is a figure which shows a mode that a 2nd exposure process (peripheral exposure) is implemented to a semiconductor wafer. FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; It is a figure which shows the modification which implements a 1st exposure process to a semiconductor wafer. FIG. 6 is a plan view showing a configuration of a lead frame in a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; It is the enlarged view to which the partial area | region of the semiconductor wafer was expanded. It is sectional drawing based on the cross section cut | disconnected by the AA line of FIG. It is the enlarged view to which the partial area | region of the semiconductor wafer was expanded. It is sectional drawing based on the cross section cut | disconnected by the AA line of FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
First, the region of the semiconductor wafer will be described. FIG. 1 is a plan view showing a semiconductor wafer WF. In FIG. 1, the semiconductor wafer WF has a substantially circular shape, and a plurality of chip regions CR are formed on the main surface of the semiconductor wafer WF. The chip region CR has a rectangular shape and is formed so as to fill the main surface of the semiconductor wafer WF. At this time, an incompletely shaped region that is not rectangular is formed on the outer peripheral portion of the semiconductor wafer WF, and this region is also referred to as a chip region CR in this specification.

  In the plurality of chip regions CR, each chip region CR is divided by a dicing region (divided region) DR. The dicing region DR is a region for dividing the chip region CR formed on the semiconductor wafer WF into pieces and cutting them into semiconductor chips. Specifically, a groove is formed in the dicing region DR. This groove has a function of facilitating dicing and a function of preventing cracks generated during dicing from extending from the dicing region DR to the chip region CR. As described above, a plurality of chip regions CR and a dicing region DR that partitions the plurality of chip regions are formed on the main surface of the semiconductor wafer WF.

  Further, in this specification, the end region is defined as one region of the semiconductor wafer. This end region will be described. FIG. 2 is a plan view showing the main surface of the semiconductor wafer WF. In FIG. 2, an end region ER is formed along the outer periphery of the semiconductor wafer WF. This end region ER is defined as a region within a predetermined range from the outer periphery of the semiconductor wafer WF. Specifically, in the present specification, an end region ER is a region from the outer peripheral portion of the semiconductor wafer WF to 3 mm to 4 mm inside.

  Next, FIG. 3 is an enlarged view of the region RA of FIG. As shown in FIG. 3, a plurality of chip regions CR are formed in the region RA, and a plurality of pads PD are formed in the chip region CR. A dicing region DR is formed so as to partition the chip region CR. Further, an end region ER is formed within a predetermined range from the outer periphery of the semiconductor wafer. At this time, a problem in the prior art will be described using a cross-sectional view in a region where the dicing region DR and the end region ER overlap in a planar manner.

  4 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 4, a dicing trench DIT is formed in the semiconductor substrate 1S, an interlayer insulating film ML is formed in a region other than the formation region of the dicing trench DIT, and a surface protective film is formed on the interlayer insulating film ML. PAS is formed. That is, an opening OP in which the interlayer insulating film ML and the surface protective film PAS are opened is formed on the dicing trench DIT.

  Here, in the manufacturing process of the semiconductor device, there is a process of grinding the back surface opposite to the main surface of the semiconductor wafer on which the semiconductor element and the multilayer wiring are formed. This back grinding process is a process performed to reduce the thickness of the semiconductor wafer. Specifically, in the back surface grinding process, a protective tape is applied to the entire main surface of the semiconductor wafer via an adhesive, and then the semiconductor wafer is turned over, and a grinder is pressed against the back surface of the semiconductor wafer to cover the back surface of the semiconductor wafer. Grinding.

  FIG. 5 is a cross-sectional view showing a state in which the protective tape PT is attached to the main surface of the semiconductor wafer in which the dicing grooves DIT shown in FIG. 4 are formed via an adhesive ADH. As shown in FIG. 5, the semiconductor substrate 1S has a recess formed by the dicing groove DIT, so that a gap exists between the adhesive ADH and the dicing groove DIT.

  In the backside grinding process of the semiconductor wafer, grinding waste is generated. This grinding waste enters the inside of the main surface of the semiconductor wafer through the gap between the dicing groove DIT and the adhesive ADH shown in FIG. Grinding debris that has entered the main surface of the semiconductor wafer may adhere to the pad PD formed in the chip region CR through the dicing groove DIT shown in FIG. The pad PD is electrically connected to a wire by a wire bonding process after the chip region CR is separated into a semiconductor chip. At this time, if grinding waste adheres to the pad PD, there arises a problem that the connection strength between the pad PD and the wire is lowered.

  The cause of such a problem is that the dicing groove DIT exists in the end region ER of the semiconductor wafer. As a result, the semiconductor wafer and the adhesive in the end region ER of the semiconductor wafer during the back grinding process of the semiconductor wafer. This is due to the fact that the protective tape PT does not adhere firmly through the ADH. That is, as a result of the dicing groove DIT being formed in the outer peripheral portion of the semiconductor wafer, the gap formed between the dicing groove DIT and the adhesive ADH is exposed on the side surface of the semiconductor wafer.

  Therefore, in the first embodiment, a contrivance is made to suppress a gap formed between the dicing groove DIT and the adhesive ADH in the end region of the semiconductor wafer. Hereinafter, a manufacturing method of the semiconductor device according to the first embodiment to which this device is applied will be described with reference to the drawings.

  FIG. 6 is an enlarged view of the region RA in FIG. In FIG. 6, a plurality of chip regions CR are formed in the region RA, and a plurality of pads PD are formed in the chip region CR. A dicing region DR is formed so as to partition the chip region CR. Further, an end region ER is formed within a predetermined range from the outer periphery of the semiconductor wafer. At this time, the cross section cut along the AA line in the chip region CR, the cross section cut along the BB line in a region that does not overlap the end region ER in the dicing region DR, and the dicing region DR A method for manufacturing the semiconductor device according to the first embodiment will be described using a cross section taken along the line CC in a region overlapping the end region ER in plan view. Here, a region of the dicing region DR that does not overlap the end region ER in a plane is called a dicing region DR (inside), and a region of the dicing region DR that overlaps the end region ER in a plane is a dicing region DR (end). Part).

First, as shown in FIG. 7, an n-channel MISFET Q ₁ and a p-channel MISFET Q ₂ are formed in the chip region CR of the semiconductor substrate 1 S by using a normal metal insulator semiconductor field effect transistor (MISFET) formation technique. .

In FIG. 7, n-channel type MISFET Q ₁ is formed in the active region isolated by the element isolation region, for example, has the following construction. Specifically, in the active region isolated by the element isolation region and p-type well is formed, n-channel type MISFET Q ₁ is formed on the p-type well. n-channel type MISFET Q ₁ is on the main surface of the semiconductor substrate 1S, e.g., a gate insulating film made of a silicon oxide film, provided on the gate insulating film on the polysilicon film on the polysilicon film silicide A gate electrode made of a laminated film of films (such as a nickel silicide film) is provided. Side walls made of, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode, and shallow n-type impurity diffusion regions are formed in alignment with the gate electrode in the semiconductor substrate below the sidewall. . A deep n-type impurity diffusion region is formed outside the shallow n-type impurity diffusion region in alignment with the sidewall. By a pair of shallow n-type impurity diffusion region and a pair of deep n-type impurity diffusion region, a source region and a drain region of the n-channel type MISFET Q ₁ are formed.

Similarly, in FIG. 7, p-channel type MISFET Q ₂ is formed in the active region isolated by the element isolation region, for example, has the following construction. Specifically, the isolated active regions by the element isolation region and n-type well is formed, p-channel type MISFET Q ₂ is formed on the n-type well. The p-channel type MISFET Q ₂ has a gate insulating film made of, for example, a silicon oxide film on the main surface of the semiconductor substrate 1 S, and a polysilicon film and a silicide film (such as a nickel silicide film) are stacked on the gate insulating film. It has a gate electrode made of a film. Side walls made of, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode, and shallow p-type impurity diffusion regions are formed in alignment with the gate electrode in the semiconductor substrate below the sidewall. . A deep p-type impurity diffusion region is formed outside the shallow p-type impurity diffusion region in alignment with the sidewall. By a pair of shallow p-type impurity diffusion region and a pair of deep p-type impurity diffusion region, a source region and a drain region of the p-channel type MISFET Q ₂ are respectively formed. N-channel type MISFET Q ₁ and p-channel type MISFET Q ₂ are formed on the semiconductor substrate 1S as described above.

  Subsequently, as shown in FIG. 8, an interlayer insulating film IL1 is formed on the semiconductor substrate 1S. This interlayer insulating film IL1 is formed on the entire main surface of the semiconductor substrate 1S including the chip region CR, the dicing region DR (inside) and the dicing region DR (end portion). The interlayer insulating film IL1 is formed of, for example, a silicon oxide film using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. Note that the interlayer insulating film IL1 may be formed of a stacked film of a silicon nitride film and a silicon oxide film. That is, after forming the interlayer insulating film IL1, a contact hole is formed in the interlayer insulating film IL1, and a silicon nitride film can also be used as an etching stopper film for forming this contact hole (SAC (Self Align Contact)) Technology).

Then, a contact hole CNT1 is formed in the interlayer insulating film IL1 in the chip region CR by using a photolithography technique and an etching technique. The chip region CR, the contact hole CNT1 so as to penetrate the interlayer insulating film IL1 is formed, the bottom of the contact hole CNT1 may be, for example, the source region of the n-channel type MISFET Q ₁ and p-channel type MISFET Q _2, reaching the drain region Formed as follows. Thus, in the chip region CR, the contact hole CNT1 is formed in the interlayer insulating film IL1, but at the same time, the interlayer insulating film IL1 is also etched in the dicing region DR (inside) and the dicing region DR (end portion). The opening OP1 and the opening OP2 are respectively formed. At this time, in the dicing region DR (inside) and the dicing region DR (end portion), the interlayer insulating film IL1 is etched to form the opening OP1 and the opening OP2, but further, the exposed semiconductor substrate 1S. Is also etched to form a dicing groove DIT.

  In the chip region CR, the contact hole CNT1 is formed by etching the interlayer insulating film IL1, and the silicide film is exposed at the bottom of the contact hole CNT1. This silicide film serves as an etching stopper, and the semiconductor substrate 1S is not etched in the step of forming the contact hole CNT1 in the chip region CR. On the other hand, no silicide film is formed on the surface of the semiconductor substrate 1S in the dicing region DR (inside) or the dicing region DR (end portion). For this reason, in the step of forming the opening OP1 and the opening OP2 in the interlayer insulating film IL1, the semiconductor substrate 1S exposed in the lower layer of the interlayer insulating film IL1 is etched to form the dicing trench DIT.

  Thereafter, in the chip region CR, a plug PLG1 is formed by embedding a metal film in the contact hole CNT1 formed in the interlayer insulating film IL1. Specifically, on the interlayer insulating film IL1 in which the contact hole CNT1 is formed, for example, a titanium / titanium nitride film that becomes a barrier conductor film using sputtering (here, the titanium / titanium nitride film is on titanium and the titanium). Represents a laminated film of titanium nitride provided on the same, and so on. Then, a tungsten film is formed on the titanium / titanium nitride film by using, for example, a CVD (Chemical Vapor Deposition) method. Thereby, a titanium / titanium nitride film is formed on the inner wall (side wall and bottom surface) of the contact hole CNT1, and a tungsten film is formed on the titanium / titanium nitride film so as to fill the contact hole CNT1.

  Here, also in the dicing region DR (inside), the titanium / titanium nitride film and the tungsten film are formed on the interlayer insulating film IL1 including the inside of the opening OP1, and also in the opening OP2 in the dicing region DR (end portion). A titanium / titanium nitride film and a tungsten film are formed on interlayer insulating film IL1 including Then, an unnecessary titanium / titanium nitride film and an unnecessary tungsten film formed on the interlayer insulating film IL1 are removed by an etch-back method, so that the titanium / titanium nitride film is only in the contact hole CNT1 in the chip region CR. As a result, the tungsten film remains and the plug PLG1 can be formed. On the other hand, in the dicing region DR (inside), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL1 including the inside of the opening OP1 are removed by the etch back method. Similarly, also in the dicing region DR (end portion), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL1 including the inside of the opening OP2 are removed by the etch back method.

  As described above, in the etch-back method, the titanium / titanium nitride film and the tungsten film embedded in the contact hole CNT1 formed in the chip region CR remain to form the plug PLG1, while the dicing region DR ( The reason why the titanium / titanium nitride film and the tungsten film formed in the opening OP1 in the interior and the opening OP2 in the dicing region DR (end portion) are removed is as follows. That is, while the size of the contact hole CNT1 formed in the chip region CR is small, the opening OP1 formed in the dicing region DR (inside) and the opening OP2 formed in the dicing region DR (end). This is because the size of is very large. That is, in the etch-back method, the etching is difficult to proceed in the small contact hole CNT1, and the etching is likely to proceed in the large opening OP1 and the opening OP2.

  Subsequently, a laminated film made of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film is formed on the interlayer insulating film IL1 on which the plug PLG1 is formed. The titanium / titanium nitride film and the aluminum film can be formed, for example, by using a sputtering method. Here, not only the chip region CR but also the dicing region DR (inside) and the dicing region DR (end portion), a laminated film made of a titanium / titanium nitride film and an aluminum film is formed. Then, the laminated film is patterned by using a photolithography technique and an etching technique. Thereby, in the chip region CR, the wiring L1 made of the laminated film is formed. On the other hand, the laminated film formed in the dicing region DR (inside) and the dicing region DR (end portion) is removed.

  Next, as shown in FIG. 9, an interlayer insulating film IL2 is formed over the interlayer insulating film IL1 in which the wiring L1 is formed. The interlayer insulating film IL2 is formed from, for example, a silicon oxide film. In the chip region CR, the interlayer insulating film IL2 is formed on the interlayer insulating film IL1 on which the wiring L1 is formed. In the dicing region DR (inside), the interlayer insulating film is formed on the interlayer insulating film IL1 including the inside of the opening OP1. IL2 is formed. Similarly, in the dicing region DR (end portion), the interlayer insulating film IL2 is formed over the interlayer insulating film IL1 including the inside of the opening OP2.

  Thereafter, by using a photolithography technique and an etching technique, a through hole TH2 that penetrates the interlayer insulating film IL2 and reaches the wiring L1 is formed in the chip region CR. At the same time, in the dicing region DR (inside) and the dicing region DR (end portion), the interlayer insulating film IL2 is etched to form the opening OP1 and the opening OP2, respectively. At this time, in the dicing region DR (inside) and the dicing region DR (end portion), the interlayer insulating film IL2 is etched to form the opening OP1 and the opening OP2, but further, the exposed semiconductor substrate 1S. A part of this is also etched to increase the depth of the dicing groove DIT.

  Subsequently, in the chip region CR, a plug PLG2 is formed by embedding a metal film in the through hole TH2 formed in the interlayer insulating film IL2. Specifically, a titanium / titanium nitride film to be a barrier conductor film is formed on the interlayer insulating film IL2 in which the through hole TH2 is formed by using, for example, sputtering. Then, a tungsten film is formed on the titanium / titanium nitride film by using, for example, a CVD (Chemical Vapor Deposition) method. Thereby, a titanium / titanium nitride film is formed on the inner wall (side wall and bottom surface) of the through hole TH2, and a tungsten film is formed on the titanium / titanium nitride film so as to fill the through hole TH2.

  Here, also in the dicing region DR (inside), a titanium / titanium nitride film and a tungsten film are formed on the interlayer insulating film IL2 including the inside of the opening OP1, and also in the dicing region DR (end portion). A titanium / titanium nitride film and a tungsten film are formed on interlayer insulating film IL2 containing Then, an unnecessary titanium / titanium nitride film and an unnecessary tungsten film formed on the interlayer insulating film IL2 are removed by an etch back method, so that the titanium / titanium nitride film is only in the through hole TH2 in the chip region CR. As a result, the tungsten film remains and the plug PLG2 can be formed. On the other hand, in the dicing region DR (inside), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL2 including the inside of the opening OP1 are removed by the etch back method. Similarly, also in the dicing region DR (end portion), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL2 including the inside of the opening OP2 are removed by the etch back method.

  Then, a laminated film made of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film is formed on the interlayer insulating film IL2 on which the plug PLG2 is formed. The titanium / titanium nitride film and the aluminum film can be formed, for example, by using a sputtering method. Here, not only the chip region CR but also the dicing region DR (inside) and the dicing region DR (end portion), a laminated film made of a titanium / titanium nitride film and an aluminum film is formed. Then, the laminated film is patterned by using a photolithography technique and an etching technique. Thereby, in the chip region CR, the wiring L2 made of the laminated film is formed. On the other hand, the laminated film formed in the dicing region DR (inside) and the dicing region DR (end portion) is removed.

  Next, as shown in FIG. 10, an interlayer insulating film IL3 is formed over the interlayer insulating film IL2 in which the wiring L2 is formed. The interlayer insulating film IL3 is formed of, for example, a silicon oxide film. In the chip region CR, the interlayer insulating film IL3 is formed on the interlayer insulating film IL2 on which the wiring L2 is formed. In the dicing region DR (inside), the interlayer insulating film is formed on the interlayer insulating film IL2 including the inside of the opening OP1. IL3 is formed. Similarly, in the dicing region DR (end portion), the interlayer insulating film IL3 is formed over the interlayer insulating film IL2 including the inside of the opening OP2.

  Thereafter, by using a photolithography technique and an etching technique, a through hole TH3 that penetrates the interlayer insulating film IL3 and reaches the wiring L2 is formed in the chip region CR. At the same time, also in the dicing region DR (inside) and the dicing region DR (end portion), the interlayer insulating film IL3 is etched to form the opening OP1 and the opening OP2, respectively. At this time, in the dicing region DR (inside) and the dicing region DR (end portion), the interlayer insulating film IL3 is etched to form the opening OP1 and the opening OP2, but further, the exposed semiconductor substrate 1S. A part of this is also etched to increase the depth of the dicing groove DIT.

  Subsequently, in the chip region CR, a plug PLG3 is formed by embedding a metal film in the through hole TH2 formed in the interlayer insulating film IL3. Specifically, a titanium / titanium nitride film to be a barrier conductor film is formed on the interlayer insulating film IL3 in which the through hole TH3 is formed by using, for example, sputtering. Then, a tungsten film is formed on the titanium / titanium nitride film by using, for example, a CVD (Chemical Vapor Deposition) method. As a result, a titanium / titanium nitride film is formed on the inner wall (side wall and bottom surface) of the through hole TH3, and a tungsten film is formed on the titanium / titanium nitride film so as to fill the through hole TH3.

  Here, also in the dicing region DR (inside), a titanium / titanium nitride film and a tungsten film are formed on the interlayer insulating film IL3 including the inside of the opening OP1, and also in the dicing region DR (end portion). A titanium / titanium nitride film and a tungsten film are formed on interlayer insulating film IL3 including Then, an unnecessary titanium / titanium nitride film and an unnecessary tungsten film formed on the interlayer insulating film IL3 are removed by an etch back method, so that the titanium / titanium nitride film is only in the through hole TH3 in the chip region CR. As a result, the tungsten film remains and the plug PLG3 can be formed. On the other hand, in the dicing region DR (inside), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL3 including the inside of the opening OP1 are removed by the etch back method. Similarly, also in the dicing region DR (end portion), all the titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL3 including the inside of the opening OP2 are removed by the etch back method.

  Then, a laminated film made of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film is formed on the interlayer insulating film IL3 on which the plug PLG3 is formed. The titanium / titanium nitride film and the aluminum film can be formed, for example, by using a sputtering method. Here, not only the chip region CR but also the dicing region DR (inside) and the dicing region DR (end portion), a laminated film made of a titanium / titanium nitride film and an aluminum film is formed. Then, the laminated film is patterned by using a photolithography technique and an etching technique. Thereby, in the chip region CR, the wiring L3 (the uppermost layer wiring of the multilayer wiring) made of the laminated film is formed. On the other hand, the laminated film formed in the dicing region DR (inside) and the dicing region DR (end portion) is removed.

  Next, as shown in FIG. 11, a silicon nitride film SIN is formed on the interlayer insulating film IL3 on which the wiring L3 is formed. In the chip region CR, the silicon nitride film SIN is formed on the interlayer insulating film IL3 on which the wiring L3 is formed. In the dicing region DR (inside), the silicon nitride film is formed on the interlayer insulating film IL3 including the inside of the opening OP1. A SIN is formed. Similarly, in the dicing region DR (end portion), the silicon nitride film SIN is formed on the interlayer insulating film IL3 including the inside of the opening OP2.

  Thereafter, the silicon nitride film SIN is patterned by using a photolithography technique and an etching technique. Specifically, in the chip region CR, a part of the surface of the wiring L3 is exposed to form the pad PD. At the same time, also in the dicing region DR (inside) and the dicing region DR (end portion), the silicon nitride film SIN is etched to form the opening OP1 and the opening OP2, respectively.

  Subsequently, as shown in FIG. 12, a negative photosensitive polyimide resin film EPI (surface protective film PAS) is formed on the entire main surface of the semiconductor substrate 1S. Thereby, in the chip region CR, the negative photosensitive polyimide resin film EPI is formed on the silicon nitride film SIN from which the pad PD is exposed. On the other hand, in the dicing region DR (inside), a negative photosensitive polyimide resin film EPI is formed so as to fill the opening OP1 and the dicing groove DIT. Similarly, in the dicing region DR (end portion), the opening OP2 and the dicing are formed. A negative photosensitive polyimide resin film EPI is formed so as to fill the trench DIT.

  Then, a first exposure process is performed on the negative photosensitive polyimide resin film EPI formed on the entire main surface of the semiconductor substrate 1S. FIG. 13 is a diagram illustrating a state in which the first exposure process is performed on the semiconductor wafer WF. In FIG. 13, this first exposure process exposes a plurality of adjacent chip regions CR at one time as one shot EXR1. Specifically, exposure processing is performed with four adjacent chip regions CR as one shot EXR1. This first exposure process is performed by irradiating the chip region CR with exposure light through a mask on which a circuit pattern is formed. As the circuit pattern, for example, a pattern that opens the pad PD formed in the chip region CR is used.

  In the first exposure process, since the plurality of chip regions CR are exposed with one shot EXR1, the pattern of the dicing region DR is also reflected. In this case, since the photosensitive material is the negative photosensitive polyimide resin film EPI, when the development process is performed after the exposure process, the negative photosensitive polyimide resin film EPI in the region irradiated with the exposure light remains, The negative photosensitive polyimide resin film EPI in the region where the exposure light is shielded disappears. Therefore, the mask pattern corresponding to the chip region CR is a pattern in which the exposure light is blocked in the region where the pad PD is formed and the exposure light is transmitted in the region where the pad PD is not formed. On the other hand, the mask pattern corresponding to the dicing region DR is a pattern in which exposure light is not irradiated to the dicing region DR so that the negative photosensitive polyimide resin film EPI does not remain in the dicing region DR.

  At this time, as shown in FIG. 13, since the first exposure process includes a case where the outer periphery of the semiconductor wafer WF protrudes and is exposed, patterning is performed so that the dicing region DR is formed up to the outer periphery of the semiconductor wafer WF. Will be. That is, in the first exposure process, patterning is performed so that the negative photosensitive polyimide resin film EPI does not remain in the dicing region DR up to the outer peripheral portion of the semiconductor wafer WF. In other words, the first exposure process is performed such that the exposure light is shielded in the dicing region DR formed up to the outer periphery of the semiconductor wafer WF.

  Next, a second exposure process is performed on the negative photosensitive polyimide resin film EPI formed on the entire main surface of the semiconductor substrate 1S. FIG. 14 is a diagram illustrating a state in which the second exposure process is performed on the semiconductor wafer WF. As shown in FIG. 14, the second exposure process is performed so that the exposure light is irradiated only to the end region ER of the semiconductor wafer. That is, the second exposure process is a peripheral exposure in which the exposure light is irradiated only to the end region of the semiconductor wafer WF. The feature of the first embodiment is that the second exposure process is performed. By performing this second exposure process, exposure light is irradiated to all of the negative photosensitive polyimide resin film EPI formed in the end region ER of the semiconductor wafer WF. This means that all of the negative photosensitive polyimide resin film EPI formed in the end region ER of the semiconductor wafer WF remains after development. In other words, when only the first exposure process is performed, the exposure light is shielded against the negative photosensitive polyimide resin film EPI in the dicing region DR in the end region ER of the semiconductor wafer WF. In the dicing region DR within the partial region ER, the negative photosensitive polyimide resin film EPI is removed. On the other hand, when the second exposure process is performed after the first exposure process, the exposure light is irradiated to all the negative photosensitive polyimide films EPI formed in the end region ER of the semiconductor wafer WF. As a result, all of the negative photosensitive polyimide resin film EPI formed in the end region ER remains, including the one formed in the dicing region DR.

  Specifically, when a development process is performed subsequent to the first exposure process and the second exposure process, the negative photosensitive polyimide resin film EPI is patterned as shown in FIG. In FIG. 15, in the chip region CR, a negative photosensitive polyimide resin film EPI is formed so as to open the formation region of the pad PD and cover the other regions. That is, by the first exposure process, the exposure light is shielded in the pad PD formation region, and the exposure light is irradiated in the region other than the pad PD formation region. In the subsequent second exposure process, the exposure light is shielded, so that the patterning by the first exposure process is maintained. As a result, the negative photosensitive polyimide resin film EPI is patterned so as to open the pad PD formation region.

  On the other hand, in the dicing region DR (inside), patterning is performed so as to remove the negative photosensitive polyimide resin film EPI formed so as to be embedded in the opening OP1. That is, the negative photosensitive polyimide resin film EPI embedded in the opening OP1 is not irradiated with the exposure light by the first exposure process, and in the opening OP1 in the subsequent second exposure process. The exposure light is not irradiated to the embedded negative photosensitive polyimide resin film EPI. For this reason, the negative photosensitive polyimide resin film EPI embedded in the opening OP1 is removed after the development processing.

  On the other hand, in the dicing region DR (end portion), patterning is performed so that the negative photosensitive polyimide resin film EPI formed so as to be embedded in the opening OP2 remains. That is, the exposure light is not irradiated to the negative photosensitive polyimide resin film EPI embedded in the opening OP2 by the first exposure process. However, exposure light is irradiated to the dicing region DR (end portion) in the end portion region ER by the second exposure process performed thereafter. As a result, even after the development processing, the negative photosensitive polyimide film EPI remains in the opening OP2.

  As described above, the negative photosensitive polyimide resin film EPI serving as the surface protective film can be patterned, and the processing on the main surface of the semiconductor wafer WF is completed. Subsequently, in the first embodiment, the back surface grinding of the semiconductor wafer WF is performed. Before carrying out the back surface grinding of the semiconductor wafer WF, as shown in FIG. 16, a protective tape PT is attached to the main surface of the semiconductor wafer WF via an adhesive ADH. Then, as shown in FIG. 17, the back surface of the semiconductor wafer WF is ground using a grinder GD.

  In FIG. 16, in the chip region CR, the protective tape PT is attached to the negative photosensitive polyimide resin film EPI from which the pad PD is exposed via the adhesive ADH. In this case, since the region where the pad PD is exposed is dented, a gap is generated between the adhesive ADH and the pad PD. However, since the chip region CR is in a region inside the end region ER of the semiconductor wafer WF, even if a gap is generated, it is irrelevant to mixing of grinding scraps.

  Similarly, in the dicing region DR (inside), since the negative photosensitive polyimide resin film EPI embedded in the opening OP1 is removed, there is a gap between the opening OP1 and the dicing groove DIT and the adhesive ADH. A gap is created. Also in this case, since the dicing region DR (inside) is in the region inside the end region ER of the semiconductor wafer WF, even if a gap is generated, it is irrelevant to mixing of grinding waste.

  On the other hand, in the dicing region DR (end portion), if a gap is generated between the adhesive ADH and the opening OP2, the gap is exposed on the outer peripheral portion (side surface) of the semiconductor wafer WF. Grinding waste enters through the gap. For this reason, in the dicing region DR (end portion), if a gap is formed between the adhesive ADH and the opening OP2, there arises a problem that grinding waste enters the main surface of the semiconductor wafer WF. For this reason, it can be seen that in the dicing region DR (end portion), it is necessary to fill a gap from the viewpoint of preventing mixing of grinding waste.

  Here, in the first embodiment, since the negative photosensitive polyimide resin film EPI is embedded in the opening OP2 in the dicing region DR (end portion), the embedded negative photosensitive polyimide resin film is embedded in the opening OP2. EPI and adhesive material ADH are firmly attached. That is, in the dicing region DR (end portion), the negative type polyimide resin film EPI is embedded in the opening OP2, and the negative type photosensitive polyimide resin film EPI and the adhesive ADH are brought into close contact with each other. Part), there is no gap. This is a feature of the first embodiment. That is, the opening OP2 reaching the outer peripheral portion (side surface) of the semiconductor wafer WF and the dicing groove DIT are filled with the negative photosensitive polyimide resin film EPI, and the negative photosensitive polyimide resin film EPI is bonded to the adhesive ADH. Since the contact is firmly made, no gap is generated between the opening OP2 and the dicing groove DIT and the adhesive ADH. This means that no gap is exposed at the outer peripheral portion (side surface) of the semiconductor wafer WF. As a result, when back grinding is performed on the semiconductor wafer WF, grinding scraps are generated, but in the first embodiment, since there is no gap in the dicing region DR (end portion), grinding is performed. It is possible to prevent waste from entering the main surface of the semiconductor wafer WF. Therefore, it is possible to prevent grinding waste from entering the main surface side of the semiconductor wafer WF and adhering to the pads PD formed in the chip region CR of the semiconductor wafer WF.

  Subsequently, as shown in FIG. 18, a plurality of semiconductor chips are obtained by dicing the semiconductor wafer WF using the dicer D. FIG. 19 shows one semiconductor chip CHP, and a pad PD is formed on the main surface side (element formation surface side) of the semiconductor chip CHP.

  Next, as shown in FIG. 20, the semiconductor chip CHP is mounted on the wiring board WB. At this time, terminals TE are formed on the chip mounting surface side of the wiring board WB. Then, as shown in FIG. 21, the pad PD formed on the semiconductor chip CHP and the terminal TE formed on the wiring board WB are connected by a wire W made of a gold wire or the like. Here, in the first embodiment, since there is no gap in the dicing region DR (end portion), it is possible to prevent grinding waste generated during back surface grinding from entering the main surface of the semiconductor wafer WF. Therefore, it is possible to prevent grinding waste from entering the main surface side of the semiconductor wafer WF and adhering to the pads PD formed in the chip region CR of the semiconductor wafer WF. For this reason, the adhesive strength between the pad PD and the wire W can be ensured. After that, as shown in FIG. 22, the semiconductor chip CHP and the wires W are sealed with a resin MR so as to cover them.

  Subsequently, as shown in FIG. 23, solder balls SB to be external connection terminals are formed on the back surface (surface opposite to the chip mounting surface) of the wiring board WB. Then, as shown in FIG. 24, by separating the wiring board WB into individual pieces, the semiconductor device according to the first embodiment as shown in FIG. 25 can be manufactured.

  As shown in FIG. 16, the first embodiment is characterized in that a negative photosensitive polyimide resin film EPI is formed so as to fill the opening OP2 and the dicing groove DIT in the dicing region DR (end part). It is. That is, when the opening OP2 and the dicing groove DIT are not filled with the negative photosensitive polyimide resin film EPI, when the protective tape PT is attached to the opening OP2 via the adhesive ADH, the adhesive A gap is generated between the ADH and the opening OP2. This gap is exposed on the side surface of the semiconductor wafer WF. Therefore, there is a possibility that polishing waste generated when grinding the back surface of the semiconductor wafer WF enters from a gap exposed on the side surface of the semiconductor wafer WF. On the other hand, in the first embodiment, the negative photosensitive polyimide resin film EPI is formed so as to fill the opening OP2 and the dicing groove DIT formed in the dicing region DR (end portion). For this reason, when the protective tape PT is attached to the opening OP2 via the adhesive ADH, the adhesive ADH and the negative photosensitive polyimide resin film EPI embedded in the opening OP2 are firmly adhered to each other. There is no gap in OP2. As a result, the dicing groove DIT and the opening OP2 reaching the side surface of the semiconductor wafer WF are filled with the negative photosensitive polyimide resin film EPI. Mixing into the main surface side of the wafer WF can be suppressed.

  As described above, the first embodiment is characterized in that the negative photosensitive polyimide resin film EPI is formed so as to fill the opening OP2 and the dicing groove DIT in the dicing region DR (end portion). This configuration can be realized by using a negative photosensitive polyimide resin film EPI. That is, in the first embodiment, first, as shown in FIG. 13, a first exposure process for forming a circuit pattern (opening pattern of the pad PD) in the chip region CR is performed. In the first exposure process, the negative photosensitive resin film EPI formed in the dicing region DR (inside) and the dicing region DR (end portion) is removed. That is, the first exposure process is performed on the negative photosensitive polyimide resin film EPI formed in the dicing region DR (inside) and the dicing region DR (end) so that the exposure light is shielded. If development processing is performed in this state, the negative photosensitive resin film EPI formed in the opening OP2 of the dicing region DR (end portion) is removed. Therefore, in the first embodiment, in order to leave the negative photosensitive polyimide resin film EPI formed in the opening OP2 of the dicing DR (end portion), the second exposure process (peripheral) shown in FIG. Exposure). Accordingly, the exposure light is also irradiated to the negative photosensitive polyimide resin film EPI in the opening OP2 that is not irradiated with the exposure light in the first exposure process. At this time, by setting the polyimide resin film formed in the opening OP2 as a negative photosensitive polyimide resin film EPI, it can be left after development.

  For example, consider the case of using a positive photosensitive polyimide resin film. In this case, in order to leave the positive photosensitive polyimide resin film in the opening OP2 of the dicing region DR (end portion), it is necessary not to irradiate the dicing region DR (end portion) with exposure light. However, in the first exposure process for forming a circuit pattern (opening pattern of the pad PD) in the chip region CR, the opening OP1 in the dicing region DR (inside) and the opening OP2 in the dicing region (end) are formed. An exposure process is performed so as to remove the positive photosensitive polyimide resin film. Specifically, exposure light is irradiated to the positive photosensitive polyimide resin film formed in the opening OP1 of the dicing region DR (inside) and the opening OP2 of the dicing region DR (end). . At this time, in order to leave the positive photosensitive polyimide resin film formed in the opening OP2 of the dicing region DR (end portion), it is not necessary to irradiate the exposure light, but it has already been performed in the first exposure process. Since exposure light is irradiated to the positive photosensitive polyimide resin film formed in the opening OP2 of the dicing region DR (end portion), the positive photosensitive resin is formed in the opening OP2 of the dicing region DR (end portion). The polyimide resin film cannot be left.

  Here, it can be considered that the exposure light should not be irradiated to the dicing region DR (end) in the first exposure process. However, since the first exposure process performs the exposure process on a plurality of chip areas CR in one shot, when the exposure process is not performed up to the area protruding from the semiconductor wafer WF (corresponding to reducing the number of shots), The number of normal chip regions CR subjected to exposure processing decreases. That is, even in one shot of the region that protrudes from the semiconductor wafer WF, a plurality of chip regions CR are exposed in this one shot. For this reason, a normal rectangular chip region CR that can be a product is included in one shot. Therefore, in order to perform exposure processing on all normal rectangular chip regions CR that are products, it is necessary to perform one shot including a region protruding from the semiconductor wafer WF. At this time, performing one-shot exposure processing including a region protruding from the semiconductor wafer WF means that the first exposure processing is also performed on the end region ER of the semiconductor wafer WF. Therefore, it can also be said that the first exposure process is performed also on the dicing region DR (end portion). From this, in order to leave the polyimide resin film formed in the opening OP2 of the dicing region DR (end portion), it cannot be realized by forming the polyimide resin film from a positive photosensitive polyimide resin film, It can be seen that there is a need to use a negative photosensitive polyimide resin film EPI.

  However, in the following cases, even if a positive photosensitive polyimide resin film is used as the polyimide resin film, the positive photosensitive polyimide resin film may be left in the opening OP2 of the dicing region DR (end portion). it can. FIG. 26 is a diagram showing a state of the first exposure process in the case of using a positive photosensitive polyimide resin film. In FIG. 26, one shot EXR2 is performed for one chip region CR. In this case, it is not necessary to expose the end region ER of the semiconductor wafer WF in order to perform the first exposure process on the normal rectangular chip region CR that is the product. This means that it is possible not to irradiate the positive type photosensitive polyimide resin film formed in the end region ER of the semiconductor wafer WF with exposure light. That is, the positive photosensitive polyimide resin film formed in the opening OP2 of the dicing region DR (end portion) can be left without being irradiated with exposure light.

  In addition, in this Embodiment 1, although the case where the photosensitive polyimide resin film which has photosensitivity is used as a polyimide resin film is demonstrated, it is not restricted to this, For example, normal polyimide resin which does not have photosensitivity A membrane may be used. In this case, patterning of the polyimide resin film is performed using a resist film formed on the polyimide resin film, and this resist film becomes a negative resist film.

(Embodiment 2)
In the first embodiment, a BGA (Ball Grid Array) type package has been described as a package of a semiconductor device. In the second embodiment, a QFP (Quad Flat Package) type package will be described.

  The manufacturing method of the semiconductor device in the second embodiment is almost the same as the manufacturing method of the semiconductor device in the first embodiment. Specifically, the same applies to FIGS. Therefore, also in the second embodiment, as shown in FIG. 16, the negative photosensitive polyimide resin film EPI is formed so as to fill the opening OP2 and the dicing groove DIT formed in the dicing region DR (end portion). The For this reason, when the protective tape PT is attached to the opening OP2 via the adhesive ADH, the adhesive ADH and the negative photosensitive polyimide resin film EPI embedded in the opening OP2 are firmly adhered to each other. There is no gap in OP2. As a result, the dicing groove DIT and the opening OP2 reaching the side surface of the semiconductor wafer WF are filled with the negative photosensitive polyimide resin film EPI. Mixing into the main surface side of the wafer WF can be suppressed.

  As shown in FIG. 19, after obtaining a plurality of semiconductor chips CHP by dicing the semiconductor wafer, a lead frame LF as shown in FIG. 27 is prepared. As shown in FIG. 27, the lead frame LF mainly includes a die pad DP on which a semiconductor chip is mounted, a frame portion FP, an inner lead IL, and an outer lead OL. In the lead frame LF, a region surrounded by the mold line ML1 is a region sealed with a resin body. Hereinafter, a process of manufacturing a package using the lead frame LF configured as described above will be described.

  FIG. 28 shows a cross section of the lead frame. As shown in FIG. 28, a die pad DP is disposed at the center, a frame portion FP is formed around the die pad DP, and an inner lead IL is formed outside thereof.

  Subsequently, as shown in FIG. 29, the semiconductor chip CHP is mounted on the die pad DP. The semiconductor chip CHP and the die pad DP are fixed by, for example, a die attach film (not shown) or an adhesive (not shown).

  Thereafter, as shown in FIG. 30, the pad PD formed on the semiconductor chip CHP and the inner lead IL are electrically connected by the wire W. Here, in the second embodiment, since there is no gap in the dicing region DR (end portion), it is possible to prevent grinding waste generated during back surface grinding from entering the main surface of the semiconductor wafer WF. Therefore, it is possible to prevent grinding waste from entering the main surface side of the semiconductor wafer WF and adhering to the pads PD formed in the chip region CR of the semiconductor wafer WF. For this reason, the adhesive strength between the pad PD and the wire W can be ensured.

  Then, as shown in FIG. 31, the semiconductor chip CHP, the wire W, the inner lead IL, the die pad DP, and the frame portion FP are sealed with a resin MR. Thereafter, an outer lead (not shown) is formed, and the semiconductor device according to the second embodiment as shown in FIG. 32 can be manufactured.

(Embodiment 3)
In the first embodiment, the example in which the dicing groove DIT is formed also in the dicing region DR (end portion) has been described. However, in the third embodiment, the dicing groove DIT is not formed in the dicing region DR (end portion). An example will be described.

  FIG. 33 is an enlarged view of a part of the semiconductor wafer. As shown in FIG. 33, a plurality of chip regions CR are formed in the enlarged region, and a plurality of pads PD are formed in the chip region CR. A dicing region DR is formed so as to partition the chip region CR. Further, an end region ER is formed within a predetermined range from the outer periphery of the semiconductor wafer. Here, the third embodiment is characterized in that no dicing groove is formed in the end region ER.

  34 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 34, an interlayer insulating film ML is formed on the semiconductor substrate 1S, and a surface protective film PAS is formed on the interlayer insulating film ML. An opening OP is formed so as to open the interlayer insulating film ML and the surface protective film PAS. In the third embodiment, no dicing groove is formed in the semiconductor substrate 1S below the opening OP. For this reason, although inferior to the first embodiment, when the protective tape PT is pasted on the surface protection film PAS including the opening OP via the adhesive ADH, the gap between the opening OP and the adhesive ADH is sufficiently reduced. be able to. As a result, it is possible to suppress polishing waste generated when grinding the back surface of the semiconductor wafer from entering the main surface side of the semiconductor wafer through the gap.

  That is, when the dicing groove is formed in the lower layer of the opening OP, the gap becomes larger by the depth of the dicing groove. In the third embodiment, the dicing groove is formed in the lower layer of the opening OP. Therefore, the gap can be made sufficiently small. For this reason, according to the third embodiment, it is possible to sufficiently suppress the polishing waste from entering the main surface side of the semiconductor wafer from the gap. However, in the third embodiment, since the peripheral exposure as in the first embodiment is not necessary, the number of steps can be reduced.

  In order to prevent the dicing groove from being formed in the dicing region DR (end portion) as in the third embodiment, for example, in the silicide film forming process of the MISFET, the surface of the dicing region DR (end portion) is formed. This can be dealt with by forming a silicide film. That is, by forming a silicide film on the surface of the semiconductor substrate 1S in the dicing region DR (end portion), this silicide film functions as an etching stopper when the interlayer insulating film is etched. Thereby, a dicing groove can be prevented from being formed in the surface of the semiconductor substrate 1S in the dicing region DR (end portion).

(Embodiment 4)
In the fourth embodiment, an example in which the surface protection film PAS is formed in the opening OP in addition to the point that the dicing groove is not formed in the end region ER as in the third embodiment will be described.

  FIG. 35 is an enlarged view of a part of the semiconductor wafer. As shown in FIG. 35, a plurality of chip regions CR are formed in the enlarged region, and a plurality of pads PD are formed in the chip region CR. A dicing region DR is formed so as to partition the chip region CR. Further, an end region ER is formed within a predetermined range from the outer periphery of the semiconductor wafer. Here, the fourth embodiment is characterized in that no dicing groove is formed in the end region ER.

  36 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 36, an interlayer insulating film ML is formed on the semiconductor substrate 1S, and a surface protective film PAS is formed on the interlayer insulating film ML. An opening OP is formed so as to open the interlayer insulating film ML and the surface protective film PAS. In the fourth embodiment, a dicing groove is not formed in the semiconductor substrate 1S below the opening OP, and the surface protective film PAS is also embedded in the opening OP. For this reason, when adhering the protective tape PT on the surface protective film PAS including the inside of the opening OP via the adhesive ADH, the gap between the opening OP and the adhesive ADH can be sufficiently reduced. As a result, it is possible to suppress polishing waste generated when grinding the back surface of the semiconductor wafer from entering the main surface side of the semiconductor wafer through the gap.

  That is, when the dicing groove is formed in the lower layer of the opening OP, the gap becomes larger by the depth of the dicing groove, but in the fourth embodiment, the dicing groove is formed in the lower layer of the opening OP. Therefore, the gap can be made sufficiently small. Furthermore, in the fourth embodiment, since the surface protective film PAS is also formed inside the opening OP, the gap can be further reduced. For this reason, according to the fourth embodiment, it is possible to sufficiently suppress polishing waste from entering the main surface side of the semiconductor wafer from the gap.

  In order to prevent the dicing groove from being formed in the dicing region DR (end portion) as in the fourth embodiment, for example, in the silicide film forming process of the MISFET, the surface of the dicing region DR (end portion) is formed. This can be dealt with by forming a silicide film. That is, by forming a silicide film on the surface of the semiconductor substrate 1S in the dicing region DR (end portion), this silicide film functions as an etching stopper when the interlayer insulating film is etched. Thereby, a dicing groove can be prevented from being formed in the surface of the semiconductor substrate 1S in the dicing region DR (end portion).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1S semiconductor substrate ADH adhesive CHP semiconductor chip CNT1 contact hole CR chip area D dicer DIT dicing groove DP die pad DR dicing area EPI negative photosensitive polyimide resin film ER end area EXR1 1 shot EXR2 1 shot FP frame section GD grinder Lead IL1 interlayer insulating film IL2 interlayer insulating film IL3 interlayer insulating film LF lead frame L1 wiring L2 wiring L3 wiring MR resin ML interlayer insulating film ML1 mold line OL outer lead OP opening OP1 opening OP2 opening PAS surface protective film PD plug PL pad PLG2 plug PLG3 plug PT protective tape Q ₁ n-channel MISFET
Q ₂ p-channel MISFET
RA area SB Solder ball SIN Silicon nitride film TE Terminal TH2 Through hole TH3 Through hole W Wire WB Wiring board WF Semiconductor wafer

Claims (21)

(A) forming a MISFET in the plurality of chip regions of the semiconductor wafer having a plurality of chip regions and a divided region dividing the plurality of chip regions on a main surface side;
(B) forming a multilayer wiring layer on the MISFET formed in the plurality of chip regions, and forming a pad on the uppermost layer of the multilayer wiring layer;
(C) forming a groove in the divided region of the semiconductor wafer;
(D) forming a surface protective film on the plurality of chip regions and the divided regions where the pads of the semiconductor wafer are formed;
(E) processing the surface protective film so as to expose the pad in the plurality of chip regions, and leaving the surface protective film in an end region within a predetermined range from the outer peripheral portion of the semiconductor wafer; ,
(F) a step of attaching a protective tape to the entire main surface of the semiconductor wafer via an adhesive;
(G) A method of manufacturing a semiconductor device, comprising a step of grinding a back surface opposite to a main surface of the semiconductor wafer to which the protective tape is attached. A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the surface protection film is formed inside the groove in a region where the divided region and the end region overlap in a planar manner. A method of manufacturing a semiconductor device according to claim 1,
In the step (e), the surface protection film formed in the trench is removed in the divided region that does not overlap the end region in a plan view. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the divided region is a dicing region for dicing. A method of manufacturing a semiconductor device according to claim 4,
(H) After the step (g), a plurality of semiconductor chips separated from the plurality of chip regions are obtained by dicing along the divided regions formed on the main surface of the semiconductor wafer. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
(I) After the step (h), the step of mounting the separated semiconductor chip on a wiring board;
(J) After the step (i), the step of electrically connecting the pad formed on the semiconductor chip and the terminal formed on the wiring board with a wire Device manufacturing method. A method of manufacturing a semiconductor device according to claim 5,
(K) After the step (h), the step of mounting the separated semiconductor chip on a lead frame;
(L) After the step (k), the semiconductor has a step of electrically connecting the pad formed on the semiconductor chip and the lead formed on the lead frame with a wire. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 1,
The surface protective film is a photosensitive polyimide resin film,
In the step (e), by patterning the photosensitive polyimide resin film, the photosensitive polyimide resin film is processed so as to expose the pads in the plurality of chip regions, and in the end region, A method of manufacturing a semiconductor device, comprising leaving a photosensitive polyimide resin film. A method for manufacturing a semiconductor device according to claim 8, comprising:
The method of manufacturing a semiconductor device, wherein the photosensitive polyimide resin film is a negative photosensitive polyimide resin film. A method for manufacturing a semiconductor device according to claim 9, comprising:
The step (e)
(E1) exposing the photosensitive polyimide resin film formed in the plurality of chip regions and the divided regions using a mask formed with a circuit pattern;
(E2) After the step (e1), the method includes a step of performing peripheral exposure by irradiating the end region of the divided region with exposure light. A method for manufacturing a semiconductor device according to claim 10, comprising:
In the step (e1), two or more chip regions are exposed in one exposure process. A method for manufacturing a semiconductor device according to claim 8, comprising:
The photosensitive polyimide resin film is a positive photosensitive polyimide resin film,
In the step (e), an exposure process is performed for each of the chip areas using a mask on which a circuit pattern is formed, and an exposure process is not performed for an area protruding from the semiconductor wafer. A method of manufacturing a semiconductor device, wherein the photosensitive polyimide resin film that is not patterned is left in a partial region. (A) forming a MISFET in the plurality of chip regions of the semiconductor wafer having a plurality of chip regions and a divided region dividing the plurality of chip regions on a main surface side;
(B) forming a multilayer wiring layer on the MISFET formed in the plurality of chip regions, and forming a pad on the uppermost layer of the multilayer wiring layer;
(C) Of the divided regions of the semiconductor wafer, a groove is formed in a region that does not overlap with the end region within a predetermined range from the outer peripheral portion of the semiconductor wafer, and the divided region and the end region A step of not forming the groove in a region where the two overlap in a plane,
(D) forming a surface protective film on the plurality of chip regions and the divided regions where the pads of the semiconductor wafer are formed;
(E) in the plurality of chip regions, processing the surface protective film so as to expose the pads, and removing the surface protective film formed in the divided regions;
(F) a step of attaching a protective tape to the entire main surface of the semiconductor wafer via an adhesive;
(G) A method of manufacturing a semiconductor device, comprising a step of grinding a back surface opposite to a main surface of the semiconductor wafer to which the protective tape is attached. A method for manufacturing a semiconductor device according to claim 13, comprising:
The method of manufacturing a semiconductor device, wherein the divided region is a dicing region for dicing. A method for manufacturing a semiconductor device according to claim 14, comprising:
(H) After the step (g), a plurality of semiconductor chips separated from the plurality of chip regions are obtained by dicing along the divided regions formed on the main surface of the semiconductor wafer. A method for manufacturing a semiconductor device. (A) forming a MISFET in the plurality of chip regions of the semiconductor wafer having a plurality of chip regions and a divided region dividing the plurality of chip regions on a main surface side;
(B) forming a multilayer wiring layer on the MISFET formed in the plurality of chip regions, and forming a pad on the uppermost layer of the multilayer wiring layer;
(C) Of the divided regions of the semiconductor wafer, a groove is formed in a region that does not overlap with the end region within a predetermined range from the outer peripheral portion of the semiconductor wafer, and the divided region and the end region A step of not forming the groove in a region where the two overlap in a plane,
(D) forming a surface protective film on the plurality of chip regions and the divided regions where the pads of the semiconductor wafer are formed;
(E) processing the surface protective film so as to expose the pad in the plurality of chip regions, and leaving the surface protective film in a region where the divided region and the end region overlap in a plane;
(F) a step of attaching a protective tape to the entire main surface of the semiconductor wafer via an adhesive;
(G) A method of manufacturing a semiconductor device, comprising a step of grinding a back surface opposite to a main surface of the semiconductor wafer to which the protective tape is attached. A method of manufacturing a semiconductor device according to claim 16,
In the step (e), the surface protection film formed in the trench is removed in the divided region that does not overlap the end region in a plan view. A method of manufacturing a semiconductor device according to claim 16,
The method of manufacturing a semiconductor device, wherein the divided region is a dicing region for dicing. A method of manufacturing a semiconductor device according to claim 18,
(H) After the step (g), a plurality of semiconductor chips separated from the plurality of chip regions are obtained by dicing along the divided regions formed on the main surface of the semiconductor wafer. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 16,
The surface protective film is a negative photosensitive polyimide resin film,
In the step (e), by patterning the negative photosensitive polyimide resin film, the negative photosensitive polyimide resin film is processed so as to expose the pads in the plurality of chip regions, and end regions are formed. Then, the manufacturing method of the semiconductor device characterized by leaving the said negative photosensitive polyimide resin film. A method of manufacturing a semiconductor device according to claim 20,
The step (e)
(E1) exposing the negative photosensitive polyimide resin film formed in the plurality of chip regions and the divided regions using a mask on which a circuit pattern is formed;
(E2) After the step (e1), the method includes a step of performing peripheral exposure by irradiating the end region of the divided region with exposure light.

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