JP2010225200A - Semiconductor memory device and method for manufacturing semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device 3 which has a large storage capacity and high reliability, and to provide a method for manufacturing the semiconductor memory device 3. <P>SOLUTION: The device includes: a plurality of first memory cells in which data of a 2<SP>N</SP>value (N is a natural number of 2 or more) are stored; a plurality of second memory cells in which data of a 2<SP>M</SP>value (M is a natural number smaller than N) is stored; and a CPU 11 which performs control of storing data in the second memory cells according to a first command, control of storing, in respectively one first memory cell, data in the respectively 2<SP>(N-M)</SP>second memory cells in which data of 2<SP>M</SP>value are stored according to a second command, and control of erasing the data stored in the second memory cells. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device that stores data in a semiconductor memory unit according to a command from a connected host, and a method for manufacturing the semiconductor memory device, and more particularly, a multi-value that stores four or more values in one memory cell. The present invention relates to a semiconductor memory device corresponding to memory and a method for manufacturing the semiconductor memory device.

  A semiconductor memory device having a NAND flash memory unit uses a charge amount of electrons injected into a floating gate of a memory cell (hereinafter also simply referred to as “cell”) as digital bit information. The advent of multi-value memory cells capable of storing multi-value data of 2 bits or more, that is, quaternary or more, in one memory cell greatly contributes to the improvement of the storage density of the semiconductor memory device.

  Here, when the semiconductor memory device is mounted on a printed wiring board such as a cellular phone, the semiconductor memory device is temporarily fixed to the printed wiring board using a solder paste, and then heated in a reflow furnace to fix the solder paste. A method of performing soldering is generally used.

  On the other hand, the host has data to be stored in advance in the semiconductor memory device at the time of shipment. For example, firmware data used by the host. When the host is a mobile phone or the like, it is data such as music samples or video samples. However, in order to store data in the host after completion of the host and before shipment, it is necessary to carry out each unit via an external interface of the host such as a USB.

  For this reason, a method of storing data in a plurality of semiconductor memory devices using a gang writer before mounting the semiconductor memory device on a printed wiring board may be used. In this case, the semiconductor memory device in which data is stored is heated to a high temperature, for example, from 220 ° C. to 260 ° C. in the process of heating in the reflow furnace.

  When a semiconductor memory device storing data is heated at a high temperature, electrons injected into the floating gate of the memory cell may be discharged from the floating gate due to thermal energy. Then, an error may occur when reading stored data.

  In particular, a semiconductor memory device storing data in a multi-level memory cell has a larger storage capacity than a binary memory semiconductor memory device storing 1-bit data in one memory cell, but reads the stored data. Sometimes, errors often occur, that is, the reliability of the semiconductor memory device may be reduced.

JP 2005-108303 A

  An object of the present invention is to realize a semiconductor memory device having a large storage capacity and high reliability and a method for manufacturing the semiconductor memory device.

According to one aspect of the present invention, there is provided a semiconductor memory device that can be connected to a host that issues a predetermined command and stores data in a semiconductor memory unit, and has 2 ^N values (where N is a natural number of 2 or more). In accordance with a first command, a plurality of second memory cells storing data of 2 ^M values (where M is a natural number less than N), and a plurality of second memory cells. Control to store data in each of the memory cells, and data in each of the 2 ^(N−M) second memory cells in which 2 ^M- value data is stored in accordance with the second command, each in the first memory There is provided a semiconductor memory device comprising: a control unit that performs control to store in a cell and control to erase data stored in a second memory cell.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device that is connectable to a host that issues a predetermined command and stores data in a semiconductor memory unit having a plurality of memory cells. The plurality of memory cells store a plurality of first memory cells storing data of 2 ^N values (where N is a natural number of 2 or more) and data of 2 ^M values (where M is a natural number less than N). A first write step for storing 2 ^M- value data in the second memory cell in accordance with the first command, and 2 ^M- value data in accordance with the second command. 2 ^(N−M) (where N is a natural number greater than M) second memory cell data is stored in one of the plurality of first memory cells, and ² in first storage step ^(N-M) number of Erasing data stored in the second memory cell, a method of manufacturing a semiconductor memory device characterized by comprising a redrawing process, it is provided.

  According to the present invention, it is possible to provide a semiconductor memory device having a large storage capacity and high reliability and a method for manufacturing the semiconductor memory device.

1 is a configuration diagram illustrating a configuration of a semiconductor memory device according to a first embodiment. It is a schematic diagram of the threshold voltage distribution of the memory cell for explaining multilevel storage. 3 is a flowchart for explaining a flow of a manufacturing method of the semiconductor memory device according to the first embodiment; 4A and 4B are schematic diagrams for explaining the storage state of the memory unit of the semiconductor memory device according to the first embodiment, in which FIG. 4A shows a four-value storage state and FIG. 4B shows a binary storage state. ing. It is a schematic diagram when the printed wiring board with which the semiconductor memory device of 1st Embodiment was mounted is observed from the side. It is a schematic diagram for demonstrating the 2nd write-in process (rewriting process) in the semiconductor memory device of 1st Embodiment. It is a schematic diagram which shows the threshold voltage distribution change of the binary storage in the semiconductor memory device of 2nd Embodiment.

<First Embodiment>
The semiconductor memory device 3 and the manufacturing method thereof according to the first embodiment of the present invention will be described below with reference to the drawings.
First, the schematic configuration of the semiconductor memory device 3 according to the first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the semiconductor storage device 3 of the present embodiment stores data received from the host 4 and transmits the stored data to the host 4. The semiconductor memory device 3 includes a semiconductor memory unit (hereinafter also simply referred to as “memory unit”) 13 and a memory controller 2 having a CPU 11 as a control unit. The semiconductor memory device 3 and the host 4 constitute a memory system 5. The memory system 5 is, for example, a mobile phone equipped with the semiconductor memory device 3. The memory unit 13 includes a NAND flash memory, a word line control unit 13A, and the like. A large number of memory cells 13D as unit cells have bit lines (not shown) used for writing, word lines 13E used for reading, and the like. It has the structure connected by. The word line control unit 13A applies a predetermined read voltage to the word line 13E when data is read.

  Here, the minimum writing unit of the memory unit 13 composed of the NAND flash memory is a page. The page capacity is, for example, 8 kbytes. A unit of 128 pages is defined as a block. That is, data of 8 kbytes × 128 = 1024 kbytes = 1 MB can be stored in one block. A block is the smallest unit that can be erased. For this reason, the memory unit 13 of the semiconductor memory device 3 cannot be rewritten in units of pages, and must be written after erasing the entire block. Therefore, when the stored data is rewritten, so-called moving is performed in which an erased block is prepared and the page data to be rewritten is copied there.

  The memory cell 13D of the memory unit 13 of the semiconductor memory device 3 of the present embodiment is a multi-value memory cell that can store N-bit (N is a natural number of 2 or more) data in one memory cell. Hereinafter, a four-value memory cell with N = 2 will be described as an example.

  The memory controller 2 includes a ROM 10, a CPU 11, a RAM 18, a host I / F (interface) 14, an error correcting code (ECC) unit 15, and a NAND I / F connected via a bus 17. (Interface) 16.

  The memory controller 2 uses the CPU 11 to perform data transmission / reception with the host 4 via the host I / F 14 and data transmission / reception with the memory unit 13 via the NAND I / F 16. The memory controller 2 realizes address management of the memory unit 13 by FW (Firmware) executed by the CPU 11. Further, the control of the entire semiconductor memory device 3 in response to command input from the host 4 is also stored in the ROM 10 which is executed by the CPU 11 by the FW, and the control program of the semiconductor memory device 3 is stored in the RAM 18 for address management. Necessary address conversion tables and the like are stored.

  The ECC unit 15 includes an encoder 15A that generates and assigns an error correction code when storing data, and a decoder 15B that decodes the read encoded data when reading data.

  In the semiconductor memory device 3, when an error occurs in the stored data, the ECC unit 15 performs error correction. However, the correction capability of the ECC unit 15 is determined in consideration of the normal use temperature of the semiconductor memory device 3, that is, the use state at room temperature, up to a high temperature far from the normal use temperature such as the reflow process. Is not determined by consideration. This is because the scale of the ECC unit 15 increases and the cost of the semiconductor memory device 3 increases in order to increase the correction capability of the ECC unit 15 so as to cope with high temperatures.

  Next, a data storage process of the semiconductor memory device 3 of the present embodiment will be described with reference to FIG. FIG. 2 is a schematic diagram of the threshold voltage distribution of the memory cells for explaining multi-level storage, where the horizontal axis indicates the threshold voltage Vth, the vertical axis indicates the frequency, in other words, the number n of memory cells. 2A shows the Vth distribution of the memory cell in the erased state, FIG. 2B shows the Vth distribution of the memory cell when storing the first page, and FIG. 2C shows the Vth distribution of the memory cell when storing the second page. Distribution is shown.

  In quaternary storage, first, data of the first page (hereinafter also referred to as “LowerPage”) is written into each memory cell, and then data of the second page (hereinafter also referred to as “UpperPage”) is the same. It is written in the memory cell. Here, when the write data is “1”, the threshold voltage of the memory cell 13D does not change and the data of the memory cell 13D does not change by the write operation. When the write data is “0”, electrons are injected into the floating gate by the write operation in which the write voltage is applied to the word line 13E, and the threshold voltage of the memory cell changes.

  As shown in FIG. 2A, the data in the erased memory cell is in state 0. First, as shown in FIG. 2B, data of the first page is written into the memory cell with the write voltage Vp1. When the write data is “1”, the memory cell remains in the state 0. When the write data is “0”, the memory cell is in the state 1.

  Next, as shown in FIG. 2C, the data of the second page is written. At this time, when the write data “0” is supplied to the memory cell in the state 1 by the write operation of the first page, the memory cell is in the state 3 by the write voltage Vp3. When the write data “0” is supplied to the memory cell whose data remains in the state 0 by the write operation of the first page, the memory cell is brought into the state 2 by the write voltage Vp2. Further, when write data “1” is supplied to a memory cell that has entered state 1 or state 0 by the write operation of the first page, the memory cell remains in state 1 or state 0.

  The write voltages Vp1 to Vp3 are applied to the word line 13E while stepping up in a pulse manner, for example, with a voltage of about 14V to 20V so as to fall within the threshold voltage range corresponding to the data to be written.

  In the data reading process, the stored data is determined based on the difference in the threshold voltage Vth of the memory cell. Here, the memory cell 13D in the state of storing quaternary data in the four states has an error because the threshold voltage distribution is more complicated than the memory cell in the state of storing the binary values in the two states. Is likely to occur.

  Next, the flow of the manufacturing method of the semiconductor memory device 3 of the present embodiment will be described with reference to FIGS. FIG. 3 is a flowchart for explaining the flow of the manufacturing method of the semiconductor memory device of the present embodiment.

<Step S10> Preparation of Semiconductor Memory Device First, the semiconductor memory device 3 is prepared. At this stage, nothing is stored in the memory unit 13 of the semiconductor memory device 3. The semiconductor memory device 3 is a chip type semiconductor memory device integrated on, for example, one chip that can be mounted on a printed wiring board.

<Step S11> Binary writing (first command reception, first writing step)
Using a gang writer 4A capable of simultaneously writing to a plurality of semiconductor memory devices, a music sample or the like that is data stored in advance in the semiconductor memory device 3 is written. That is, at this time, the gang writer 4A to which the semiconductor memory device 3 is connected functions as a host.

  Then, the gang writer 4 </ b> A that is the first host transmits a binary write command that is the first command to the semiconductor memory device 3. The semiconductor memory device 3 that has received the binary write command from the gang writer 4A binary stores the data received from the gang writer 4A in the memory cell 13D capable of quaternary storage. That is, as shown in FIG. 4B, in response to a write command after the gang writer 4A issues a binary write command, the memory controller 2 stores data only in the lower page of the memory cell 13D. Note that in the first writing step, the memory cell 13D in which data is stored is referred to as a second memory cell. As shown in FIG. 4B, in the first writing step, that is, binary storage, data is written in the memory unit 13 in the order of Page 0, Page 2,. Note that a flag for writing binary values in the write command may be provided, and this command may be used as the first command.

  In the first writing step, binary storage is performed on the memory unit 13 capable of quaternary storage, so that the storage capacity of the memory unit 13 of the semiconductor memory device 3 is halved. For example, if the physical block size is 1 MByte, the four-value storage shown in FIG. 4A can store 1 MB of data in the memory unit 13, but the two-value storage shown in FIG. In value storage, only half of the data of 512 kbytes can be stored. That is, in binary storage, the capacity that can be stored in the memory unit 13 is reduced, but in general, data that should be stored in advance in the semiconductor memory device 3 at the time of shipment is the total capacity of the memory unit 13 of the semiconductor memory device 3. It is not a problem because it is small.

<Step S12> Mounting process (reflow process)
As shown in FIG. 5, the semiconductor memory device 3 in which binary data is stored in the second memory cell according to the first command is soldered to the surface of the printed wiring board 20 constituting the host 4.

  In the mounting process, first, a low melting point metal alloy such as solder paste or solder ball, that is, a bonding metal 23 is disposed between a predetermined pad of the printed wiring board 20 and an external connection pad of the semiconductor memory device 3. Is done. FIG. 5 shows an example in which other electronic components 21 </ b> A, 21 </ b> B, and 22 </ b> A to 22 </ b> D are mounted on the printed wiring board 20 in addition to the semiconductor memory device 3.

  The printed wiring board 20 on which various electronic components including the semiconductor memory device 3 are arranged is heated to a temperature at which the bonding metal 23 melts in a reflow furnace and then cooled. The reflow temperature is, for example, 220 ° C. to 260 ° C.

  Due to the reflow process, a part of the electrons injected into the floating gate of the memory cell 13D of the semiconductor memory device 3 is discharged from the floating gate by thermal energy. However, in the semiconductor memory device 3, only binary data is stored in the second memory cell in which data is stored. For this reason, even if some electrons are discharged from the floating gate of the memory cell 13D in the state 1, the difference from the state 0 in which no electrons are injected into the floating gate as shown in FIG. Errors are unlikely to occur during reading.

  In the printed wiring board 20 shown in FIG. 5, components are mounted on both surfaces. In this case, the placement of components on the surface of the wiring board and the reflow process are performed for each surface. That is, when the surface on which the semiconductor memory device 3 is mounted is the surface on which the reflow process is performed first, the semiconductor memory device 3 is subjected to two heat treatments. Note that the melting point of the bonding metal subjected to the first reflow treatment is higher than the melting point of the bonding metal subjected to the second reflow treatment.

<Step S13> Block erase (second command reception)
The printed wiring board 20 on which the semiconductor memory device 3 is mounted is housed in a housing together with other components, and a product host is completed. Here, the second memory cell 13D storing binary data can store four values in terms of structure. Therefore, in order to increase the memory area that can be used by the user in the semiconductor memory device 3, the CPU 11 stores the data stored binary in the second memory cell in accordance with the command from the host 4 in the first memory cell. Performs 4-level memory control. Here, the second command issued by the host 4 is a multi-value rewrite command.

  The CPU 11 that has received the multi-value rewrite command from the host 4 as the second host first erases an unused block, that is, an unused block if there is no block in which data can be stored. To create an empty block. When there is an empty block, it is not necessary to erase the block. For convenience of explanation, the first memory cell and the second memory cell are distinguished from each other, but both are memory cells having the same structure.

<Step S14> Multilevel rewrite process (second write process / erase process: rewrite process)
The CPU 11 of the semiconductor memory device 3 that has received the multi-level rewrite command performs a second write process of storing the binary stored data in the second memory cell into the first memory cell in the empty block in a four-value manner. Take control.

  Further, the CPU 11 erases the data stored in the second memory cell in order to enlarge the memory area that can be used by the user, that is, an erasing step of making the block to which the second memory cell belongs into an empty block. Take control. The user can store data in four values in the second memory cell in the empty block.

  As described above, the CPU 11 stores the data stored in the two second memory cells in one first memory cell, and performs the multi-value rewriting process of erasing the data in the second memory cell. Control.

  Here, FIG. 6 shows a state where data written only in the lower page of Block 0 and Block 1 is copied to the Lower Page / Upper Page of Block 2.

  The semiconductor memory device 3 according to the present embodiment is a semiconductor memory device in which predetermined data is stored in multiple values in a plurality of first memory cells. Before soldering, the second memory cell is in accordance with a first command. Data is written using a binary write function, and after the soldering process, data is written back to multiple values in accordance with the second command. This reduces the effect of stored data deterioration due to heat and improves data retention characteristics. can do.

  For this reason, the semiconductor memory device 3 of the present embodiment has a large storage capacity and high reliability. Further, the manufacturing method of the semiconductor memory device of this embodiment can manufacture a semiconductor memory device having a large storage capacity and high reliability.

<Second Embodiment>
The semiconductor memory device according to the second embodiment of the present invention will be described below with reference to the drawings. Since the semiconductor memory device 3A of the second embodiment is similar to the semiconductor memory device 3 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  As described above, before the reflow process, data is written only in the lower page and stored in the first memory cell of the semiconductor memory device 3A. However, the first memory cell has a structure capable of storing quaternary data.

  Therefore, the first memory cell can apply not only the write voltage Vp1 shown in FIG. 2B but also the write voltages Vp2 and Vp3 to the memory cell 13D. In the semiconductor memory device 3A of the present embodiment, the write voltage when writing binary data to the second memory cell is set to Vp4 that is higher than the write voltage Vp1 during normal binary write, and the data “0 Is stored in state 3. The write voltage Vp4 is, for example, the write voltage Vp3 when storing quaternary data. That is, when storing the binary data in the second memory cell in the first writing process, the CPU 11 which is the control unit of the semiconductor memory device 3A has a voltage higher than the writing voltage Vp1 during normal binary storage. A write voltage in the second write process is applied to the word line 13E.

  As shown in FIG. 7, in state 3, since more electrons are injected into the floating gate than in state 1, even if some electrons are discharged from the floating gate due to the thermal energy of the reflow process, The difference is remarkable. Note that the write voltage Vp4 may be the write voltage Vp2, and the state of the memory cell may be the state 2.

  The semiconductor memory device 3A of the present embodiment has the effect of the semiconductor memory device 3 of the first embodiment, and further has fewer errors after the reflow process than the semiconductor memory device 3, and has high reliability. . Further, since the semiconductor memory device 3A can be reflowed at a higher temperature than the semiconductor memory device 3 of the first embodiment, it can be bonded to the wiring board using a high melting point solder.

In the above description, a semiconductor memory device that stores binary data in a memory cell that can store four values has been described as an example, but four-value storage may be performed in a memory cell that can store eight values. In other words, 2 ^M (where M is a natural number less than N) value data is stored in a memory cell that can store 2 ^N value (where N is a natural number greater than or equal to 2), and rewritten to 2 ^N value storage after the reflow process. May be. The upper limit of N is not particularly determined, but is 5 or less due to restrictions on the manufacturing process of the memory cell.

  As described above, the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Memory system 2 ... Memory controller 3, 3A ... Semiconductor memory device 4 ... Host 10 ... ROM
11 ... CPU
13 ... Memory unit 13A ... Word line control unit 13D ... Memory cell 13E ... Word line 14 ... Host I / F
15 ... ECC
16 ... NAND I / F
17 ... Bus 18 ... RAM
20 ... Printed wiring board 21A ... Chip components 22A to 22D ... Chip component 23 ... Bonding metal

Claims (5)

A semiconductor memory device that is connectable to a host that issues a predetermined command and stores data in a semiconductor memory unit,
A plurality of first memory cells storing data of 2 ^N values (where N is a natural number of 2 or more);
A plurality of second memory cells storing data of 2 ^M values (where M is a natural number less than N);
Control for storing data in the plurality of second memory cells according to the first command, and 2 ^(N−M) second memories each storing 2 ^M- value data according to the second command And a control unit that performs control for storing data in each cell in each of the first memory cells and control for erasing data stored in the second memory cells. A semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein the control unit stores data in the second memory cell with a write voltage when storing in the first memory cell. 3. A method of manufacturing a semiconductor memory device that is connectable to a host that issues a predetermined command and stores data in a semiconductor memory unit having a plurality of memory cells,
The plurality of memory cells store a plurality of first memory cells storing data of 2 ^N values (where N is a natural number greater than or equal to 2) and data of 2 ^M values (where M is a natural number less than N). A plurality of second memory cells,
A first writing step of storing 2 ^M- value data in the second memory cell in accordance with a first command;
According to the second command, 2 ^(N−M) (where N is a natural number exceeding ^M) data of 2 ^M values in which 2 ^M- value data is stored are used as the data of the plurality of first memory cells. And a rewriting step of erasing data stored in the 2 ^(N−M) second memory cells in the first storage step. A method for manufacturing a semiconductor memory device.   4. The method of manufacturing a semiconductor memory device according to claim 3, further comprising a reflow step of soldering the semiconductor memory device to a wiring board between the first writing step and the rewriting step. .   5. The method of manufacturing a semiconductor memory device according to claim 3, wherein the data of the first writing step is stored at a writing voltage when data is stored in the rewriting step. 6.

Images