JP2010219947A - Driver device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver device with a built-in UVLO function. <P>SOLUTION: The driver device includes a first switch element connected to a power source, a second switch element connected serially to the first switch element, a third switch element, a fourth switch element connected in parallel with the third switch element, a first resistor connected to the third and fourth switch elements at one end and connected to the control electrode of the first switch element at the other end, a current mirror being a load of the third switch element through the first resistor, a discharge circuit for making a current flow to the current mirror, and a control circuit for receiving an input signal from the outside, executing control so as to alternately turn on and off the second switch element and the first switch element through the third switch element, also turning on the discharge circuit and the fourth switch element when the power source is turned on to make the current flow to the current mirror, and thus turning off the fourth switch element after the power source is turned on. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driver device, and more particularly to a driver device incorporating a UVLO function.

Driver devices that drive and control power transistors such as MOSFETs and IGBTs used in power electronics applications have a UVLO (Under Voltage Lock out) function that lowers the output terminal regardless of the input until the external power supply is stabilized. Some are provided (see, for example, Patent Document 1).
Some devices have a function of preventing erroneous switching on of the semiconductor switching element (see, for example, Patent Document 2).

JP 2005-318552 A JP 2004-112987 A

  The present invention provides a driver device incorporating a UVLO function.

  According to one aspect of the present invention, a first switch element connected to a power source, a second switch element connected in series with the first switch element, a third switch element, and the third switch element A fourth switch element connected in parallel with the switch element; one end connected to the third switch element and the fourth switch element; and the other end connected to a control electrode of the first switch element. 1 resistor, a current mirror serving as a load of the third switch element via the first resistor, a discharge circuit that is connected to the reference side of the current mirror and passes a current to the current mirror, and a control circuit And receiving an input signal from the outside, controlling the second switch element and the first switch element via the third switch element to alternately turn on and off, and Said discharge circuit And the fourth switch element is turned on when the power supply is turned on and the first switch element is turned off by passing a current through the current mirror. After the power supply is turned on, the fourth switch element is turned on. There is provided a driver device comprising a control circuit for turning off.

  According to the present invention, a driver device incorporating a UVLO function is provided.

It is a circuit diagram which illustrates the composition of the driver device concerning the embodiment of the invention. It is a circuit diagram of the driver device of a comparative example. It is a timing chart of the main signals of the driver device of a comparative example. 2 is a timing chart of main signals of the driver device illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a discharge circuit illustrated in FIG. 1. It is a circuit diagram which illustrates other composition of a discharge circuit. It is a circuit diagram which illustrates other composition of a discharge circuit. It is a circuit diagram which illustrates the composition of the driver device concerning other embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the present specification, the logical value low level is represented by “0” and the high level is represented by “1”.

(First embodiment)
FIG. 1 is a circuit diagram illustrating the configuration of a driver device according to an embodiment of the invention.
As shown in FIG. 1, the driver device 61 of this embodiment includes a first switch element M1, a second switch element M2, a third switch element M3, a fourth switch element M4, and a first resistor R1. , A current mirror 20, a discharge circuit 30 and a control circuit 10.
These are formed on the same semiconductor substrate to form a single chip, or formed on a plurality of chips and packaged as a single package body.

The first switch element M1 and the second switch element M2 are connected in series with each other, the first switch element M1 is connected to the power supply VCC, and the second switch element M2 is connected to the ground GND. A connection point between the first switch element M1 and the second switch element M2 is output to the outside as an output signal VO, and drives, for example, a power MOSFET and an IGBT.
Thus, the first and second switch elements M1 and M2 form a half bridge in which the first switch element M1 is the high side and the second switch element M2 is the low side.

The third switch element M3 and the fourth switch element M4 are connected in parallel, and one end drives the control electrode (wiring 56) of the first switch element M1 via the first resistor R1. The other end is connected to the ground GND.
The first resistor R1 is inserted for current limitation and protection.

  The second switch element M2 is controlled by the control circuit 10 via the wiring 58. The first switch element M1 is controlled by the control circuit 10 via the wiring 57, the third switch element M3, the first resistor R1, and the wiring 56 (control electrode).

The current mirror 20 includes transistors 20a and 20b.
The reference-side transistor 20a of the current mirror 20 is connected to the current source 21 by the wiring 55, and the mirror-side transistor 20b is connected to the third and fourth switch elements M3 and M4 via the first resistor R1. Yes. As described above, the current mirror 20 is a load of the third and fourth switch elements M3 and M4.

  The discharge circuit 30 is a circuit that allows current to flow from the wiring 54 to the ground GND. In addition, by controlling the potential of the wiring 53 or the wiring 52, a structure in which the current flowing from the wiring 54 to the ground GND can be controlled to be on or off can be used. In the present embodiment, the wiring 53 is connected to the power supply VCC via the second resistor R2. The wiring 53 is connected to the output of the negative (INV) circuit Iv 1, and the input terminal of the negative circuit Iv 1 is connected to the control circuit 10 by the wiring 52. Further, the wiring 54 is connected to the wiring 55, that is, the transistor 20 a on the reference side of the current mirror 20.

  Since the negative circuit Iv1 is not yet in an operating state when the power supply is turned on, the potential of the wiring 53 rises as the potential of the power supply VCC rises through the second resistor R2. For this reason, the discharge circuit 30 causes a current to flow from the reference side 20a of the current mirror 20 via the wiring 54 and the wiring 55 when the power supply is turned on.

  As a result, the charges accumulated in the transistors 20a and 20b constituting the current mirror 20 are discharged, and erroneous turn-on of the first switch element M1 is prevented. That is, the UVLO function is reliably realized. Details of the UVLO function will be described later.

  Further, after the power supply VCC rises and the potential is stabilized, the control circuit 10 changes the potential of the wiring 52 from “0” to “1”. The potential of the wiring 53 connected to the output terminal of the negative circuit Iv1 is “0”, and the fourth switch element M4 and the discharge circuit 30 are turned off. Thereafter, the normal operation state is obtained.

  In the normal operation state, the control circuit 10 receives the input signal VI from the outside and controls the second switch element M <b> 2 via the wiring 58. Further, the first switch element M1 is controlled by the wiring 57 via the third switch element M3. That is, the control circuit 10 receives the logical values “0” and “1” of the input signal VI and controls one of the first and second switch elements M1 and M2 to be on and the other to be off. Thereby, the output signal VO is electrically connected to the power supply VCC or the ground GND in accordance with the input signal VI, and for example, an externally connected MOSFET or IGBT can be driven.

  In this embodiment, the first to fourth switch elements M1 to M4 are n-type MOSFETs, and the current mirror 20 is a p-type MOSFET. However, the present invention is not limited to this, and may be a bipolar transistor. Further, a protective Zener diode may be connected to the control electrode (wiring 56) of the first switch element M1 and the connection point (output signal VO) of the first and second switch elements.

(Comparative example)
Here, before describing the UVLO function of the driver device 61 of the present embodiment in detail, the operation and problems of the driver device without the discharge circuit 30 will be described.
FIG. 2 is a circuit diagram of a driver device of a comparative example.
The driver device 161 of the comparative example shown in FIG. 2 is the same as the driver device 61 of the present embodiment except that the discharge circuit 30 is not provided.

That is, the driver device 161 of the comparative example operates in the same manner as the driver device 61 of the present embodiment after the power supply is turned on and the potential of the power supply VCC is stabilized.
Further, when the power is turned on, the fourth switch element M4 is turned on to keep the wiring 56 at a low potential and the first switch element M1 is turned off. Thereby, the UVLO function is realized.

  By the way, the elements inside the driver device 161 do not operate until the potential of the power supply VCC becomes 0 V until the power supply circuit inside the driver device 161 can operate. For example, the negative circuit Iv1, the current source 21, the current mirror 20, and the third switch element M3 are not operating.

For this reason, as described above, when the power supply rises, the potential of the wiring 53 increases with the potential of the power supply VCC via the second resistor R2, and the fourth switch element M4 is turned on.
Then, the wiring 56 is set to a low potential via the first resistor R1, and the first switch element M1 is turned off. Thereby, the UVLO function is realized.

However, when the fourth switch element M4 is turned on and the wiring 56 is set to a low potential, not only the first switch element M1 is turned off, but also the drain of the transistor 20b constituting the current mirror 20 is set to a low potential.
Here, since the current source 21 connected to the reference side of the current mirror 20 has not yet operated, the reference-side transistor 20a is off.

  Therefore, the transistor 20b is in a state where the potential of the power supply VCC is applied to the source and the low potential of the wiring 56 is applied to the drain. Incidentally, the transistor 20b has parasitic capacitances of a gate-source capacitance Cgs and a gate-drain capacitance Cgd. Therefore, a voltage Vgs obtained by dividing the difference voltage between the potential of the power supply VCC and the potential of the wiring 56 by the gate-source capacitance Cgs and the gate-drain capacitance Cgd is applied between the gate and source of the transistor 20b. Become.

Here, since the reference-side transistor 20a is off, there is no charge flowing out from the gate terminal of the transistor 20b. Therefore, the transistor 20b may be turned on by the gate-source voltage Vgs.
When the transistor 20b is turned on, the transistor 20b from the power supply VCC, a first resistor R1, a current _{I 2} flows to the ground GND via a fourth switch element M4.

Voltage R1 × I ₂ of the first resistor R1 caused by the current I _2, exceeds the threshold voltage of the first switching element M1, a first switching element M1 is turned on. At this time, the output signal VO becomes the potential of the power supply VCC, and the UVLO function cannot be realized.

FIG. 3 is a timing chart of main signals of the driver device of the comparative example.
In FIG. 3, the main signal of the driver device 161 of the comparative example, the potential of the power supply VCC, the current of the current source 21, the potential of the wiring 52, the potential of the wiring 53, the current of the wiring 55, the current of the first resistor R1 I ₂ , the potential of the wiring 56, and the output signal VO are schematically shown (FIGS. 1A to 1H).

As shown in FIG. 3A, when the power is turned on at time t = 0 and the potential of the power supply VCC rises from 0V, the potential of the power supply VCC rises until it becomes stable at time T4.
Further, as shown in FIG. 3B, the current I ₁ of the current source 21 is 0 until the current I ₁ of the current source 21 rises at time t = T3.

  Until the power supply circuit in the driver device 161 can operate, the elements in the driver device 161 are in the off state. Therefore, as shown in FIG. 3C, the potential of the wiring 52, which is the output of the control circuit 10, is controlled to "1" at a predetermined time T5 after the potential of the power supply VCC is stabilized at time t = T4. Until it is done, it is “0”.

  Similarly, the potential of the wiring 53 connected to the output terminal of the negation circuit Iv1 rises together with the potential of the power supply VCC by the second resistor R2 connected to the power supply VCC while the negation circuit is not operating. After the potential of the power supply VCC is stabilized, it becomes “0” at time T5.

Current on the reference side of the wiring 55 of the current mirror 20 is equal to the current _{I 1} of the current source 21, to the current source 21 is to operate at time t = T3, a 0 (Fig. 3 (e)).
As described above, the transistor 20a on the reference side of the current mirror 20 is off at time t <T3, and there is no charge flowing out from the gate terminal of the transistor 20b. Therefore, a voltage Vgs obtained by dividing the difference voltage between the potential of the power supply VCC and the potential of the wiring 56 by the gate-source capacitance Cgs and the gate-drain capacitance Cgd is applied between the gate and source of the transistor 20b.

This voltage Vgs, when transistor 20b is turned on at time t = T1, the current _{I 2} begins to flow through the first resistor R1 (FIG. 3 (f)). Current I ₂ flowing through the first resistor R1 is a current source 21 and current mirror 20 at time t = T3 will be able to operate, are limited to be equal to the current I ₁ of the current source 21.

Thus, at time t is T1 <t <T3, the voltage R1 × _{I 2} due to the current _{I 2} flowing through the first resistor R1, the potential of the wiring 56 is raised (FIG. 3 (g)). When the potential of the wiring 56 exceeds the threshold voltage Vth of the first switch element M1 (time t = T2), the output signal VO changes from 0 to the potential of the power supply VCC (FIG. 3 (h)).

When the current source 21 and the current mirror 20 start to operate at time t = T3, the current I ₂ flowing through the first resistor R1 becomes equal to the current I ₁ of the current source 21, and the potential of the wiring 56 becomes a normal value. Returning (FIG. 3 (g)), the output signal VO changes from the potential of the power supply VCC to 0 (FIG. 3 (h)).

Thus, in the driver device 161 of the comparative example, the UVLO function may malfunction when the power supply VCC starts up.
Next, the operation of the driver circuit 61 of this embodiment will be described.

FIG. 4 is a timing chart of main signals of the driver device shown in FIG.
In FIG. 4, the main signal of the driver device 61 of this embodiment, the potential of the power supply VCC, the current of the current source 21, the potential of the wiring 52, the potential of the wiring 53, the current of the wiring 55, the current of the wiring 54, The current I ₂ of the resistor R ₁ , the potential of the wiring 56, and the output signal VO are schematically shown (FIGS. (A) to (i)).

4A to 4D, the potential of the power supply VCC, the current of the current source 21, the potential of the wiring 52, and the potential of the wiring 53 are the same as those in FIGS. 3A to 3D. is there.
In the driver device 61 of the present embodiment, the discharge circuit 30, when the power VCC rises, a point passing a small current _{I 3} to the wiring 54 are different (Fig. 4 (f)).

Therefore, as shown in FIG. 4E, the current of the reference-side wiring 55 of the current mirror 20 is the same as that of the discharge circuit 30 during the time t = 0 to T3 when the current source 21 is not operating. A minute current I ₃ flows through 54.

Then, due to the current I ₃ flowing from the wiring 54 through the discharge circuit 30, a part of the charge disappears from the gate of the transistor 20 b via the wiring 55 and the current I ₂ flowing through the transistor 20 b is limited to I ₃ . That is, the current _{I 3} flowing through the discharge circuit 30 becomes a reference current of the current mirror 20, transistor 20b, a first resistor R1, so that the current _{I 2} flowing from the fourth switching element M4 to the ground GND is equal to _{I 3} (FIG. 4 (g)).

Here, the voltage R1 × _{I 3} generated in the first resistor R1 is so as not to exceed the threshold voltage Vth of the first switch element M1, sets the value or the current _{I 3} of the first resistor R1 (Fig. 4 ( h)). As a result, the output signal VO can be held at 0 when the power supply VCC rises, and the UVLO function can be reliably realized.

The operation after the current source 21 and the internal elements start operating at time t = T3 is the same as that of the driver device 161 of the comparative example.
In the driver device 61 of this embodiment, since the control circuit 10 controls the potential of the wiring 52 from “0” to “1” at time t = T5 after the potential of the power supply VCC is stabilized, The potential of the wiring 53 connected to the output terminal of the negative circuit Iv1 changes from “1” to “0”. As a result, the discharge circuit 30 is turned off, and the current I _{3 of the} wiring 54 becomes zero.

  As described above, according to the driver device 61 of the present embodiment, when the power is turned on, the current is caused to flow by the discharge circuit 30 to the reference side of the current mirror 20 serving as the load of the third switch element M3. It is possible to prevent the switch element M1 from being erroneously turned on and to reliably realize the UVLO function.

FIG. 5 is a circuit diagram illustrating the configuration of the discharge circuit shown in FIG.
As shown in FIG. 5, the discharge circuit 30a includes a fifth switch element M5 and a third resistor R3. In this specific example, the case where the fifth switch element is an n-type MOSFET is illustrated.
The source of the fifth switch element M5 (n-type MOSFET) is connected to the ground GND via the third resistor R3, and the drain and gate are connected to the wirings 54 and 53, respectively.

When the power supply rises, the wiring 53 rises with the potential of the power supply VCC, and turns on the fourth switch element M4 and the fifth switch element M5.
However, the source of the fifth switching device M5 for the third resistor R3 is inserted, the current I ₃ which sucks the wire 54 is limited to small current.

Further, after the power supply is turned on and the potential of the power supply VCC is stabilized, the wiring 53 is set to “0” by the control circuit 10 and the fifth switch element M5 is turned off. Therefore, the discharge circuit 30a is turned off, the current _{I 3} does not flow. Thus, the discharge circuit 30a, only realized reliably UVLO function by applying a current I ₃ to the wiring 54 at startup, normal operation the potential of the power supply VCC has stabilized is turned off.

The discharge circuit 30 illustrated in Figure 1, thus at startup may be Nagasere the current I ₃ to the wiring 54, other configurations, for example configurations by the current source are also possible.
FIG. 6 is a circuit diagram illustrating another configuration of the discharge circuit.
As shown in FIG. 6, the discharge circuit 30b includes a current source including transistors Q32 and Q33 and resistors R32 and R33.

  The bases of the transistors Q32 and Q33 are connected to each other, the emitter of the transistor Q33 is connected to the ground GND, and the emitter of the transistor Q32 is connected to the ground GND via the resistor R32. The collector of the transistor Q32 is connected to the wiring 54, and the collector of the transistor Q33 is connected to the power supply VCC via the resistor R33.

That is, the discharge circuit 30b of this specific example is a Wideler current source (Widler type current mirror).
Compared to discharge circuit 30a represented in the normal current mirror and 5, by using a Widlar current source 30b, it is possible to suppress the resistance R32 which is required to flow a small current I ₃ to a relatively small resistance value it can. That is, when the potential of the power supply VCC rises, the resistance R32, the current I ₃ will be limited to very small current.

In this specific example, the transistors Q32 and Q33 are illustrated as bipolar transistors. However, the transistors Q32 and Q33 may be constituted by MOSFETs.
Alternatively, the discharge circuit 30b may be turned off after the potential of the power supply VCC is stabilized.

FIG. 7 is a circuit diagram illustrating another configuration of the discharge circuit.
As shown in FIG. 7, the discharge circuit 30c of this specific example includes transistors Q32 to Q34 and a resistor R33.
The transistors Q32 and Q33 constitute a current mirror, and the reference-side transistor Q33 is connected to the power supply VCC via a resistor R33. The collector of the transistor Q32 is connected to the wiring 54. Thus, the transistors Q32, Q33, resistor R33 becomes a current source draws a current _{I 3} from the wiring 54.

The transistor Q34 is connected in parallel to the reference-side transistor Q33, the base is connected to the wiring 52, and is controlled by the control circuit 10.
When the power rises, the potential of the wiring 52 is a transistor Q34 for the "0" is off, the transistor Q32, Q33, resistor R33 becomes a current source draws a current _{I 3} from the wiring 54. Thereby, the UVLO function is reliably realized.

In addition, after the potential of the power supply VCC is stabilized, the potential of the wiring 52 is set to “1” by the control circuit 10, and the transistor Q34 is turned on. Thus, the transistors Q32, Q33, a current source including the resistor R33 is turned off, the wiring 54 is not sucked the current _{I 3.}

  In this specific example, the transistors Q32 to Q34 are illustrated as bipolar transistors. However, the transistors Q32 to Q34 may be constituted by MOSFETs. The transistors Q32 and Q33 and the resistor R33 can also be configured by other current sources, for example, the above-mentioned Wideler current source.

FIG. 8 is a circuit diagram illustrating the configuration of a driver device according to another embodiment of the invention.
As shown in FIG. 8, the driver device 62 of this embodiment further includes a photocoupler 40.
These are formed on the same semiconductor substrate to form one chip, or formed on a plurality of chips and packaged as one package body.

The photocoupler 40 receives an input signal VIN from outside and converts it into an optical signal, a photoelectric conversion element 42 that converts the optical signal back into an electrical signal, and an electrical signal of the photoelectric conversion element 42. Is supplied to the input signal VI of the control circuit 10.
The portion that receives the input signal VI and outputs the output signal VO is the same as that of the driver device 61 described above.

The driver device 62 outputs an output signal VO controlled by an input signal VIN input to the photocoupler 40 from the outside. For example, a power MOSFET and an IGBT can be driven by the output signal VO.
Thus, according to the driver device 62 of the present embodiment, it is possible to provide a driver device that reliably realizes the UVLO function controlled by the isolated input of the photocoupler 40.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the driver device, as long as a person skilled in the art can implement the present invention in a similar manner by appropriately selecting from a known range and obtain the same effect, Included in the range.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all driver devices that can be implemented by those skilled in the art based on the driver device described above as an embodiment of the present invention are also included in the scope of the present invention as long as they include the gist of the present invention. In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

DESCRIPTION OF SYMBOLS 10 Control circuit 20 Current mirror 20a, 20b Transistor 21 Current source 30, 30a, 30b, 30c Discharge circuit 40 Photocoupler 41 Electro-optical conversion element 42 Photo-electric conversion element 43 Amplifier circuit 52-58 Wiring 61, 62, 161 Driver apparatus GND Ground Iv1 Negating circuit M1 1st switch element M2 2nd switch element M3 3rd switch element M4 4th switch element M5 5th switch element Q32, Q33, Q34 Transistor R1 1st resistance R2 2nd resistance R3 Third resistor R32, R33 Resistor VCC Power supply VI, VIN Input signal VO Output signal

Claims (5)

A first switch element connected to a power source;
A second switch element connected in series with the first switch element;
A third switch element;
A fourth switch element connected in parallel with the third switch element;
A first resistor having one end connected to the third switch element and the fourth switch element and the other end connected to a control electrode of the first switch element;
A current mirror serving as a load of the third switch element via the first resistor;
A discharge circuit that is connected to a reference side of the current mirror and causes a current to flow through the current mirror;
A control circuit,
Receiving an input signal from the outside, and controlling the second switch element and the first switch element via the third switch element to alternately turn on and off;
The discharge circuit and the fourth switch element are turned on when the power supply is turned on, and the first switch element is turned off by passing a current through the current mirror. After the power supply is turned on, the first switch element is turned on. A control circuit for turning off the switching element of 4;
A driver device comprising: The discharge circuit is:
A fifth switch element;
A second resistor that senses the potential of the power supply and controls the fifth switch element;
A third resistor connected in series to the fifth switch element to limit the current;
The driver device according to claim 1, further comprising:   The driver device according to claim 1, wherein the discharge circuit includes a current source circuit.   The driver device according to claim 1, wherein the control circuit turns off the discharge circuit after the power supply is turned on.   5. The photocoupler according to claim 1, further comprising a photocoupler that converts the input signal into an optical signal, converts the optical signal into an electrical signal again, and outputs the electrical signal to the control circuit. Driver device.

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