JP2010219426A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which a large amount of distortion can be generated. <P>SOLUTION: A manufacturing method of the semiconductor device comprises a process (S3) of forming an SiGeC layer containing C and Ge of 10 times or more the concentration of the C, and a process (S4) of lowering a proportion of the C located on a lattice substitution position among all C in the SiGeC layer, from a proportion at the time when the device has been formed to lower the proportion to 50% or smaller by moving C located on the lattice substitution position among the C in the SiGeC layer to an inter-lattice position. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a strained silicon region and a manufacturing method thereof.

  One of the most promising structures for future LSI (large scale integrated circuits) technology is a method of imparting strain to Si by using SiGe having a lattice constant different from that of Si. Specifically, for example, compressive strain is applied to a channel region made of Si by using SiGe for a source / drain region of a p-type MOSFET (metal oxide semiconductor field effect transistor).

  When this technique is used, the higher the amount of strain due to the SiGe region, the higher the performance of the MOSFET. The higher the Ge concentration in the SiGe region, the greater the amount of strain that the SiGe region imparts to the Si region, so a higher Ge concentration is desirable. However, when the Ge concentration is high, defects such as dislocations occur in the SiGe region during the deposition of SiGe that requires high temperature processing. As a result, the originally intended increase in strain cannot be realized by increasing the Ge concentration. Specifically, when the Ge concentration is higher than about 20%, such dislocations are particularly likely to occur.

  As a method for solving this problem, for example, it is conceivable to lower the processing temperature when forming the SiGe layer. By doing so, dislocations hardly occur during the growth of the SiGe layer. However, if the processing temperature during film formation is lowered by 50 ° C., the growth rate of the SiGe layer is reduced by about an order of magnitude, so this method is not practical.

  Patent Document 1 proposes a method of alternately supplying SiGe and SiC in order to form high-quality SiGeC when C and Ge are simultaneously added during the epitaxial growth of Si.

  Patent Document 2 describes an invention relating to an epitaxial layer containing C and Ge in Si.

JP 2002-289526 A Special table 2007-537601 gazette

A. Madan et al, ECS Transactions 16 (10), 2008, p. 325 to 332

  The present invention seeks to provide a semiconductor device capable of generating a large amount of distortion and a method for manufacturing the same.

  According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes a step of forming a SiGeC layer containing C and Ge having a concentration of 10 times or more of C, and a lattice substitution position of C in the SiGeC layer. The ratio of C located at the lattice substitution position to all the C in the SiGeC layer is decreased from the ratio at the time of formation to 50% or less by moving the present to the interstitial position. And a process.

  A semiconductor device according to one embodiment of the present invention includes a substrate made of Si, a gate electrode provided over the substrate with a gate insulating film interposed therebetween, and a region sandwiching a channel region below the gate electrode on the surface of the substrate The ratio of C located at the lattice substitution position for all C is 50% or less including C and Ge having a concentration of 10% or more and 20% or more of the C concentration. A SiGeC layer and a source / drain region formed in the SiGeC layer are provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can generate | occur | produce a big distortion amount, and its manufacturing method can be provided.

Sectional drawing which shows a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process following FIG. 6 is a flowchart of a manufacturing process of the semiconductor device according to the embodiment. The figure which shows the comparison with the ON current of MOSFET which concerns on embodiment of this invention, and the ON current of reference MOSFET. The figure which shows SiGeC which C is located in a lattice substitution position. The figure which shows SiGeC which C is located in the position between lattices. It shows to the flow rate ratio of SiH ₃ CH ₃ and SiH _4, the relationship between C concentration of all the C concentration and lattice substitution positions within the SiC layer. The figure which shows the relationship between the lattice substitution position C density | concentration immediately after film-forming, and the distortion amount after film-forming. The figure which shows the relationship between heat processing temperature and lattice substitution position C concentration ratio. The figure which shows the relationship between lattice substitution position C density | concentration ratio and on-current.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3 are cross-sectional views sequentially illustrating a part of the manufacturing process of the semiconductor device according to the embodiment. FIG. 4 is a flowchart of the manufacturing process of the semiconductor device according to the embodiment.

  First, the structure shown in FIG. 1 is formed using a known process (step S1). That is, for example, a trench for an element isolation insulating film is formed on the surface of the substrate 1 made of Si by using a lithography process and etching such as RIE (reactive ion etching). Next, the element isolation insulating film 2 is formed by filling the trench with an insulating film such as a silicon oxide film. The element isolation insulating film 2 defines an element region. Next, an impurity is implanted into a portion of the element region where the formation of the MOSFET channel region 3 is scheduled for controlling the threshold value of the MOSFET. Next, a gate insulating film 4 is formed on this implantation region. Next, a gate electrode 5 is formed on the gate insulating film 4. Next, by implanting ions using the gate electrode 5 as a mask, extension regions 6 of source / drain regions are formed on both sides of the gate electrode 4 on the surface of the substrate 1. Next, a sidewall insulating film 7 that covers the sidewalls of the gate insulating film 4 and the gate electrode 5 is formed. Next, by etching (regardless of dry etching or wet etching), the formation planned region of the source / drain region on the surface of the substrate 1 is removed, and the etching region 11 is formed (step S2). That is, the substrate surfaces on both sides of the gate electrode 5 are removed by this etching. The depth of the etching region 11 is sufficient to obtain an effect of increasing the on-current of the MOSFET by applying strain to the channel region 3 of the MOSFET in the SiGe film embedded in the etching region in a later step. Specifically, the etching is performed at least deeper than the channel region.

  Next, as shown in FIG. 2, a SiGeC layer 12 having a thickness of, for example, 100 nm is selectively epitaxially grown in the etching region 11 (step S3). For example, the selective growth of the SiGeC layer 12 was performed at 600 ° C. using H 2, GeH 4, SiH 4, GeH 4, SiCH 6, and HCl. Although the content ratio of C and Ge in the SiGeC layer 12 will be described in detail later, as an example, it is assumed that C is 1% and Ge is 30% in terms of element density ratio. In addition, throughout this specification, what is indicated by “%” is the ratio of the number of atoms of each element to the total number of atoms (that is, at%), not the mass ratio. The reason for adding C is that Ge having a lattice constant of 0.5658 nm increases the lattice constant of Si crystal having a lattice constant of 0.5431 nm, while C having a lattice constant of 0.365 nm. Is expecting the effect of reducing the lattice constant for Si crystals.

  Next, as shown in FIG. 3, source / drain regions 13 are formed in the SiGeC layer 12 by lithography and ion implantation to complete a p-type MOSFET. The MOSFET according to the embodiment undergoes a heat treatment process for diffusing implanted ions for the source / drain regions. Or (and) it passes through the further heat processing process after that (step S4).

  In order to confirm the effect of the MOSFET according to the present embodiment, the MOSFET according to the present embodiment created in accordance with the above description was compared with the first reference MOSFET. Instead of the SiGeC layer of the MOSFET of the embodiment, the first reference MOSFET has the same thickness and does not contain C and has a Ge concentration of 20%. The on-currents of these MOFETs were compared. The result is shown in FIG. As shown in FIG. 5, it was confirmed that the on-current of the MOSFET of the embodiment was 30% higher than the on-current of the first reference MOSFET for the same off-current.

  Further, the MOSFET of the embodiment was compared with the second reference MOSFET. Instead of the SiGeC layer of the MOSFET of the embodiment, the second reference MOSFET has the same thickness, does not contain C, and has a Ge concentration of 30%. FIG. 5 shows a result of comparison between the on-current of the MOSFET of the embodiment and the on-current of the second reference MOSFET. As shown in FIG. 5, it was confirmed that the on-current of the second reference MOSFET was 10% lower than the on-current of the first reference MOSFET for the same off-current.

  From the above comparison, when SiGe containing 30% Ge without containing C is used for the source / drain regions, the on-current is rather than using SiGe containing 20% Ge with a Ge concentration of SiGe not containing C. As can be seen, the performance deteriorates. On the other hand, even if the Ge concentration is 30%, if SiGeC containing 1% C is used, it is possible to improve the characteristics of the MOSFET that cannot be realized only by increasing the Ge concentration.

  It is considered that the difference in the characteristics of these MOSFETs is caused by the difference in strain applied to the channel region by the SiGeC layer of the embodiment and the SiGe layers of the first and second references. Thus, the amount of distortion in the channel region of the embodiment and the first and second reference MOSFETs was measured by NBD (nano beam diffraction stain). Then, although both the MOSFET of the embodiment and the second reference MOSFET have the same Ge concentration of 30%, the MOSFET of the embodiment having the C concentration of 1% has a distortion amount related to the channel of the second reference MOSFET. It was confirmed that it was higher than the MOSFET.

  This result is interpreted as follows. First, if the Ge concentration is 20%, the amount of strain is not very large. Therefore, dislocation does not occur during the deposition of SiGe or in the heat treatment after the deposition. For this reason, distortion can be applied to the channel region by the inherent function of SiGe, and the characteristics of the MOSFET can be improved. However, when the Ge concentration is further increased, for example, 30%, the strain amount of SiGe is reduced due to defects during film formation, and as a result, the strain applied to the channel is higher than when the Ge concentration is 20%. The amount becomes smaller. As the amount of strain decreases, the pMOSFET characteristics do not reach the Ge concentration of 20%.

  On the other hand, when the Ge concentration is set to 30% as in the present embodiment, the addition of C at a concentration of 1% suppresses the occurrence of dislocation during film formation. This is because, as shown in FIG. 6, when C is positioned at the lattice substitution position, C reduces the strain amount of SiC (C has an effect of reducing the strain amount with respect to Si). More specifically, the amount by which C at a concentration of 1% decreases the amount of strain of SiC roughly matches the amount by which the amount of strain of SiGe at a concentration of 10% is increased (Ge has an effect of increasing the amount of strain with respect to Si). For this reason, even when the Ge concentration is 30%, the amount of strain in the SiGeC layer is almost the same as when the Ge concentration is 20%. In FIG. 6, a Si layer is drawn under the SiGeC layer for comparison.

  However, as described above, although the amount of strain in the SiGeC layer was small at the time of film formation, the completed MOSFET of this embodiment has better characteristics than the first reference MOSFET (Ge concentration 20%). Have. The reason for this is considered to be that C, which was present at the lattice substitution position at the time of film formation, moved to the interstitial position as shown in FIG. 7 by the heat treatment after the formation of the SiGeC layer. In FIG. 7, for comparison, a Si layer is drawn under the SiGeC layer.

  In order to confirm the above interpretation, the amount of strain in the SiGeC layer (Ge concentration 30%, C concentration 1%) of this embodiment was actually measured. As a result, the strain amount was the same as that of the sample having the Ge concentration of 20% (first reference) immediately after the film formation, but after the heat treatment, the sample having the Ge concentration of 27% was obtained. It was almost the same. In other words, C exhibits a strain reduction effect on Si by being in a lattice substitution position when forming a SiGeC film, and does not activate this strain reduction effect by moving to an interstitial position after heat treatment. As a result, the effect of increasing the amount of strain of Ge is partially offset by C during the film formation, and after the heat treatment, the suppressing effect by C is deactivated to restore its original size. In the case shown in the above embodiment, since the strain amount corresponds to the Ge concentration of 20% immediately after the film formation, almost all of C having the total concentration of 1% is in the lattice substitution position, and as a result, the strain is reduced. It is considered that the amount was reduced by an amount corresponding to a Ge concentration of 10%. On the other hand, after the heat treatment, the strain amount corresponds to the Ge concentration of 27%, so that 0.3% (= (30−27) / 10)% C is in the lattice substitution position. Yes. That is, for a C having a total C concentration of 1%, a C having a concentration corresponding to 30% is present at the lattice replacement position.

Thus, when forming the SiGeC layer, it is desirable that the concentration of C at the lattice substitution position is high so that the effect of increasing the amount of strain of Ge can be suppressed. Next, conditions for growing a SiGeC layer having a high C concentration at the lattice substitution position will be described with reference to FIG. FIG. 8 shows the relationship between the flow rate ratio of SiH ₃ CH ₃ and SiH ₄ , which are Si source gases, to all the C concentrations in the SiC layer and the C concentration at the lattice substitution position based on the measurement results. . The C concentration at the lattice substitution position is shown at a typical processing temperature in the range of 550 ° C. to 600 ° C. As shown in FIG. 8, when the temperature during film formation is 550 ° C., almost all C is located at the lattice substitution position. On the other hand, when the film formation temperature is 650 ° C. or higher, the C concentration at the lattice substitution position has already decreased in the state of film formation. Therefore, in order to create a C concentration state at a high lattice substitution position during film formation, which is to be realized in this embodiment, it is desirable that the temperature during film formation is low. In particular, in order to obtain a lattice substitution position C concentration of about 80% with respect to the total C concentration, the temperature during film formation is desirably 650 ° C. or lower. In FIG. 8, Ge is not contained in the film forming gas, but the same result was obtained when the same measurement was performed when Ge was changed in the range of 0 to 50%. The reason for aiming to obtain a lattice substitution position C concentration of about 80% of the total C concentration is based on FIG. FIG. 9 is a diagram showing the relationship between the ratio of C indicating the lattice replacement position immediately after film formation and the amount of strain immediately after film formation. Here, the Ge concentration is 30%, the C concentration is 1%, the broken line is the calculated value (theoretical value), and the strain amount is the Ge concentration converted value when all Ge occupies the lattice substitution positions. . As shown in FIG. 9, the measured value and the theoretical value do not match. This is because when the lattice substitution position C concentration is lowered, the effect of reducing the strain amount due to C is reduced, and consequently the effect of canceling the strain amount due to C with respect to Ge is reduced, and the above-described “Ge concentration (without addition of C) This is because, if it is 30%, the phenomenon that the amount of strain of SiGe decreases due to defects during film formation occurs. For this reason, if the density of the lattice substitution position C immediately after film formation is too low, a sufficient amount of distortion reduction effect due to C cannot be obtained, and a distortion amount such as a calculated value cannot be obtained as the density of the lattice substitution position C decreases. Therefore, a lattice replacement position C concentration of 80% or more where the calculated value and the measured value overlap is desired.

  On the other hand, it is necessary to move C located at the lattice replacement position at the time of film formation to an interstitial position in order to inactivate the distortion reduction effect. The heat treatment step in which C is deactivated when the MOSFET is actually manufactured according to the present embodiment is a relatively high temperature step among the heat treatment steps performed after the formation of the SiGeC layer until the completion of the MOSFET. It is expected that Therefore, paying attention to spike annealing at 1050 ° C., which was the highest temperature of heat treatment when the MOSFET was actually manufactured, the amount of strain after spike annealing in the range of 850 ° C. to 1100 ° C. was measured. Using this result, assuming that all 30% concentration Ge in the SiGeC layer occupies the lattice substitution position, the ratio of C occupying the lattice substitution position among the C contained after the spike annealing was calculated. The result is shown in FIG. Here, the spike annealing has a holding time at the maximum temperature of 1 second or less. What can be said from the results shown in FIG. 10 is that the ratio of C occupying the lattice substitution position by performing heat treatment at 1000 ° C. or higher is 50% or less. Therefore, according to the prediction using the heat treatment temperature, when the ratio of C occupying the lattice substitution position is 50% or less, the inactive effect of the C strain reduction effect as shown in FIG. 5 is obtained. Conceivable. Actually, when the characteristics of the MOSFET were measured, good characteristics were exhibited when the proportion of C occupying the lattice substitution position was 50% or less. That is, as shown in FIG. 11, the on-state current of the completed MOSFET increases rapidly at 50% of the ratio of C occupying the lattice substitution position. FIG. 11 is a diagram showing the relationship between the lattice substitution position C concentration ratio and the on-current based on SiGeC containing 1% C and 30% Ge. From the above, it can be seen that the proportion of C occupying the effective lattice substitution position, which is required to inactivate the C strain reduction effect, is desirably 50% or less of the concentration of contained C.

  FIG. 10 also shows a result of a rapid thermal process (RTP) and thermal annealing as a heat treatment method other than spike annealing. Here, in RTP, the holding time at the maximum temperature was 30 seconds, and in thermal annealing, the holding time at the maximum temperature was 30 minutes. In the temperature range from 850 ° C. to 1100 ° C. in which the experiment was performed, the substitution position C concentration was lower than that before the heat treatment in any heat treatment, and the effect intended by the present embodiment is not limited to spike annealing, but in various heat treatments. It turns out that it is obtained.

  In this embodiment, as an example, the Ge concentration is 30% and the C concentration is 1%. However, the present embodiment is not limited to this. In the present embodiment, a desired amount of the effect of increasing the amount of strain with respect to Si by Ge can be obtained in the completed MOSFET, and the purpose is to suppress the effect of increasing the amount of strain of Ge during film formation. From this viewpoint, if the C concentration is too low, the effect of suppressing the amount of Ge strain cannot be obtained. As described above, since the magnitude of the strain substantially corresponds to the Ge concentration of 10% and the C concentration of 1%, the Ge concentration is 10 times or more of the C concentration (the C concentration is 1 / G of the Ge concentration). 10 or less) is a condition required in the present embodiment. As a specific example, although the C concentration is 1% in the above example with respect to the Ge concentration of 30%, it can be 2% or 3% which is 1/10 or less of the Ge concentration. Further, under the condition that the C concentration is 1/10 or less of the Ge concentration, the value of Ge is set so that the amount of strain of Ge after the suppression of the effect of increasing the amount of strain of Ge by C is released becomes a desired value. Is selected. In the above example, the Ge concentration was 30%, but the Ge concentration may be any value as long as it is in the range of 20% or more and less than 100%.

The C concentration is an atomic number density in Si of at least 0.2% (1E20 cm ⁻³ ), and preferably 0.5% (2.5E20 cm ⁻³ ).

  In the example of the embodiment, a SiGeC layer is formed. However, it may contain B. Since B acts as a p-type dopant in the material of the source / drain layer of the pMOSFET, the parasitic resistance of the MOSFET can be reduced when the concentration is increased. However, since B is an element having a smaller covalent bond radius than Si as in C, it has an effect of reducing the strain amount with respect to Si as in C. Therefore, for example, the B concentration greatly affects the distortion during film formation. However, unlike C, B does not move one-way from the lattice replacement position to the interstitial position in the heat treatment step after film formation. For this reason, the addition of B cannot be controlled so as to suppress the effect of reducing the amount of distortion at the time when the MOSFET is completed, as realized by C.

  Note that Patent Document 2 describes that carbon is moved from one position in the crystal lattice to another position by performing an annealing process after the formation of the SiGeC film. However, the description in Patent Document 2 is different from the present embodiment as described below. First, Patent Document 2, particularly paragraph [0028], describes that C mixed in the SiC layer and the SiGeC layer is generally located at an interstitial position of the crystal lattice immediately after the SiC layer is deposited. . In paragraph [0028], the content of C at the interstitial position is about 10% or less, preferably less than about 5%, more preferably in the range of about 1% to about 3%, for example, about 2%. It is described that it may be annealed so that a part of C is mixed into the lattice substitution position. That is, in Patent Document 2, immediately after the film formation, most of the C in the SiC layer and the SiGeC layer is located at the interstitial position, and some of them may be moved to the lattice substitution position by subsequent heat treatment. It is described that it is good. Therefore, this embodiment is different from the present embodiment in which C located at the lattice replacement position is moved to the inter-lattice position by heat treatment.

  Further, not only the direction of movement of C is opposite between Patent Document 2 and the present embodiment, but also Patent Document 2 describes an annealing condition for moving a part of contained C to a lattice substitution position. Is not listed. On the other hand, in this embodiment, as shown in FIG. 5 and the like, immediately after the growth, carbon occupies the interstitial position and the lattice substitution position, and as long as the annealing temperature is at least 1100 ° C., the C concentration at the lattice substitution position may decrease. It is shown.

  Furthermore, in this embodiment, as in Patent Document 2, annealing is not performed so that a part of C is mixed into the substitution position of the crystal lattice. Note that Patent Document 2 describes that this annealing includes spike annealing such as high-speed heating process, laser annealing, or thermal annealing. However, the phenomenon of moving a part of carbon to the substitution position of the crystal lattice is, as described in Non-Patent Document 1, when SiC is heat-treated at a temperature close to the melting point of Si, that is, Only when using laser annealing. On the other hand, in the present embodiment, it is confirmed by experiments that various heat treatment steps can be used as well as laser annealing, as shown in FIG.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the SiGeC layer containing C positioned at the lattice substitution position is grown at 10% or less of the Ge concentration at the time of film formation. Later, C is moved to the interstitial position by heat treatment. By doing so, at the time of film formation, the effect of increasing the amount of strain of Ge is suppressed by C at the lattice substitution position, and then the effect of increasing the amount of strain of Ge is manifested by C moved to the interstitial position. That is, it is possible to form a SiGeC layer containing a high concentration of Ge, which cannot be realized only by increasing the Ge concentration. For this reason, at the time of film formation, the SiGeC layer can be grown without causing defects such as dislocation, and in a completed semiconductor device, a large strain can be applied to the adjacent Si layer by SiGeC containing a high concentration of Ge.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the above embodiments, the problems described in the column of the problem to be solved by the invention can be solved, and are described in the column of the effect of the invention. If the effect is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Element isolation insulating film, 3 ... Channel region, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Extension region, 7 ... Side wall insulating film, 11 ... Etching region, 12 ... SiGeC layer, 13 ... Source / drain region.

Claims (5)

Forming a SiGeC layer containing C and Ge having a concentration of 10 times or more of C;
By moving the C located in the lattice substitution position among the C in the SiGeC layer to the interstitial position, the ratio of C located in the lattice substitution position with respect to all the C in the SiGeC layer was formed. A step of reducing from the ratio at the time to 50% or less,
A method for manufacturing a semiconductor device, comprising: Before the step of forming the SiGeC layer, a step of forming a gate insulating film on a substrate made of Si, a step of forming a gate electrode on the gate insulating film, and the gate electrode of the surface of the substrate And a step of removing a portion adjacent to and forming a removal portion,
Forming the SiGeC layer comprises forming the SiGeC layer on the removal portion;
Forming a source / drain region in the SiGeC layer;
The method of manufacturing a semiconductor device according to claim 1.   The step of reducing the ratio of C located at lattice substitution positions to all C in the SiGeC layer from the ratio at the time of formation to 50% or less, heating the SiGeC layer at 1000 ° C. or more. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of:   The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the SiGeC layer is performed under a condition of 650 ° C. or lower. A substrate made of Si;
A gate electrode provided on the substrate via a gate insulating film;
Provided in a region where a region sandwiching a channel region below the gate electrode on the surface of the substrate is removed, and includes C and Ge having a concentration of 10% or more and a concentration of 20% or more of C. A SiGeC layer in which the ratio of C located at the lattice substitution position is 50% or less;
Source / drain regions formed in the SiGeC layer;
A semiconductor device comprising:

Images