JP2010217151A - Angle detector and angle detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an angle detector that has high accuracy and high reliability, and is easily miniaturized. <P>SOLUTION: A relative rotation angle with respect to the magnetic field of a Hall element is determined using a vector expressed by outputs from at least one pair of Hall elements 11 and 12 arranged mutually orthogonally. Drive directions of the Hall elements 11 and 12 are changed at predefined frequencies and two pairs of outputs of the Hall elements 11 and 12 are changed and fetched at the predefined frequencies by a switching means. Also, signs of fetched signals are inverted at the predefined frequencies and a pair of Hall element output signals are acquired. The acquired signals are ΔΣ-modulated by ΔΣ modulators 50 and 60, and angle data are fetched from which various offsets are removed from the ΔΣ-modulated signals through a phase synchronizing circuit 200. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an angle detection device that receives output signals from at least two Hall elements arranged in directions orthogonal to each other and outputs a value corresponding to a rotational angular displacement from a reference position in a magnetic field.

  A resolver has been conventionally used as a device for measuring the rotation angle of a rotating shaft of a motor or a rotating body in a servo mechanism. As is well known, a resolver has a rotor coil and a stator coil, and when an excitation current is passed through the stator coil, the voltage induced in the rotor coil according to the relative rotation angle between the two coils is RD (resolver digital). The digital signal of the rotation angle is obtained by converting the signal with the conversion IC.

Since the resolver improves the electromagnetic induction effect by increasing the number of windings of the rotor coil and the stator coil, the resolution of the rotation angle is high. A resolver generally has a structure in which a coil is housed in a solid housing and has excellent environmental resistance that can be used even in a high temperature environment.
However, it is difficult to reduce the cost of the resolver because it is necessary to wind the coil precisely during the manufacturing process. Also, the need to increase the number of windings of the rotor coil and the stator coil reduces the size and space. This is disadvantageous in terms of cost reduction.

In addition, the resolver requires wiring for connecting the coil and the above-described RD conversion IC, and there is a possibility that this wiring is disconnected. For this reason, a technique for detecting disconnection of the wiring between the resolver coil and the RD conversion IC has also been proposed (see, for example, Patent Document 1).
On the other hand, RD conversion ICs generally require many external parts such as resistors and capacitors (see Non-Patent Document 1, for example).

On the other hand, some non-contact rotation angle detection devices that do not use a resolver detect the rotation angle using a magnetic sensor such as a magnet and a Hall element. In this method, two magnetic sensors are arranged in a direction perpendicular to each other in a magnetic field generated by the magnet, and the rotation angle of the magnet is obtained based on the Hall element output signals obtained from the two magnetic sensors.
The rotation angle detection device that uses a magnet and a Hall element to detect the rotation angle is smaller, saves space, and costs less than a rotation angle detection device that uses a resolver and a non-contact rotation angle sensor. It has the advantage that it can be realized and is easy to assemble and mount.

However, the Hall element output signal has an offset due to manufacturing variations, and there is also an offset in the analog circuit portion in the non-contact rotation angle detection IC. Therefore, the offset of the Hall element output signal and the offset in the analog circuit section cause an error in the detected angle value as the output signal.
Of the various offsets included in the angle detection signal as described above, a technique for removing the offset of the Hall element output signal is often used. This is because the detection output of the two Hall elements is modulated with a clock signal and taken out as a two-phase signal whose phase is inverted, and when the modulated signal is demodulated, the offset component becomes relatively high-frequency side. Therefore, the offset component is removed with a low-pass filter (see, for example, Non-Patent Document 2).

JP 2000-131096 A

Analog Devices RD Converter IC AD2S83 Datasheet (ANALOG DEVICES Variable Resolution Resolver-to-Digital Converter AD2S83) Published by R S Popovic, Hall Effect Devices (ISBN-10: 0750300965 Inst of Physics Pub Inc (1991/05)

However, with the method described in Non-Patent Document 2 as described above, the offset of the entire analog circuit in the non-contact rotation angle detection IC cannot be removed, and an error occurs in the angle detection output. Therefore, in order to achieve high accuracy and miniaturization of the angle at the same time, a method for efficiently removing the offset of the Hall element output signal and the offset of the entire analog circuit without increasing the circuit scale is an issue. .
The present invention has been made in view of the above-described conventional technical problems, and efficiently removes not only the offset of the Hall element output signal but also the offset of the entire analog circuit without increasing the circuit scale. An object of the present invention is to provide an angle detection device that is accurate, reliable, and easy to downsize.

In order to solve the above-described problems, the angle detection device of the present invention has the following configuration.
(1) An angle detection device that inputs output signals from at least one pair of Hall elements arranged in directions orthogonal to each other and outputs a value corresponding to a rotational angular displacement from a reference position in a magnetic field,
In synchronization with the clock signal, the first switch circuit unit that alternately switches the drive current terminal and the output terminal of the Hall element to connect to the subsequent stage and switches the direction of the drive current of the Hall element;
A second switch circuit unit that switches a sign of an output signal of the Hall element output from the first switch circuit unit in synchronization with the clock signal;
A ΔΣ modulator that ΔΣ modulates an output signal from the second switch circuit unit;
A storage unit storing sine and cosine corresponding to a plurality of angles;
An angle signal obtained by time integration after removing a high frequency component from a signal based on an output signal of the ΔΣ modulation unit and a predetermined sine and cosine output from the storage unit by a loop filter having a low-pass characteristic. An angle detection loop unit to be supplied to the previous storage unit;
An angle detection device comprising:

  In the angle detection apparatus of (1), output signals from at least one pair of Hall elements arranged in directions orthogonal to each other are input, and a value corresponding to the rotational angular displacement from the reference position in the magnetic field is output. In this case, the rotation angle of the hall element from the reference position in the magnetic field is a relative angle with respect to the direction of the magnetic field (magnetic flux). It can take the form of rotational displacement.

The first switch circuit unit alternately switches the drive current terminal and the output terminal of the Hall element in synchronization with the clock signal to connect to the rear stage side and switch the direction of the drive current of the Hall element.
The second switch circuit unit switches the sign of the output signal of the Hall element output from the first switch circuit unit in synchronization with the clock signal.

Further, the ΔΣ modulation unit ΔΣ modulates the output signal from the second switch circuit unit.
On the other hand, the storage unit stores and holds sine and cosine values corresponding to a plurality of angles.
Further, after the angle detection loop unit removes high frequency components from the signal based on the output signal of the ΔΣ modulation unit and the predetermined sine and cosine output from the storage unit by a loop filter having a low-pass characteristic. An angle signal obtained by time integration is supplied to the previous storage unit.
As the clock signal, a chopper clock signal as will be described later with reference to FIG. 5 can be applied.

The Hall element, ΔΣ modulator, and switch circuit synchronized with the chopper clock signal modulate the offset of the Hall electromotive force signal and the offset of the entire analog circuit in the non-contact rotation angle detection IC to the frequency of the chopper clock signal. The modulated offset can be efficiently removed without providing a new circuit for removing the offset by the loop filter incorporated in the phase locked loop circuit.
At the same time, since the signal input to the ΔΣ modulator is a signal modulated by the chopper clock signal, generation of pattern noise from the ΔΣ modulator can be suppressed.

Furthermore, the noise-shaped quantization noise generated in the ΔΣ modulator is efficiently reduced without providing a new circuit for reducing the quantization noise by a loop filter built in the subsequent phase synchronization circuit. be able to.
In other words, by using a Hall element, a ΔΣ modulator, a switch circuit synchronized with a chopper clock signal, and a phase locked loop with a built-in loop filter, all offsets and noise that cause angular errors can be increased in IC area. Therefore, it is possible to realize an angle detection device that is efficiently removed or reduced, highly accurate, highly reliable, and easy to downsize.

It is a block diagram showing the angle detection apparatus as embodiment of this invention. It is a figure showing the structure of the non-contact rotation angle sensor to which the angle detection apparatus of FIG. 1 is applied. FIG. 2 is a vector diagram showing a relationship between each Hall element output signal by a pair of Hall elements in FIG. 1 and a rotation angle θ detected thereby. It is a figure showing a mode that a Hall element output signal arises between the output terminals of a Hall element, when the drive current of a Hall element is changed synchronizing with the chopper clock signal CC. It is a timing chart showing the relationship between the chopper clock signal CC and the Hall element output signal. FIG. 2 is a block diagram illustrating a configuration example of a ΔΣ modulator in FIG. 1. It is a figure of the noise shaping effect by a ΔΣ modulator. It is a figure which shows the specific example of the analog circuit of the Hall element which is the front | former stage of the angle detection apparatus of FIG. 1, and an angle detection apparatus. FIG. 9 is a diagram illustrating a sampling clock signal supplied to the ΔΣ modulator of FIG. 8. It is a figure for demonstrating the removal of the offset of a Hall electromotive force signal and an analog circuit, the removal of pattern noise, and reduction of quantization noise. It is a figure showing the simulation result (when not accompanied by the modulation by a chopper clock signal) about the suppression effect of pattern noise generation. It is a figure showing the simulation result (when accompanied by the modulation by a chopper clock signal) regarding the suppression effect of pattern noise generation.

Hereinafter, the present invention will be clarified by describing embodiments of the present invention in detail with reference to the drawings.
FIG. 1 is a block diagram showing an angle detection apparatus as an embodiment of the present invention. The outputs of the pair of Hall elements 11 and 12 arranged in directions orthogonal to each other are connected so as to be supplied to the corresponding first switch circuit sections 13 and 14.
The Hall element 11 is an element having two pairs of terminals as usual, and is arranged along the X axis among the X axis and the Y axis, which are two orthogonal axes set in a virtual plane. For this reason, hereinafter, the Hall element 11 is appropriately referred to as an X Hall element.

The Hall element 12 is also an element having two pairs of terminals as usual, and is arranged along the Y axis of the above-mentioned X axis and Y axis. For this reason, hereinafter, the Hall element 12 will be appropriately referred to as a Y Hall element.
Further, in connection with the above, the first switch circuit unit 13 corresponding to the X Hall element 11 is hereinafter referred to as an X channel side first switch circuit unit as appropriate.
Similarly, the first switch circuit unit 14 corresponding to the Y Hall element 12 is hereinafter appropriately referred to as a Y channel side first switch circuit unit.

The outputs of the first switch circuit units 13 and 14 are supplied to the corresponding second switch circuit units 17 and 18 through the corresponding preamplifiers 15 and 16.
As for the second switch circuit units 17 and 18, as described above for the first switch circuit units 13 and 14, hereinafter, the X channel side second switch circuit unit and the Y channel side second switch circuit unit will be appropriately Call it.
The outputs of the second switch circuit units 17 and 18 are supplied to the corresponding ΔΣ modulators 50 and 60, respectively.

Also for the ΔΣ modulators 50 and 60, hereinafter, the ΔΣ modulator 50 is appropriately referred to as an X channel side ΔΣ modulator, and similarly, the ΔΣ modulator 60 is also referred to as a Y channel side ΔΣ modulator. .
The outputs of the ΔΣ modulators 50 and 60 are supplied to the corresponding multipliers 21 and 22, and further, the outputs of the multipliers 21 and 22 are supplied to the subtractor 23. A difference output of each output is obtained. The phase error detection circuit 20 is configured including the multipliers 21 and 22 and the subtracter 23.

The output of the subtracter 23 is supplied to a DCO (Digitally Controlled Oscillator) 25 through a loop filter 24 having a low-pass characteristic.
The output of the DCO 25 is an output having a positive / negative sign, and the output of the DCO 25 is always counted by the counter 26 in the next stage.
The count output of the counter 26 is a value of an angle θ _n that has a correlation with the angle to be measured, and is supplied to storage units 27 and 28 that obtain sine and cosine outputs corresponding to the angle θ _n . In the case of this example, the storage unit 27 forms a signal conversion unit that outputs a value of a sine function corresponding to the input angle (data) θ _n , and the storage unit 28 cosines corresponding to the input angle data. It constitutes a signal converter that outputs the value of the function. These storage units 27 and 28 are configured as ROMs holding table data in which the relationship of output data corresponding to the value of the trigonometric function of these data is set corresponding to various angles (data) θ _n supplied to the input side. Can be done.
The output of the storage unit 27 is supplied to the multiplier 21, and the output of the storage unit 28 is supplied to the multiplier 22.

  In the above configuration, the chopper clock signal CC from the chopper clock generation circuit 300 is supplied to the first switch circuit units 13 and 14, the second switch circuit units 17 and 18, and the ΔΣ modulators 50 and 60, respectively. Thus, a switching operation described later is executed. The ΔΣ modulators 50 and 60 are also supplied with the sampling clock signal SC from the sampling clock generation circuit 400, and a ΔΣ modulation operation described later is executed.

In this example, the analog circuit unit 100 includes the first switch circuit units 13 and 14, the preamplifiers 15 and 16, the second switch circuit units 17 and 18, and the ΔΣ modulators 50 and 60. Has been. Further, in the case of the illustrated apparatus, the pair of Hall elements 11 and 12 are stationary and the magnetic field side intersecting them is relatively moved, so that these Hall elements 11 and 12 are also analog circuits. It is provided in the part 100.
Further, the phase error detection circuit 20, the loop filter 24, the DCO 25, the counter 26, and the storage units 27 and 28 constitute a phase synchronization circuit 200 that is a digital circuit unit.

FIG. 2 is a diagram illustrating a configuration of a non-contact rotation angle sensor to which the angle detection device of FIG. 1 is applied. The circuit of the angle detection device in FIG. 1 is housed in the IC package 1 in FIG. Disc-shaped permanent magnets 3 that are coaxially attached to the end portion of the output shaft 2 of the motor at regular intervals are positioned on the upper surface of the IC package 1 so as to oppose each other.
The pair of Hall elements 11 and 12 arranged in the directions orthogonal to each other are arranged stationary in the IC package 1 as described above, but rotate integrally with the output shaft 2 of the motor. The magnetic field generated by the permanent magnet 3 is relatively moved.

FIG. 3 is a vector diagram showing the relationship between the above-described Hall element output signals Vx and Vy from the pair of Hall elements 11 and 12 and the rotation angle θ detected thereby. As described above, the X Hall element 11 and the Y Hall element 12 are arranged in the IC package 1 in FIG. 2 in a positional relationship in which the X Hall element 11 and the Y Hall element 12 are orthogonal to each other. Thus, each Hall element output signal is generated at the pair of detection output terminals.
Hall element output signals Vx and Vy from the X Hall element 11 and the Y Hall element 12 are

である。ここでＡはホール素子の感度である。

It is. Here, A is the sensitivity of the Hall element.

FIG. 4 is a diagram illustrating how the Hall element output signal is generated between the output terminals of the Hall element when the drive current of the Hall element is changed in synchronization with the chopper clock signal CC.
FIG. 4A is a diagram showing the direction of the drive current and the direction of the Hall element output signal in the phase (phase 1) of one half cycle of the chopper clock signal CC, and FIG. It is a figure which shows the direction of the drive current in the phase (phase 2) for every other half cycle of the clock signal CC, and the direction of a Hall element output signal. In either case, it is assumed that the magnetic field is in a direction perpendicular to the paper surface and exiting backward as indicated by the symbol.

  4A and 4B, in phase 1, in the phase 1, a drive current is supplied to one of the two terminals of the Hall element, and the other pair of terminals. The Hall element output signal V1 is obtained from the terminal. Further, in phase 2, a drive current is passed through the other pair of terminals of the two pairs of Hall elements to obtain the Hall element output signal V2 from the one pair of terminals. At this time, the direction of the drive current in phase 1 and the direction of the drive current in phase 2 are perpendicular to each other as shown. Hall element output signals V1 and V2 by the Hall elements are supplied alternately to the corresponding preamplifiers 15 and 16 which are subsequent circuits by the first switch circuit units 13 and 14 in synchronization with the switching of the phase.

The relationship between the drive current and the Hall element output signal described with reference to FIGS. 4A and 4B is, in other words, the Hall signal output signal synchronized with the chopper clock signal CC by the first switch circuit unit. This means that the drive current terminal and the output terminal of the element are alternately switched and connected to the subsequent stage side, and the direction of the drive current of the Hall element is switched.
FIG. 5 is a timing chart showing the relationship between the chopper clock signal CC and the Hall element output signal. FIGS. 5 (a) represents the chopper clock signal CC frequency f _c, FIG. 5 (b) represents the Hall element output signal.

The positive and negative Hall element output signal, because it depends on the direction of the driving current, while being modulated at a frequency f _c of the chopper clock signal CC, the offset of the Hall element output signal does not depend on the orientation of the drive current It becomes a DC component. Therefore, as shown in FIG. 5B, V1 = V _Hall + V _off in phase 1 and V2 = −V _Hall + V _off in phase 2. Since the offset of the Hall electromotive force signal is modulated when demodulating this signal, it is possible to remove the offset of the Hall electromotive force signal by providing a low-pass filter in the subsequent stage.

Here, the description returns to FIG. In the X Hall element 11 system, the X channel side first switch circuit unit 13 switches the Hall element drive current terminal and the output terminal alternately in synchronism with the chopper clock signal CC to provide the preamplifier 15 on the rear stage side. While connecting, the direction of the drive current of the Hall element is switched.
Similarly, with respect to the system of the Y Hall element 12, the Y channel side first switch circuit unit 14 alternately switches the terminal of the Hall element drive current and the output terminal in synchronism with the chopper clock signal CC. The direction of the drive current of the Hall element is switched while being connected to the preamplifier 16.

The output signal of the preamplifier 15 is supplied to the X channel side second switch circuit unit 17, and the sign of the output signal is switched in synchronization with the chopper clock signal CC. This switching is demodulation corresponding to the modulation in the Y-channel first switch circuit unit 14 in the preceding stage. During this demodulation, while the Hall element output signal which has been modulated in the preceding paragraph is demodulated, for offset of the offset and the preamplifier 15 in the X Hall element 11, the modulation is applied by the chopper clock signal CC frequency f _c.

Also for the output signal of the preamplifier 16, the output signal is supplied to the Y channel side second switch circuit section 18, and the sign of the output signal is switched in synchronization with the chopper clock signal CC. As in the X channel side, while the Hall element output signal which has been modulated in the preceding paragraph is demodulated, for offset Y offset and pre-amplifier 16 relates to the Hall element 12, the modulation is applied by the chopper clock signal CC frequency f _c .

  The output signal of the X channel side second switch circuit unit 17 and the output signal of the Y channel side second switch circuit unit 18 as described above are input to the corresponding ΔΣ modulators 50 and 60, respectively. As described above, the ΔΣ modulators 50 and 60 are supplied with the chopper clock signal CC from the chopper clock generation circuit 300 and the sampling clock signal SC from the sampling clock generation circuit 400, and ΔΣ modulation is performed on the input signal. multiply.

FIG. 6 is a block diagram showing a first-order ΔΣ modulator which is a configuration example of ΔΣ modulators 50 and 60. This ΔΣ modulator is given a reference numeral 60 again. This ΔΣ modulator 60 includes an adder 61 at the analog signal input unit, an integrator 62 that integrates the output of the adder 61, a quantizer 63 that quantizes the output of the integrator 62, and a quantizer The digital-analog converter 64 inserted in the loop which feeds back the output of 63 to the adder 61 of the input side is comprised.
The ΔΣ modulator 60 in FIG. 6 is expressed by the following equation (3), where V _in (z) is the input, V _out (z) is the output, and E (z) is the quantization noise.

That is, the transfer function related to quantization noise is (1−z ⁻¹ ). When the transfer function related to the quantization noise is converted into an expression related to the frequency and further expanded to a k-th order ΔΣ modulator, the following expression (4) is obtained.

Here, f _s is the sampling frequency of the ΔΣ modulator as described above. Here, paying attention to the magnitude of the amplitude, the magnitude of the equation (4) is expressed by the following equation (5).

From this equation (5), it can be seen that the quantization noise is shaped toward a higher frequency.
FIG. 7 is a diagram of the noise shaping effect by the ΔΣ modulator. When the noise shaping effect is not considered, the quantization noise is distributed substantially uniformly from the low frequency range to the high frequency range as shown by the broken line. On the other hand, the quantization noise in consideration of the noise shaping effect has a characteristic of gradually increasing toward the high frequency region as shown by the solid line, and its level is low in the low frequency region. Therefore, most of the quantization noise can be removed by applying a low-pass filter as shown by a solid line. In FIG. 7, the quantization noise portion that can be reduced by the noise shaping effect as described above is hatched.

Further, since the phase locked loop circuit unit 200 connected to the subsequent stage of the ΔΣ modulator is provided with a loop filter 24 having the characteristics of a low-pass filter, it is possible to efficiently perform quantization noise without providing another filter. Can be removed well.
Here, the description will be returned to FIG. 1 again, and the phase synchronization circuit 200 will be described in detail. Signal inputted to the phase synchronizing circuit 200, △ sigma modulator 50 and 60 is the output signal of the s1 and s2, as well, there is a digital angle output theta _n. Further, there is a sin [theta _n and cos [theta] _n, which is the output of the memory unit 27 and 28. These signals are supplied to the multipliers 21 and 22 of the phase error detection circuit 20. These multipliers 21 and 22 multiply the corresponding input signals described above to obtain signals s3 and s4 represented by the following equations (6) and (7).

  Here, α is a signal amplification factor of the preamplifier 15 and the preamplifier 16. These s3 and s4 are supplied to the subtracter 23 to obtain a signal s5 represented by the equation (8) which is a difference between them.

When the signal s5 is obtained from the output signals of the ΔΣ modulators 50 and 60 through the phase error detection circuit 20 as described above, there are the following advantages.
S1 = Aαcosθ and S2 = Aαsinθ are signals converted by the ΔΣ modulators 50 and 60 into signed 1-bit signals of +1 and −1. Therefore, S5 is expressed by the following equation (9) by a combination of four positive and negative patterns of S1 and S2.

(9) from the equation, the output signal S5 of the phase error detection circuit, the digital angle output theta _n, can be obtained by adding and subtracting circuit for sin [theta _n and cos [theta] _n obtained through the storage unit 27 and 28.
Therefore, by combining the ΔΣ modulators 50 and 60 and the phase synchronization circuit 200 (its phase error detection circuit 20) as in the present invention, the phase error detection circuit can be realized by an addition / subtraction circuit, and the circuit scale of the phase error detection circuit Can be reduced.
In the present embodiment, the loop filter 24 at the subsequent stage of the phase error detection circuit 20 has an important function.

The loop filter 24 is a filter circuit having a low-pass filter characteristic, and the response characteristic of the present angle detection device, which is a non-contact rotation angle sensor IC, is determined by the frequency characteristic of the loop filter 24. A DCO control signal ω output from the loop filter 24 is used to control a DCO (Digitally Controlled Oscillator) circuit 25. In the DCO circuit 25, at the time t, the value of ω obtained at the sampling time before the time t is integrated by the counter 26 to obtain the digital angle output θ _n .
As described above, the storage unit 27 and the storage unit 28 hold sine and cosine values for θ _n , respectively, and these values sin θ _n and cos θ _n are fed back to the phase error detection circuit 20. Yes. By adopting the configuration as described above, rotation angle detection can be realized.

  In general, nonlinearity as an angle sensor often deteriorates due to nonlinearity of a phase error detection circuit. This is because the DAC (digital / analog converter) is used in the conventional phase error detection circuit, and the nonlinearity of the DAC greatly affects the angle output. For this reason, the DAC in the phase error detection circuit is required to have high linearity, and a resistor array and a capacitor array with excellent matching are required to satisfy this requirement. Therefore, the circuit scale is large and it is difficult to reduce the cost. In the present invention, since the phase error detection circuit that greatly affects the nonlinearity of the angle sensor can be replaced with an addition / subtraction circuit, high detection accuracy can be obtained without increasing the circuit scale.

Then the Hall element output signal offset for the offset and △ sigma modulator offset of the preamplifier is modulated chopper clock frequency f _c, is described in detail with reference to FIG.
FIG. 8 is a diagram illustrating a specific example of the above-described analog circuit among the Hall element, which is the previous stage of the angle detection device of FIG. 1, and the angle detection device. In FIG. 8, the above-described phase synchronization circuit is shown only as one block, but the disclosure relating to this part is the same as in FIG. In FIG. 8, regarding the ΔΣ modulator, reference numerals 50 and 60 in FIG.

First, the switching operation regarding the X Hall element 11 will be described. The output signal of the X Hall element 11 is switched by the corresponding first switch circuit unit 13 so that the output from one of the two pairs of terminals is alternately switched in synchronization with the chopper clock signal CC as described above. Derived and supplied to the preamplifier 15.
The output of the preamplifier 15 is switched and output by the second switch circuit unit 17 so that the polarity is inverted in synchronization with the chopper clock signal CC. Therefore, the modulation received by the first switch circuit unit 13 in the previous stage is Demodulated by the second switch circuit unit 17.

As described above, the operation of modulating the output signal of the Hall element by the first switch circuit unit and demodulating it by the second switch circuit unit is the same as the switching operation for the Y Hall element 12.
When there is an offset, the output signals from the X Hall element 11 and the output signals Vx and Vy from the Y Hall element 12 are expressed by the following equations (10) and (11).

Vx and Vy expressed by the equations (10) and (11) are modulated by the first switch circuit units 13 and 14. As described above, while the Hall electromotive force signal from the output signal and the Y Hall element 12 from the X Hall element 11 is modulated at a frequency f _c of the chopper clock signal CC, the offset of the Hall element output signal is driven Since it does not depend on the direction of current, it becomes a DC component. In the preamplifiers 15 and 16 at the next stage, the input signal is multiplied by α. Although the preamplifiers 15 and 16 also have an offset, they are constant with respect to the input signal, and thus have a direct current component similar to the offset of the Hall electromotive force signal.

  Second switch circuit portions 17 and 18 in the next stage of preamplifiers 15 and 16 alternately switch the connection relationship when a pair of output signals of preamplifiers 15 and 16 are connected to the subsequent stage in synchronization with chopper clock signal CC. For this reason, the signals modulated by the first switch circuit sections 13 and 14 in the previous stage are demodulated into original DC signals by the second switch circuit sections 17 and 18.

Contrast is modulated with the frequency f _c in synchronization with the offset and the offset of the preamplifier of the first switch circuit section 13 and the Hall electromotive force signal has remained as a DC signal without being modulated at 14 chopper clock signal CC . The signals modulated in this way are input to the corresponding ΔΣ modulators 500 and 600, respectively.
The ΔΣ modulators 500 and 600 of the present example are the first-order ΔΣ modulators already described with reference to FIG. 6, but the ΔΣ modulator suitable for the angle detection device of the present invention is the first order. There is no necessity, and a multiple-order ΔΣ modulator can be applied.

  In FIG. 9, the circuit elements of the ΔΣ modulator 500 relating to the channel on the X Hall element 11 side are given reference numerals in the 500s. The circuit elements of the ΔΣ modulator 600 relating to the Y Hall element 12 are given reference numerals in the 600s. Since both ΔΣ modulators 500 and 600 have similar configurations, the configuration of the ΔΣ modulator 500 will be referred to, and for the ΔΣ modulator 600, the corresponding circuit elements are denoted by reference numerals in the 600s. Additional reference is made to the reference to the ΔΣ modulator 500.

The ΔΣ modulator 500 is supplied with a chopper clock signal CC, and the input side changeover switch 510 and the output side changeover switch 550 of the fully differential operational amplifier 530 are switched in synchronization with the signal CC. The fully-differential operational amplifier 530 is provided with capacitors 531 and 532 in each feedback loop via these switches 510 and 550 to constitute a switched capacitor circuit.
Further, the ΔΣ modulator 500 is a two-phase no-overlapping circuit having a frequency f _s as shown in FIG. 9, which is generated based on the sampling clock signal SC from the sampling clock generation circuit 400 of FIG. Sampling clock signals φ1 and φ2 which are clock signals are supplied.

  The illustrated switches 501, 502, 505, and 506 for the ΔΣ modulator 500 are controlled by the sampling clock signal φ1, and the switches 515, 516, 517, and 518 are controlled by the sampling clock signal φ2. The switch group controlled by the sampling clock signal φ1 and the switch group controlled by the sampling clock signal φ2 substantially follow the waveform of the two-phase no-overlap clock signal in FIG. Their opening and closing is controlled in the form of

The integration capacitors 503 and 504 are charged by the potential difference from the ground (GND) potential by the input signal (output signal of the second switch circuit unit 17) s1 when the switch group controlled by the sampling clock signal φ1 is on, and sampling is performed. When the switch group controlled by the clock signal φ2 is on, the signal is supplied to the fully differential operational amplifier 530 through the input side changeover switch 510.
A quantizer 570 is connected to the output side of the fully differential operational amplifier 530 via an output side changeover switch 550. The output s1 of the quantizer 570 is supplied to the phase synchronization circuit 220 described above.

  On the other hand, the output s1 is also used as a switching control signal for the changeover switches 581 and 582. These changeover switches 581 and 582 selectively switch a predetermined positive power supply voltage Vref + and negative power supply voltage Vref− in accordance with the signal s1, and integrate capacitors 503 and 504 via corresponding switches 515 and 516, respectively. Applied to each input side. As a result, the accumulated charges in the integrating capacitors 503 and 504 are reset at a predetermined timing.

Although fully differential operational amplifier 530 described above has an offset, in synchronism with switch 510 and the output side changeover switch 550 input-side switch disposed before and after the fully differential operational amplifier 530 to the chopper clock signal CC frequency f _c 1 by switching the wire pairs alternately, the offset of the fully differential operational amplifier 530 can be modulated to the chopper clock frequency f _c.

As described above, by made modulated offset of the fully differential operational amplifier 530 in the chopper clock frequency f _c, △ sigma output signal of the modulator 500, the Hall electromotive force signal demodulated in DC band, chopper clock frequency f offset of the modulated Hall electromotive force signal _c, and the one that contains the offset of the analog circuit portion 100 of Fig. 1 modulated chopper clock frequency f _c.

In other words, the offset in the offset and the analog circuit portion 100 of the Hall electromotive force signal is modulated at a frequency f _c of all chopper clock signal CC, having a low-pass filter characteristics described above in the subsequent stage of the phase synchronization circuit 200 The loop filter 24 enables efficient removal without newly providing a low-pass filter. Therefore, various offsets can be removed without increasing the complexity of the configuration, and the angle detection accuracy can be improved.

In general, when a DC signal is input to a ΔΣ modulator and used, there is a known problem that tone-like noise called pattern noise is generated from the ΔΣ modulator. A technique for suppressing noise is often used. In this case, it is inevitable that the configuration for performing dithering is complicated or the signal processing is increased.
In contrast, since in the embodiment of the present invention, it is superimposed offset component modulated at the frequency f _c of the chopper clock signal CC to the signal supplied to △ sigma modulator, remove the component with a low pass filter An extremely simple method of doing this works.

FIG. 10 is a diagram for explaining the removal of the Hall electromotive force signal and analog circuit offset, the removal of pattern noise, and the reduction of quantization noise.
As can be easily understood from FIG. 10, since the frequency f _c of the chopper clock signal CC is higher than the band of the loop filter that also functions as a low-pass filter, the pattern noise generated by the ΔΣ modulator is Removed by filter.
As described above, by using the signal processing method of the present invention, it is possible to suppress the generation of pattern noise that becomes a problem in the ΔΣ modulator without adding a new circuit such as a circuit for dithering. That is, the results of actually simulating the effect of suppressing the generation of pattern noise are shown in FIG. 11 and FIG.

FIG. 11 shows a frequency spectrum of a signal output from the ΔΣ modulator when a DC voltage corresponding to 1/1024 of the reference voltage VRef is input to a normal secondary ΔΣ modulator. is there.
When FIG. 11 is seen, many peaks of pattern noise are seen in the signal spectrum including a frequency near 1/1024 of the Nyquist frequency.
FIG. 12 shows that the input signal to the ΔΣ modulator and ΔΣ modulator is the same as in FIG. 11, but the output signal of the Hall element is modulated by the chopper clock signal according to the present invention. This is a frequency spectrum of a signal output from the ΔΣ modulator at a time.
In the frequency spectrum of FIG. 12, it can be seen that almost no pattern noise occurs compared to FIG.

The embodiment described above is an example of an angle detection device configured to be appropriate when a pair of Hall elements arranged in directions orthogonal to each other is applied as a detection element.
However, the technical idea of the present invention is not limited only to the case where the Hall elements are arranged so as to be orthogonal to each other.
That is, the technical idea of the present invention is an angle that can be dealt with when a hall element, which is arranged in pairs so that at least one pair of hall elements intersect with each other at various known angles, is applied as a detection element. The detection device is limited.

1 ………………………………… IC package 2 ………………………………… Output shaft 3 ………………………………… Permanent magnet 11, 12 ... …………………… Hall elements 13, 14 ……………………… First switch circuit parts 15, 16 ……………………… Preamplifiers 17, 18 …………… ………… Second switch circuit unit 21, 22 …………………… Multiplier 23 ……………………………… Subtractor 24 …………………………… ... Loop filter 25 ……………………………… DCO (Digitally Controlled Oscillator)
26 ……………………………… Counter 27, 28 ……………………… Storage section 50, 60, 500, 600… ΔΣ modulator 100 ……………………… …… Analog circuit unit 200 ……………………………… Phase synchronization circuit 300 …………………………… Chopper clock generation circuit 400 …………………………… Sampling clock Generator circuit

Claims (2)

An angle detection device for inputting output signals from at least one pair of Hall elements arranged in directions orthogonal to each other and outputting a value corresponding to a rotational angular displacement from a reference position in a magnetic field,
In synchronization with the clock signal, the first switch circuit unit that alternately switches the drive current terminal and the output terminal of the Hall element to connect to the subsequent stage and switches the direction of the drive current of the Hall element;
A second switch circuit unit that switches a sign of an output signal of the Hall element output from the first switch circuit unit in synchronization with the clock signal;
A ΔΣ modulator that ΔΣ modulates an output signal from the second switch circuit unit;
A storage unit storing sine and cosine corresponding to a plurality of angles;
An angle signal obtained by time integration after removing a high frequency component from a signal based on an output signal of the ΔΣ modulation unit and a predetermined sine and cosine output from the storage unit by a loop filter having a low-pass characteristic. An angle detection loop unit to be supplied to the previous storage unit;
An angle detection device comprising: An angle detection method for obtaining a relative rotation angle with respect to a magnetic field of the Hall element using a vector expressed by outputs from at least one pair of Hall elements arranged in directions orthogonal to each other,
The driving direction of the Hall element is switched at a predetermined frequency and the two pairs of outputs of the Hall element are switched at the predetermined frequency for extraction, and the sign of the extracted signal is inverted at the predetermined frequency to form a pair of holes. A switching step for obtaining an element output signal;
For the Hall element output signal acquired in the switching step, the correspondence relationship between the input signals supplied to the inverting input terminal and the non-inverting input terminal of the operational amplifier to be applied is mutually switched at the predetermined frequency and the non-operational state of the operational amplifier is switched. The value obtained by integrating the input signal by the operational amplifier and the predetermined capacitor is quantized in time series while the correspondence relationship between the output signals taken out from the inverting output terminal and the inverting output terminal is mutually switched at the predetermined frequency. ΔΣ modulation step for applying ΔΣ modulation,
An angle error (θ−θ _n ) between the angle data θ corresponding to the phase difference between the paired Hall element output signals and the angle data θ _n held in advance is calculated, and the calculated angle error A closed-loop phase synchronization step of detecting the angle data θ by performing control to remove the high-frequency component included by a loop filter and increase or decrease the counter value according to the value of the angle error. Detection method.

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