JP2010212742A - Level shift circuit, switching element driving circuit, and inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit, a switching element driving circuit, and an inverter device, which can transmit a signal without being clamped even when common mode noise due to voltage variation etc. of the level shift circuit occurs. <P>SOLUTION: The level shift circuit includes: a pulse generating circuit which generates a set pulse and a reset pulse; a first switching element which converts the set pulse into a current and a second switching element which converts the reset pulse into a current; a load for setting which is on a floating potential side and converts a signal, converted into the current by the first switching element, into a voltage; a load for resetting which converts a signal, converted into a current by the second switching element, into a voltage; and a pulse regenerating circuit which regenerates a control pulse signal from the signal level of the load for setting and the signal level of the load for resetting. The level shift circuit uses circuits having nonlinear load characteristics as the load for setting and the load for resetting. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a level shift circuit, a switching element drive circuit, and an inverter device used in a power converter.

  In a power converter such as an inverter, a power switching element for driving a load is connected in series between main power supply terminals. The midpoint between the lower power switching element (hereinafter referred to as “lower arm switching element”) and the higher power switching element (hereinafter referred to as “upper arm switching element”) is connected to the load. Has been.

  In such a device, the reference potential of the upper arm switching element is driven in a floating state. Therefore, drive control of the upper arm switching element is transmitted from a reference potential side of the lower arm switching element by a circuit called level shift.

  In the level shift unit of the conventional switching element driving circuit shown in FIG. 1 of Patent Document 1, a resistor is used as a load for converting a level shift signal into a voltage. Further, a Zener diode is used to clamp the load voltage to a desired voltage due to a withstand voltage so as not to exceed a certain level.

JP 2007-235245 A

  Thus, in the conventional level shift circuit, when the level shift current exceeds a certain level, it is clamped. Therefore, when a noise current of the same phase flows due to voltage fluctuations such as dv / dt, a normal signal is transmitted. I can't.

  In the present invention, a level shift circuit that transmits a normal signal without clamping even when a common-mode noise current due to voltage fluctuation flows, a switching element drive circuit including the level shift circuit, and an inverter device using the level shift circuit For the purpose of provision.

  In order to solve the above problems, a level shift circuit according to the present invention includes a first reference potential, a second reference potential that is a floating potential with respect to the first reference potential, and a first reference potential side. A pulse generation circuit for generating a set pulse corresponding to a rising edge and a reset pulse corresponding to a falling edge of a control pulse signal transmitted from the first reference potential side to the second reference potential side; and the set A first switching element that converts a pulse into a current, a second switching element that converts the reset pulse into a current, and a signal that is on the second reference potential side and converted into a current by the first switching element A set load for converting the signal into a voltage, a reset load for converting the signal converted into a current by the second switching element into a voltage, and the set load and From the signal level of the reset load, the set pulse detection circuit that detects the set pulse, the reset pulse detection circuit that detects the reset pulse, the output signal of the set pulse detection circuit, and the output signal of the reset pulse detection circuit A pulse regeneration circuit that regenerates the control pulse signal, wherein the set load and the reset load have a current that increases and an impedance that decreases.

  According to the present invention, even if a common mode noise current due to dv / dt or the like is generated, the voltage of the level shift receiving circuit is not clamped, so that a normal signal can be transmitted. Further, the Zener diode for clamping can be omitted.

FIG. 1 is a block diagram for one phase of an inverter device according to a first embodiment of the present invention. FIG. 2 is a graph showing the relationship between the level shift current and the voltage in comparison with the present invention. FIG. 3 is a block diagram of one phase of the inverter device according to the second embodiment of the present invention. FIG. 4 is a circuit configuration diagram showing the level shift operation of the set pulse detection comparator according to the second embodiment of the present invention. FIG. 5 is a circuit configuration diagram showing the level shift operation of the set pulse detection comparator according to the third embodiment of the present invention. FIG. 6 is a waveform diagram showing the operation of the level shift circuit of the present invention. FIG. 7 is a circuit diagram in which the level shift circuit according to the fourth embodiment of the present invention is used for level down.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows one phase of the three-phase inverter device of this embodiment. The same applies to the other two phases. An upper arm power switching element (hereinafter referred to as “upper arm element”) 302 and a lower arm power switching element (hereinafter referred to as “lower arm element”) 301 are provided between the main power supplies HV. A totem pole connection (series connection) is made to form a half bridge. A connection point 5 between the upper arm element 302 and the lower arm element 301 is connected to the load 6 and serves as a reference potential for driving the upper arm element 302.

  The upper arm element 302 and the lower arm element 301 are configured by an IGBT (insulated gate bipolar transistor) 2 and an FWD (free wheel diode) 4 and IGBTs 1 and FWD 3, respectively. In the present embodiment, the upper and lower arm elements 301 and 302 for one phase are housed in the power module 300.

  The switching element drive circuit 101 for the upper and lower arms for one phase includes a lower arm control circuit 200 and an upper arm control circuit 201. VD1 is a power source for the lower arm control circuit 200. VD2 is a power source for the upper arm control circuit 201, and is insulated from VD1 by a transformer.

  Next, the flow of drive control will be described. The input signals P_PIN (upper arm drive control signal) and P_NIN (lower arm drive control signal) are given from a host controller (not shown). For the upper arm drive pulse signal, the pulse generation circuit 31 generates a set pulse signal P_S corresponding to the rising timing of the pulse and a reset pulse signal P_R corresponding to the falling timing.

  The level shift circuit 910 includes a pulse generation circuit 31, level shift current driving NMOSFETs 12 and 13, load PMOS EFTMs 20 and M 21 that convert current into voltage, and an RS flip-flop 62. In the level shift circuit 910, the level shift NMOSFETs 12 and 13 are driven by the set pulse signal P_S and the reset pulse signal P_R, the pulse signal is converted into a current, and the voltage is converted by the level shift loads M20 and M21 on the upper arm side. The

  The voltage signal V_S accompanying the set pulse is input to the set of the RS flip-flop 62 in the next stage, and the voltage signal V_R accompanying the reset pulse is input to the reset to reproduce the pulse. The upper arm element 302 is driven by a buffer circuit (DRV) 63.

  FIG. 2 shows the relationship between the current and voltage of the level shift circuit in comparison with the prior art and the present invention. In the level shift (2) using the conventional resistance load, it is necessary to provide a protective Zener diode in parallel with the load resistance so that the level shift allowable signal level is not exceeded.

  On the other hand, since the level shift (1) of the present invention uses a diode-connected PMOSFET as a load, when the level shift current increases, the impedance decreases, and the level shift voltage can be suppressed within the allowable level range. In addition, since the impedance is high in a region where the current is low, the minimum operating current can be suppressed to a low level, so that the level shifting operating current can be reduced.

  In the conventional level shift (2), the control range of the level shift current is limited to a relatively narrow range that intersects the level shift allowable signal level from the linear load minimum operating current, whereas the level shift (1) of the present invention is limited. ), The control range of the level shift current can be controlled in a wide range from the nonlinear load minimum operation current along the level shift allowable signal level.

  FIG. 3 shows an embodiment in which the level shift circuit of the present invention has a differential configuration. The only difference from FIG. 1 is that the level shift receiving circuit 910 has a differential configuration. In FIG. 3, a level shift receiving circuit 910 includes a pulse generation circuit 31, level shift current driving NMOSFETs 12 and 13, load PMOSEFTMs 20 and M21 for converting current into voltage, a set pulse detection comparator 52 and a reset pulse detection comparator. 53 and an RS flip-flop 62.

  Only the operation of the level shift receiving circuit will be described. The V_S signal of the set pulse load resistor is input to the non-inverting input side of the set pulse detection comparator 52, and the V_R signal of the reset pulse load resistor is input to the inverting input side.

  Similarly, the V_S signal of the reset pulse load resistor is input to the non-inverting input side of the reset pulse detection comparator 53, and the V_R signal of the set pulse load resistor is input to the inverting input side. The outputs of the comparators 52 and 53 are input to the RS flip-flop 62 via the LPFs 60 and 61. The upper arm element 302 is driven by a buffer circuit (DRV) 63.

  FIG. 4 is a circuit diagram showing an example of the comparator 52 of the present embodiment. The set pulse detection comparator 52 includes an interface unit 92, a standby bias unit 91, a differential pair 90, and a level conversion unit 93. VD2 is a power supply for driving the upper arm, VD3 is a power supply for the upper arm control circuit, and VD2> VD3. 74, 75 and 80 are constant current sources.

  The differential pair includes PMOSFETs 70 and 71, a constant current source 80, and load MOSs 72 and 73. The differential pair input level is normally biased to a desired level by a bias circuit including resistors 76 and 77 and constant current sources 74 and 75. When the input level of the differential pair is the same, the output of the differential pair should be “Lo”. The dead zone is set by the constants of the load MOSs 72 ′ and 73.

  The operation during the operation of the level shift circuit will be described. When the level shift NMOSFET 12 is turned on by the level shift drive pulse P_S, the V_S level is lowered. When the level of V_S becomes lower than the level obtained by subtracting the VF (forward voltage drop) of the diode 78 from the bias level, the Vgs of the PMOSFET 70 ′ increases, the drain voltage of the load MOS 72 ′ increases, and the NMOSFET 81 of the next level conversion circuit Is turned on, and a “Lo” pulse is transmitted to the LPF 60 in the next stage.

By configuring the interface unit 92 with a diode, the range of the input level of the comparator is appropriately limited, contributing to stable operation of the comparator.
The input level is limited to a range from the level at which the voltage level of the load resistor is lower than the standby bias level by VF of the diode to the voltage determined by the operating point of the PMOS of the load. For this reason, there is also an effect of preventing a reverse current flow when a reverse surge occurs between the upper and lower arms.

  Next, the operation when an erroneous signal is generated due to common mode noise such as dv / dt will be described. When the reference potential between the upper and lower arms fluctuates, a current of a product of dv / dt and a parasitic capacitance such as a level shift MOSFET flows to the level shift unit. As a result, a voltage is generated on both the set side and the reset side in the level shift load.

  In the present invention, the set pulse detection comparator 52 provides an input dead zone, so that the differential pair does not react in the in-phase mode, so that erroneous detection can be suppressed.

  FIG. 5 shows one phase of the three-phase inverter device of this embodiment. The outline is the same as FIG. 3 of the second embodiment. In this embodiment, the upper arm drive control semiconductor chip 211, the lower arm drive control semiconductor chip 210, and the level shift IGBTs 10 and 11 are mounted in the same switching element drive circuit 100 package.

The level shift differential receiving unit is also different from that in FIG. As the load, two stages of diode-connected PMOSFETs are connected in series, and a resistor is arranged in parallel with each stage of the PMOSFET.
In FIG. 5, a level shift receiving circuit 910 includes a pulse generation circuit 31, level shift IGBTs 10 and 11, loads M20 to M23 and R20 to R23, a set pulse detection comparator 50, a reset pulse detection comparator 51, and an LPF (low pass). Filter) 60 and 61, and RS flip-flop 62.

  The level shift IGBTs 10 and 11 are driven by the set pulse signal P_S and the reset pulse signal P_R, the pulse signal is converted into a current, and the voltage is converted by the level shift load on the upper arm side. The load is composed of M20 to M23 and R20 to R23.

  The set pulse detection comparator 50 receives a high level V_S (H) signal of the set pulse load on the non-inverting input side, and a low level side V_R (L) of the reset pulse load on the inverting input side. Input the signal. Similarly, a reset pulse load high level V_S (H) signal is input to the non-inverting input side of the reset pulse detection comparator 51, and a set pulse load low level V_R is input to the inverting input side. Input the signal (L).

  The outputs of the comparators 50 and 51 are input to the RS flip-flop 62 via LPFs (low-pass filters) 60 and 61. The upper arm element 302 is driven by a buffer circuit (DRV) 63.

  FIG. 6 is a circuit diagram showing an example of the comparator 50 of the present embodiment. The set pulse detection comparator 50 includes an interface unit 92, a standby bias unit 91, a differential pair 90, and a level conversion unit 93. VD2 is a power supply for driving the upper arm, VD3 is a power supply for the upper arm control circuit, and VD2> VD3. 74, 75 and 80 are constant current sources.

  The differential pair includes PMOSFETs 70 and 71, a constant current source 80, and load MOSs 72 and 73. The differential pair input level is normally biased to a desired level by a bias circuit including resistors 76 and 77 and constant current sources 74 and 75. When the input levels of the differential pair are the same, the dead band is set by the constants of the load MOSs 72 and 73 so that the output of the differential pair becomes “Lo”.

FIG. 7 shows an embodiment of a level shift circuit for transmitting a status signal generated by the upper pulse status pulse generation circuit 32 from the upper arm control circuit side to the lower arm drive control side. The level shift drive devices 14 and 15 are configured by PMOSFETs, and the level shift loads 24 and 25 on the lower arm side are configured by diode-connected NMOSFETs, which are connected to the set pulse detection comparator 54 and the reset pulse detection comparator 55. Since this level shift performs a level down operation, the basic operation is the same as the level up described with reference to FIG. 3 except that the polarity is reversed. Thus, by switching the polarity, the present invention can be applied to a level down circuit.

1 Lower arm IGBT (Insulated gate bipolar transistor)
2 Upper arm IGBT
3 FWD (Freewheel Diode)
4 FWD
5 Connection point 6 Load 10 Level shift IGBT
11 Level shift IGBT
12 Level shift MOSFET
13 Level shift MOSFET
14 PMOSFET for level shift
15 PMOSFET for level shift
18 Level shift load on the upper arm side 19 Level shift load on the upper arm side 20 Level shift load on the upper arm side 21 Level shift load on the upper arm side 22 Level shift load on the upper arm side 23 Level shift load on the upper arm side Level shift load 24 Lower arm level shift load 25 Lower arm level shift load 30 Upper and lower pulse generation circuit 31 Pulse generation circuit 32 Upper arm status pulse generation circuit 50 Set pulse detection comparator 51 Reset pulse detection comparator 52 Set Pulse Detection Comparator 53 Reset Pulse Detection Comparator 54 Set Pulse Detection Comparator 55 Reset Pulse Detection Comparator 60 LPF (Low Pass Filter)
61 LPF (low pass filter)
62 RS flip-flop 63 Buffer circuit (DRV)
64 Buffer circuit (DRV)
70 PMOSFET
71 PMOSFET
72 Load MOS
73 Load MOS
74 Constant Current Source 75 Constant Current Source 76 Resistor 77 Resistor 78 Diode 79 Diode 80 Constant Current Source 81 NMOSFET
82 Constant Current Source 90 Differential Coupler 91 Standby Bias Unit 92 Interface Unit 93 Level Conversion Unit 100 Switching Element Drive Circuit 101 Switching Element Drive Circuit 200 Lower Arm Control Circuit 201 Upper Arm Control Circuit 300 Power Module 301 Lower Arm Power Switching Element (lower arm element)
302 Upper arm power switching element (upper arm element)
910 level shift circuit

Claims (8)

A first reference potential and a second reference potential that is a floating potential with respect to the first reference potential;
A set pulse corresponding to a rising edge and a reset pulse corresponding to a falling edge of a control pulse signal that is on the first reference potential side and is transmitted from the first reference potential side to the second reference potential side is generated. A pulse generation circuit that
A first switching element that converts the set pulse into a current and a second switching element that converts the reset pulse into a current;
A set load that is on the second reference potential side and that converts a signal converted into a current by the first switching element into a voltage and a signal that is converted into a current by the second switching element are converted into a voltage Reset load,
In a level shift circuit comprising: a pulse regeneration circuit that regenerates the control pulse signal from the signal level of the set load and the signal level of the reset load;
The level shift circuit, wherein the set load and the reset load have non-linear load characteristics. A first reference potential and a second reference potential that is a floating potential with respect to the first reference potential;
A set pulse corresponding to a rising edge and a reset pulse corresponding to a falling edge of a control pulse signal that is on the first reference potential side and is transmitted from the first reference potential side to the second reference potential side is generated. A pulse generation circuit that
A first switching element that converts the set pulse into a current and a second switching element that converts the reset pulse into a current;
A set load that is on the second reference potential side and that converts a signal converted into a current by the first switching element into a voltage and a signal that is converted into a current by the second switching element are converted into a voltage Reset load,
A set pulse detection circuit for detecting the set pulse and a reset pulse detection circuit for detecting the reset pulse from signal levels of the set load and the reset load;
In a level shift circuit comprising: a pulse regeneration circuit that regenerates the control pulse signal from an output signal of the set pulse detection circuit and an output signal of the reset pulse detection circuit;
The level shift circuit, wherein the set load and the reset load have non-linear load characteristics. The level shift circuit according to claim 1 or 2,
2. The level shift circuit according to claim 1, wherein the set load and the reset load are composed of diode-connected transistors, and the impedance decreases as the current increases. The level shift circuit according to claim 1 or 2,
2. The level shift circuit according to claim 1, wherein the set load and the reset load are configured by diode-connected MOSFETs, and the impedance decreases as the current increases. The level shift circuit according to claim 2, wherein
The set pulse detection circuit compares the signal level of the set load provided with an offset and the signal level of the reset load,
A level shift circuit, wherein the set pulse is detected by determining that the level of the set load is lower than the offset compared to the level of the reset load. A first reference potential and a second reference potential that is a floating potential with respect to the first reference potential;
A set pulse 2 corresponding to a rising edge of a status signal that is on the second reference potential side and is transmitted from the second reference potential side to the first reference potential side, and a reset pulse 2 corresponding to the falling edge. A pulse generation circuit 2 for generating;
A third switching element that converts the set pulse 2 into a current and a fourth switching element that converts the reset pulse 2 into a current;
A load for set 2 that is on the first reference potential side and that converts a signal converted into a current by the third switching element into a voltage, and a signal that is converted into a current by the fourth switching element is converted into a voltage Reset 2 load to
A set pulse 2 detection circuit for detecting the set pulse 2 and a reset pulse 2 detection circuit for detecting the reset pulse 2 from signal levels of the set 2 load and the reset 2 load;
A level shift circuit comprising: a pulse regeneration circuit 2 that regenerates the status signal from an output signal of the set pulse 2 detection circuit and an output signal of the reset pulse 2 detection circuit;
2. The level shift circuit according to claim 1, wherein the load for the set 2 and the load for the reset 2 have a non-linear load characteristic including an N-channel MOSFET having a diode connection. A switching element drive circuit for driving and controlling the first and second power switching elements connected in series between main power supply terminals;
A control pulse from the first reference potential side with respect to the ground side potential of the first power switching element to the second reference potential side with reference to the connection point of the first and second power switching elements. In a switching element driving circuit including a level shift circuit for transmitting a signal,
The level shift circuit includes the first reference potential and the second reference potential that is a floating potential with respect to the first reference potential;
A set pulse corresponding to a rising edge and a reset pulse corresponding to a falling edge of a control pulse signal that is on the first reference potential side and is transmitted from the first reference potential side to the second reference potential side is generated. A pulse generation circuit that
A first switching element that converts the set pulse into a current and a second switching element that converts the reset pulse into a current;
A set load that is on the second reference potential side and that converts a signal converted into a current by the first switching element into a voltage and a signal that is converted into a current by the second switching element are converted into a voltage Reset load,
A set pulse detection circuit for detecting the set pulse and a reset pulse detection circuit for detecting the reset pulse from signal levels of the set load and the reset load;
A pulse regeneration circuit for regenerating the control pulse signal from the output signal of the set pulse detection circuit and the output signal of the reset pulse detection circuit,
The switching element drive circuit, wherein the set load and the reset load have nonlinear load characteristics. First and second switching elements connected in series between main power supply terminals; a first control power supply based on a first reference potential which is a ground-side potential of the first switching element; A second control power source having a connection point potential of the first and second switching elements as a second reference potential, and the second switching element drive control signal from the first reference potential to the second reference potential. In an inverter device comprising a level shift circuit for transmitting to the side and a buffer circuit for driving the first and second switching elements,
The level shift circuit includes the second reference potential that is a floating potential with respect to the first reference potential and the first reference potential.
A set pulse corresponding to a rising edge and a reset pulse corresponding to a falling edge of a control pulse signal that is on the first reference potential side and is transmitted from the first reference potential side to the second reference potential side is generated. A pulse generation circuit that
A first switching element that converts the set pulse into a current and a second switching element that converts the reset pulse into a current;
A set load that is on the second reference potential side and that converts a signal converted into a current by the first switching element into a voltage and a signal that is converted into a current by the second switching element are converted into a voltage Reset load,
A set pulse detection circuit for detecting the set pulse and a reset pulse detection circuit for detecting the reset pulse from signal levels of the set load and the reset load;
A pulse regeneration circuit for regenerating the control pulse signal from the output signal of the set pulse detection circuit and the output signal of the reset pulse detection circuit,
The inverter device, wherein the set load and the reset load have nonlinear load characteristics.

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