JP2010212729A - Semiconductor device and manufacturing method of the same - Google Patents
Semiconductor device and manufacturing method of the same Download PDFInfo
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- JP2010212729A JP2010212729A JP2010119301A JP2010119301A JP2010212729A JP 2010212729 A JP2010212729 A JP 2010212729A JP 2010119301 A JP2010119301 A JP 2010119301A JP 2010119301 A JP2010119301 A JP 2010119301A JP 2010212729 A JP2010212729 A JP 2010212729A
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract
Description
本発明は、金線などによるワイヤボンドをされず、ワイヤの代りに金属片でチップとリードとを繋いだワイヤボンドレスの半導体装置およびその製造方法に関する。 The present invention relates to a wire bondless semiconductor device in which a chip and a lead are connected by a metal piece instead of a wire, and a manufacturing method thereof.
従来の半導体装置としては、上面に電極部を設けた半導体チップと、該半導体チップの下面に接続した第一のリード端子と、電極部に接続した第二のリード端子と、半導体チップおよび第一乃至第二のリード端子の一部を覆うモールド部とを備えてなる半導体装置であって、電極部と第二のリード端子とをフレームを介して接続しているものがあった(例えば、特許文献1参照)。 As a conventional semiconductor device, a semiconductor chip having an electrode portion on the upper surface, a first lead terminal connected to the lower surface of the semiconductor chip, a second lead terminal connected to the electrode portion, the semiconductor chip and the first There is a semiconductor device including a mold part that covers a part of the second lead terminal, in which the electrode part and the second lead terminal are connected via a frame (for example, a patent). Reference 1).
図3は、特許文献1に記載された従来の半導体装置を示す図である。図3において、101は第一リード端子、102は第二リード端子、103は半導体チップ、105は電極部、107はフレーム、108はモールド部を示す。
FIG. 3 is a diagram showing a conventional semiconductor device described in
上記フレーム107は、電極部105と第二リード端子102との間を、該第二リード端子102と電極部105とに各々はんだ接続(図示せず)にて電気的に接続されている。この構成によって、フレーム107をその一方端部を電極部105上に、その他方端部を第二リード端子上に位置させて載置して接続することが可能となるため、半導体チップ103に対して押圧力を付加する必要なく上記接続が可能と成り、第一リード端子101上における半導体チップ103の位置ずれを発生させたり、電極部105を傷つけたりすることなく、容易に上記接続をなし得る事ができた。
The
しかしながら、従来の構成では、フレーム107と、電極部105及び第二リード端子102とをはんだ接続させる際の熱で融解したはんだが、毛管現象にてフレーム107と半導体チップ103との間隙を伝って電極部105の外へ流れ出て、極端な場合は半導体チップ103の側面にまで達する事が有り、これらの場合は半導体チップ103の電気特性が、リーク大やショートといった半導体装置としての電気特性が損なわれた不具合品となる課題を有していた。
However, in the conventional configuration, the solder melted by heat when soldering the
本発明は、従来の課題を解決するもので、組み立ての際にロー付けするにおいて、融解したロー材が流れて不具合品となる事が無く、且つ、効率良く製造が可能な半導体装置とその製造方法を提供する事を目的とする。 SUMMARY OF THE INVENTION The present invention solves the conventional problems, and a semiconductor device that can be efficiently manufactured without causing a molten solder material to flow and become a defective product when brazed during assembly, and its manufacture The purpose is to provide a method.
従来の課題を解決するために、本半導体装置の発明は、クランク状に段差を設けてフォーミングされた第一リード端子の上段第一主面に半導体チップがロー付けにて電気的に導通され、該半導体チップの第一主面には電極部を有し、クランク状に段差を設けてフォーミングされた第二リード端子が前記第一リード端子と対向して且つ前記第一リード端子の下段第二主面と前記第二リード端子の下段第二主面とが同一面に設けられ、前記電極部と前記第二リード端子の上段第一主面とにロー材を有し、前記電極部と前記第二リード端子の上段第一主面とを前記ロー材で接続されたフレームを介して電気的に導通され、前記半導体チップと前記電極部と前記ロー材と前記フレームと、前記第一リード端子と前記第二リード端子との一部を含んで覆ったモールド部を備えてなる半導体装置に於いて、フレームは、電極部側の端部である第一先端部が、当該第一先端部を除く中央部分より下段となるように、クランク状に段差を設けてフォーミングされ、電極部の表面より小さく形成された第一先端部の第二主面が、電極部の表面に収まるように、電極部に固定されており、第一先端部の第二主面と電極部とがロー付けされた際における、第一先端部の第二主面を取り囲む前記第一先端部の側面へのロー材の毛管現象によって、ロー材が第一先端部の側面に濡れ上がっている。 In order to solve the conventional problems, the semiconductor device of the present invention is electrically conductive by brazing the upper first main surface of the first lead terminal formed by providing a step in a crank shape, The first main surface of the semiconductor chip has an electrode portion, and a second lead terminal formed with a step in a crank shape is opposed to the first lead terminal and the second lower terminal of the first lead terminal. The main surface and the lower second main surface of the second lead terminal are provided on the same surface, and have a brazing material on the electrode portion and the upper first main surface of the second lead terminal, and the electrode portion and the The upper lead first main surface of the second lead terminal is electrically connected through the frame connected by the brazing material, the semiconductor chip, the electrode portion, the brazing material, the frame, and the first lead terminal. And part of the second lead terminal In the semiconductor device comprising the mold part, the frame has a crank-like step so that the first tip part, which is the end part on the electrode part side, is below the center part excluding the first tip part. The second main surface of the first tip portion that is formed to be smaller than the surface of the electrode portion is fixed to the electrode portion so as to fit on the surface of the electrode portion, and the second tip surface of the first tip portion is When the main surface and the electrode portion are brazed, the brazing material is formed on the side surface of the first tip portion by capillary action of the brazing material on the side surface of the first tip portion surrounding the second main surface of the first tip portion. Is getting wet.
また、本半導体装置の別の発明は、電極部表面と第二リード端子の上段第一主面とが同一高さに位置する事を特徴とする。 Another invention of the present semiconductor device is characterized in that the surface of the electrode portion and the upper first main surface of the second lead terminal are positioned at the same height.
また、本半導体装置の別の発明は、フレームの形状が左右対称で、双方の先端が同様な構成である事を特徴とする。 Another invention of the present semiconductor device is characterized in that the shape of the frame is bilaterally symmetric and the tips of both are the same.
また、本半導体装置の別の発明は、フレームの先端形状が、クランク状に段差を設けた第一先端部と、該第一先端部に対して反対側に形成されたクランク状の段差である第二先端部とで左右対称である事を特徴とする。 In another aspect of the present invention, the tip shape of the frame is a first tip portion having a crank-like step, and a crank-like step formed on the opposite side of the first tip portion. It is characterized by being symmetrical with the second tip.
本構成によって、組み立ての際にロー付けするにおいて、融解したロー材が流れて不具合品となる事が無く、且つ、効率良く製造が可能な半導体装置とすることができる。 With this configuration, when brazing is performed during assembly, the molten brazing material does not flow and become a defective product, and the semiconductor device can be manufactured efficiently.
以上のように、本発明の半導体装置によれば、組み立ての際にロー材の延展による不具合品が発生を防止出来て、効率良く製造が可能な半導体装置とすることができる。 As described above, according to the semiconductor device of the present invention, it is possible to prevent a defective product due to the spreading of the brazing material during assembly, and to obtain a semiconductor device that can be efficiently manufactured.
以下、本発明の実施の形態について、図面を参照しながら説明する。図1は発明の実施の形態を示す断面図であり、図2は発明の製造方法を示す上面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the invention, and FIG. 2 is a top view showing a manufacturing method of the invention.
図1および図2において、1は第一リード端子、2は第二リード端子、3は半導体チップ、4は電極部、5は第一のはんだ、6は第二のはんだ、7はフレーム、7aは第一先端部、7bは第二先端部、8はモールド部、10はフレームII、10aは第一の溝、10bは第二の溝を各々示している。 1 and 2, 1 is a first lead terminal, 2 is a second lead terminal, 3 is a semiconductor chip, 4 is an electrode portion, 5 is a first solder, 6 is a second solder, 7 is a frame, and 7a. Is the first tip, 7b is the second tip, 8 is the mold part, 10 is the frame II, 10a is the first groove, and 10b is the second groove.
(第1の実施形態)
図1(a)は、本発明の第1の実施形態に係る半導体装置の断面図である。図1(a)は、クランク状に段差を設けてフォーミングされた第一リード端子1の上段第一主面に半導体チップ3がロー付けにて電気的に導通され、該半導体チップ3の第一主面には電極部4を有し、クランク状に段差を設けてフォーミングされた第二リード端子2が第一リード端子1と対向して、且つ、第一リード端子1の下段第二主面と該第二リード端子2の下段第二主面とが同一面に設けられ、電極部4と第二リード端子2の上段第一主面とにロー材である第一のはんだ5とロー材である第二のはんだ6とを有し、電極部4と第二リード端子2の上段第一主面とを第一のはんだ5と第二のはんだ6とではんだ接続された金属片であるフレーム7を介して電気的に導通され、半導体チップ3と電極部4と第一のはんだ5と第二のはんだ6とフレーム7と、第一リード端子1と第二リード端子2との一部を含んで覆ったモールド部8を備えてなる半導体装置である。
(First embodiment)
FIG. 1A is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. In FIG. 1A, the
ここで、上述のフレーム7は、その両端が該フレーム7に対して下段となる方向に各々クランク状に段差を設けてフォーミングされたフレーム7の第一先端部7aと第二先端部7bとして形成されており、第一先端部7aの第二主面側と電極部4と、第二先端部7bの第二主面側と第二リード端子2の上段第一主面とを各々第一のはんだ5と第二のはんだ6とを介して電気的に導通を取って固定されているが、第一先端部7aの第二主面を電極部4表面よりも内側に納まる様に小さく形成されている。
Here, the above-mentioned
かかる構成によれば、半導体装置としての組み立ての際に、電極部4と第一先端部7aとをはんだ接続させる際の熱で融解したはんだが、表面張力と濡れ上がり現象とによって第一先端部7aを電極部4の中央に位置させて保つセルフアライメントと共に、第一先端部7aの外側に位置する電極部4の外周面から第一先端部7a側面にかけて濡れ上がって行き(図示せず)、毛管現象によるはんだの延展防止手段と成り、電極部4の外側にはんだが流れ出て半導体チップ3の表面や側面に付着する事が防止できるので、融解したはんだが流れて不具合品となる事のない半導体装置とすることができる。
According to such a configuration, during assembly as a semiconductor device, the solder melted by heat when the electrode portion 4 and the
また、電極部4表面と第二リード端子2の上段第一主面とを同一高さの面とする事によって、フレーム7の形状を左右対称とすることが可能なので、組み立ての際の部品供給としてフレーム7の方向性を考慮する必要が無くなる事や、組み立ての際第一のはんだ5と第二のはんだ6とが同一高さの面に載置できるので、スクリーン印刷等を用いて一括してクリームはんだとして第一のはんだ5と第二のはんだ6とを材料供給できるので、製造の簡略化や高効率化が可能な半導体装置とすることができる。
In addition, since the surface of the electrode portion 4 and the upper first main surface of the
この様な半導体装置の製造方法としては、図2を参考にできる。即ち、第一リード端子1と該第一リード端子1に段差の上段同士を対向させて形成された第二リード端子2とを含んで連続した枠体に形成されたリードフレームの第一リード端子1の上段第一主面にはんだ等(図示せず)を介して半導体チップ3をロー付けするチップ接着工程と、該半導体チップ3の上面に形成された電極部(図示せず)上と第二リード端子2上とに印刷や塗布等の方法を用いて第一のはんだ5と第二のはんだ6とを載置してフレーム7を第一のはんだ5と第二のはんだ6とに架けて載置するフレーム載置工程と、加熱炉を用いて第一のはんだ5と第二のはんだ6とを融解して電極部(図示せず)と第二リード端子2とに架けてフレーム7をロー付けするフレーム接着工程と、モールド型にリードフレームを勘合させて半導体チップ3とフレーム7と、第一リード端子1と第二リード端子2との一部を含んだキャビティーを形成し該キャビティー内にモールド用樹脂を注入して加熱硬化させてモールド部8を形成するモールド工程と、モールド部8から引き出されたリードフレームの一部である第一リード端子1と第二リード端子2とのリード端子先端予定部を各々切断して外部引出し端子としての第一リード端子1と第二リード端子2とするリード端子切断工程とにより製造する事ができる。
As a method for manufacturing such a semiconductor device, FIG. 2 can be referred to. That is, the first lead terminal of the lead frame formed in the continuous frame including the
(第2の実施の形態)
図1(b)は、本発明の第2の実施形態に係る半導体装置の断面図である。図1(b)は、第1の実施形態で示した図1(a)の第二リード端子2の上段第一主面と電極部4表面とを同一高さの面とし、フレーム7をフレームII10に置き換えたもので、他は図1(a)と同様である。
(Second Embodiment)
FIG. 1B is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 1B shows an upper first main surface of the
ここで、フレームII10は、上述のフレーム7の様なフォーミングにて段差を設ける事なく、電極部4上面と第二リード端子2の上段第一主面とを略直線状に繋ぐものである。また、フレームII10の電極部4上部に位置する部分は、その有する寸法幅が電極部4の対比する寸法よりも狭く、該フレームII10の第二主面で幅方向に横断して、且つ、電極部4の両端である外縁近傍の内側に対比する部位の二箇所に溝切りされた第一の溝10aが形成されている。
Here, the frame II10 connects the upper surface of the electrode portion 4 and the upper first main surface of the
かかる構成によれば、半導体装置としての組み立ての際に電極部4とフレームII10とをはんだ接続させる際の熱で融解したはんだが、濡れ上がり現象と毛管現象とによって、フレームII10の幅方向外側に位置する電極部4の表面からフレームII10側面にかけて濡れ上がって行き(図示せず)、フレームII10と電極部4との間隙を伝って該フレームII10の長さ方向の電極部4の外へ流れ出ようとするはんだが、毛管現象によって第一の溝10aに吸い上がって行き(図示せず)、毛管現象によるはんだの延展防止手段と成り、電極部4の外側にはんだが流れ出て半導体チップ3の表面や側面に付着する事が防止できるので、融解したはんだが流れて不具合品となる事がない半導体装置とすることができる。
According to such a configuration, the solder melted by heat when the electrode part 4 and the frame II10 are solder-connected at the time of assembly as a semiconductor device is moved outward in the width direction of the frame II10 due to the wetting phenomenon and the capillary phenomenon. Wet up (not shown) from the surface of the electrode part 4 positioned to the side surface of the frame II10 (not shown) and flow out of the electrode part 4 in the longitudinal direction of the frame II10 through the gap between the frame II10 and the electrode part 4 The solder to be sucked up into the
また、図1(c)は、上述の第一の溝10aを設けたフレームII10であるが、図1(d)に示す様にフレームII10の一端に設けた第一の溝10aと、フレームII10の他端にも同様に第二の溝10bを設ける事によって左右対称形状とすることが可能なので、組み立ての際の部品供給としてフレームII10の両端方向性を考慮する必要が無くなり、更に、フレームII10を表裏同形状とすることによって組み立ての際の部品供給としてフレームII10の両端表裏方向性を考慮する必要が無くなるので、製造の簡略化や高効率化が可能な半導体装置とすることができる。
1C shows the frame II10 provided with the
尚、第1の実施形態の第一先端部7aおよび第二先端部7bに、第2の実施形態の第一の溝10aおよび第二の溝10bを形成して、第1の実施形態と第2の実施形態とのはんだ流れ止め手段を併用しても良い。
Note that the
面実装タイプの半導体パッケージとして有用であり、特に内部配線に大電流が可能な半導体装置に適している。 It is useful as a surface-mounting type semiconductor package, and is particularly suitable for a semiconductor device capable of large current in internal wiring.
1 第一リード端子
2 第二リード端子
3 半導体チップ
4 電極部
5 第一のはんだ
6 第二のはんだ
7 フレーム
7a 第一先端部
7b 第二先端部
8 モールド部
10 フレームII
10a 第一の溝
10b 第二の溝
DESCRIPTION OF
10a
Claims (3)
前記フレームは、前記電極部側の端部である第一先端部が、当該第一先端部を除く中央部分より下段となるように、クランク状に段差を設けてフォーミングされ、
前記電極部の表面より小さく形成された前記第一先端部の第二主面が、前記電極部の表面に収まるように、前記電極部に固定されており、
前記第一先端部の第二主面と前記電極部とがロー付けされた際における、前記第一先端部の第二主面を取り囲む前記第一先端部の側面への前記ロー材の毛管現象によって、前記ロー材が前記第一先端部の側面に濡れ上がっている、半導体装置。 The semiconductor chip is electrically connected to the upper first main surface of the first lead terminal formed by providing a step in a crank shape by brazing, and the first main surface of the semiconductor chip has an electrode portion, A second lead terminal formed with a step in a crank shape is opposed to the first lead terminal, and a lower second main surface of the first lead terminal and a lower second main surface of the second lead terminal are Provided on the same surface, having a brazing material on the electrode portion and the upper first main surface of the second lead terminal, and connecting the electrode portion and the upper first main surface of the second lead terminal with the brazing material. A mold that is electrically connected through a connected frame and includes a part of the semiconductor chip, the electrode portion, the brazing material, the frame, the first lead terminal, and the second lead terminal. In a semiconductor device comprising a portion,
The frame is formed with a step in a crank shape so that the first tip portion, which is the end portion on the electrode portion side, is lower than the central portion excluding the first tip portion,
The second main surface of the first tip portion formed smaller than the surface of the electrode portion is fixed to the electrode portion so as to fit on the surface of the electrode portion,
Capillary phenomenon of the brazing material to the side surface of the first tip portion surrounding the second main surface of the first tip portion when the second main surface of the first tip portion and the electrode portion are brazed Thus, the brazing material is wetted on the side surface of the first tip portion.
前記第一先端部と、前記第二先端部とは、前記第一先端部の中心と前記第二先端部の中心とを結ぶ線に直交する線分を軸に対称の形態を有する、請求項2に記載の半導体装置。 The frame is formed with a step in a crank shape so that a second tip portion that is an end portion on the second lead terminal side is lower than the center portion.
The first tip portion and the second tip portion are symmetrical with respect to a line segment orthogonal to a line connecting the center of the first tip portion and the center of the second tip portion. 2. The semiconductor device according to 2.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015170787A (en) * | 2014-03-10 | 2015-09-28 | 新電元工業株式会社 | Resin-sealed semiconductor device |
WO2020071185A1 (en) * | 2018-10-02 | 2020-04-09 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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2010
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015170787A (en) * | 2014-03-10 | 2015-09-28 | 新電元工業株式会社 | Resin-sealed semiconductor device |
WO2020071185A1 (en) * | 2018-10-02 | 2020-04-09 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
JPWO2020071185A1 (en) * | 2018-10-02 | 2021-09-02 | ローム株式会社 | Semiconductor devices and manufacturing methods for semiconductor devices |
US11721612B2 (en) | 2018-10-02 | 2023-08-08 | Rohm Co., Ltd. | Semiconductor device with connecting member for electrode and method of manufacturing |
JP7326314B2 (en) | 2018-10-02 | 2023-08-15 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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