JP2010211349A - Semiconductor integrated circuit and memory access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a memory access control method for efficiently controlling access through the transmission path of a split transaction to an external memory. <P>SOLUTION: An ASIC 4 temporarily stores the write data of write access to a main memory 3 received from a DMAC connected to an external interface in a write packet buffer, and a read request monitoring circuit determines the transmission efficiency of a PCIe bus 5 based on a prescribed transmission efficiency determination reference, and divides write data stored in the write packet buffer into prescribed division data amounts based on the determination result, and transmits the write data through the PCIe bus 5 to a main memory 3. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a memory access control method, and more particularly, to a semiconductor integrated circuit and a memory access control method for efficiently controlling a request for access to an external memory via a split transaction transmission line.

  In recent years, requests and responses have been separated, and high-speed split transaction buses such as PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe) that can issue the next request without waiting for a response have come to be used. It is coming.

  On the other hand, in an image processing apparatus such as a printer, a copying apparatus, a composite apparatus, or a computer, an ASIC (Application Specific Integrated Circuit) that performs interface processing with the outside, which is a semiconductor integrated circuit, is mounted, a network, and a USB (Universal Serial Bus). ) Interfacing with scanners, plotters, computers and other external devices using an ASIC, storing external data in the main memory, and reading out data stored in the main memory and outputting it to the outside Is starting to do.

  That is, the ASIC exchanges data with a network, a scanner, a plotter, etc., and exchanges data with a main memory connected via a PCIe end point by DMA (Direct Memory Access). .

  For example, as an ASIC installed in an image forming apparatus, an I / O function for controlling a network I / F such as an Ethernet (registered trademark) I / F or a USB (Universal Serial Bus) I / F is installed. There is an ASIC, and such an ASIC includes network read DMAC (Direct Memory Access Controller: DMA controller) and write DMAC, USB read DMAC and write DMAC, arbiter, PCIe endpoint circuit, etc. Data transmission / reception with USB data is performed as follows.

  In other words, in transmission to the network, the ASIC transfers the transmission data stored in the main memory to the Ethernet I / F from the PCIe endpoint circuit via the arbiter by the read DMAC, and the Ethernet I / F. F transmits data on the network. In receiving data from the network, the data received from the network by the Ethernet I / F is written to the main memory by the write DMAC via the arbiter.

  Similarly, in transmission / reception of data to / from the USB, the ASIC reads data from the main memory and sends it to the USB I / F, and the USB I / F transmits data to the USB. Further, the data from the USB I / F is written to the main memory by the write DMAC via the arbiter.

  That is, the ASIC has a built-in arbiter and arbitrates memory access for reading and writing data to and from the memory via the PCIe bus by the DMAC.

  In accessing the main memory using such an arbiter, a request output from the arbiter is exchanged with the main memory via the PCIe bus interface, and transmission and reception are performed in full duplex.

  In other words, PCIe is read and written in split transactions. That is, as shown in FIG. 11, in the write transaction, the write data (WD) is transmitted following the write command (WC) in the Tx transmission path in the write transaction, and the read command is transmitted in the Tx transmission path in the read transaction. After (RC) is transmitted, read data (RD) is received on the Rx transmission line as a response.

  However, the conventional arbiter only processes access requests in the order determined by the prescribed fixed priority method or the round robin method. In the case of an ASIC, overflow of received data from the network, USB, etc. In order to avoid this, the priority of the write DMAC, which is the reception operation, is set high as the priority in the arbiter and is processed in round robin. On the other hand, the data transfer size between the DMAC and the arbiter is 128 bytes, and the amount of data exchanged in one transaction is 128 bytes. The data transfer size between the arbiter and the PCIe end point (PCIe bus I / F) is 128 bytes, and 128-byte packets are transmitted and received on the PCIe bus.

  For example, when the ASIC includes a plurality of DMACs that transfer data between the external I / F of a device such as a network or USB and the main memory, when the plurality of DMACs operate in parallel, as shown in FIG. When the write access is continuously received from the arbiter, the issue of the read command is postponed, and the balance between the efficiency of the Tx transmission line and the efficiency of the Rx transmission line is deteriorated. In particular, since the read command cannot be transmitted unless 128-byte write data is transmitted, the transmission of the read command to the device is delayed and the efficiency on the Rx transmission path is deteriorated.

  As a result, when data is transmitted from an external device I / F such as an Ethernet I / F or USB I / F to the external device, transmission data read from the main memory is delayed, and transmission underrun occurs. There is a problem that performance is degraded due to re-transmission.

  In addition, since the PCIe bus is a split transaction bus, the efficiency of the Tx transmission path and the Rx transmission path deteriorates only by arbitrating access from a plurality of DMACs by the arbiter, and arbitration considering read access and write access is performed. Necessary. For example, if the size of the write packet transmitted at a time is increased in order to increase the efficiency of the Tx transmission path, the efficiency of the Rx transmission path is reduced as described above, and the latency (delay time) of the read packet is increased. . Conversely, if the size of the write packet transmitted at a time is reduced in order to increase the efficiency of the Rx transmission line, the number of write commands added to the write packet increases, and the efficiency of the Tx transmission line decreases.

  Conventionally, the write command from the arbiter is stored in the buffer, and when the read command is received while the write command is stored, the read command is passed to the PCIe interface before the already stored write command, so that the transmission path And a technique for improving the utilization efficiency of the receiving path has been proposed (see Patent Document 1).

  However, in the prior art described in the above publication, when a write command from the arbiter is stored in a buffer and a read command is received while the write command is being stored, the read command is read before the already stored write command. Since the command is passed to the PCIe interface, the timing control when the acceptance of the write command and the acceptance of the read command occurs simultaneously and the timing control when the acceptance of the read command occurs simultaneously with the completion of acceptance of the write command processing are complicated. As a result, the circuit scale increases and the cost may increase.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit and a memory access control method that can improve the throughput by improving the utilization efficiency of the split transaction transmission line with a simple configuration.

  In order to achieve the above object, the present invention temporarily stores write data for write access to an external memory received from a DMA controller connected to an external interface in a data storage means, and sets the transmission efficiency of the transmission path to a predetermined value. The write data stored in the data storage means is divided into a predetermined amount of divided data based on the determination result and transmitted to the memory via the transmission path. It is characterized by that.

  Further, the present invention monitors a request time interval of a read request received from the DMA controller and output to the transmission line side, and sets a predetermined reference time interval in which the request time interval is set in advance as the transmission efficiency criterion. The transmission efficiency of the transmission path may be determined as follows.

  Furthermore, the present invention is characterized in that the operation state of the external interface is acquired, and the transmission state of the transmission path is determined using the operation state as a criterion for determining the transmission efficiency based on a predetermined operation state set in advance. Also good.

  According to the present invention, since the divided transmission of write data from the DMA controller is controlled according to the transmission efficiency of the transaction transmission path, the utilization efficiency of the transmission path can be improved with a simple configuration. The throughput of the processing used can be improved.

1 is a block diagram of a main part of an image forming apparatus to which an embodiment of the present invention is applied. Arbiter block diagram The figure which shows the example of a state of a PCIe bus | bath when several DMAC operate | moves in parallel. The figure which shows the example of a state of the PCIe bus | bath of the state in which the read request time interval became long. The figure which shows the example of a state of a PCIe bus | bath when write data is divided | segmented into a division size and transmitted. The block block diagram of the image forming apparatus in the case of carrying out the division | segmentation control of a packet based on the communication mode of an external interface. The flowchart which shows the packet division | segmentation control processing based on the communication mode of an external interface. FIG. 3 is a block diagram of an image forming apparatus when a write packet is divided and controlled based on an operation state of an external interface. The flowchart which shows the packet division | segmentation control processing based on the operation state of an external interface. 1 is a block configuration diagram of an image forming apparatus equipped with an image processing ASIC. Explanatory drawing of the write and read transaction in PCIe. The figure which shows the state in which the balance of the efficiency of the transmission transmission path in PCIe and the efficiency of a receiving transmission path deteriorated.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 10 are diagrams showing an embodiment of a semiconductor integrated circuit and a memory access control method according to the present invention. FIG. 1 is an application of an embodiment of the semiconductor integrated circuit and the memory access control method according to the present invention. 2 is a block diagram of the main part of the image forming apparatus 1. FIG.

  In FIG. 1, an image forming apparatus 1 is, for example, a printer, a composite device, or the like, and includes a CPU (Central Processing Unit) chip set 2, a main memory (external memory) 3, and an ASIC (Application Specific Integrated Circuit) as a semiconductor integrated circuit. 4 etc. The ASIC 4 and the MCH (Memory Controller Hub) built in the CPU chipset 2 are connected by a PCIe bus 5 which is a transmission path for split transactions.

  The ASIC 4 includes an Ethernet I / F 11 and a USB I / F 12 that perform I / F (interface) for connection with an external device, a read DMAC (Direct Memory Access Controller: DMA controller) 13r for the Ethernet I / F 11, a write DMAC 13w, and a USB. The I / F 12 includes two read DMACs 14r and 15r, write DMACs 14w and 15w, an arbiter 16, a PCIe end point 17 serving as a PCIe interface, and the like, and performs interface processing with an external device.

  The arbiter 16 arbitrates write requests and read requests from the DMACs 13r, 13w, 14r, 14w, 15r, and 15w and passes them to the PCIe end point 17. The PCIe end point 17 accesses the main memory 3 through the PCIe bus 5 and the CPU chipset 2 via the PCIe bus 5.

  In the data transmission to the network, the ASIC 4 transfers the transmission data on the main memory 3 from the PCIe end point 17 to the Ethernet I / F 11 via the arbiter 16 by the read DMAC 13r, and by the Ethernet I / F 11 In receiving data from the network (Ethernet) and receiving data from the network, the data received by the Ethernet I / F 11 is written to the main memory 3 via the arbiter 16 by the write DMAC 13w. Similarly, in outputting data to the USB, the ASIC 4 transfers the output data stored in the main memory 3 from the PCIe end point 17 to the USB I / F 12 via the arbiter 16 by the read DMACs 14r and 15r. The data is transferred and output to the USB by the USB I / F 12, and when receiving data from the USB, the data received by the USB I / F 12 is written to the main memory 3 via the arbiter 16 by the write DMACs 14w and 15w. To do.

  When accessing the main memory 3 through the CPU chip set 2 using the PCIe bus 5, a request output from the arbiter 16 is exchanged with the main memory 3 via the PCIe end point 17. .

  As described above, the arbiter 16 arbitrates the read command from the read DMACs 13r, 14r, and 15r and the write command from the write DMACs 13w, 14w, and 15w and passes them to the PCIe end point 17, but the arbiter 16 of this embodiment As shown in FIG. 2, a write packet buffer 21, a write packet size control circuit 22, a read request monitoring circuit 23, a register 24, and the like are provided.

  The read request monitoring circuit (determination means) 23 monitors the time interval tr of the read request transmitted from the arbiter 16, compares the read request time interval tr with the efficiency decrease determination time interval (transmission efficiency determination criterion) tp, If the read request time interval tr (long) exceeding the efficiency decrease determination time interval tp continues, it is determined that the efficiency (transmission efficiency) of the read transaction has decreased, and the write packet size control circuit 22 is notified of a decrease in transmission efficiency. I do. The register 24 sets and holds the efficiency reduction determination time interval tp and the write packet division size described later. Further, the read request monitoring circuit 23 acquires the operation state from each of the external interfaces Ethernet I / F 11 and USB I / F 12 as a transmission efficiency determination criterion, and determines whether there is a decrease in transmission efficiency.

  The write packet buffer (data storage unit) 21 temporarily stores the write data received from the write DMACs 13w, 14w, and 15.

  When the write packet size control circuit (divided transmission control means) 22 receives the transmission efficiency decrease notification from the read request monitoring circuit 23, the write packet size control circuit (divided transmission control means) 22 converts the write data stored in the write packet buffer 21 into the divided size held in the register 24 Is divided into divided write packets and transmitted to the PCIe end point 17.

  The ASIC 4 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), and a DVD (Digital Video). A memory access control program for executing the memory access control method of the present invention recorded on a computer-readable recording medium such as a disk (SD), a secure digital (SD) card, or a magneto-optical disc (MO). It is constructed as a semiconductor integrated circuit that executes a memory access control method for improving the utilization efficiency of the PCIe bus 5 described later by being introduced into a ROM (not shown). This memory access control program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. And can be distributed.

  Next, the operation of this embodiment will be described. In the ASIC 4 of this embodiment, the arbiter 16 determines the transmission efficiency of the PCIe bus 5, divides the write data and performs write access to the main memory 3, thereby improving the transmission efficiency of the PCIe bus 5.

  That is, the ASIC 4 includes a read DMAC 13r and a write DMAC 13w for the Ethernet I / F 11, and two read DMACs 14r and 15r and two write DMACs 14w and 15w for the USB I / F 12, and these DMACs 13r, 13w, 14r, 14w, 15r, and 15w operate in parallel. When these DMACs 13r, 13w, 14r, 14w, 15r, and 15w operate in parallel, the arbiter 16 adjusts the access from each of the DMACs 13r, 13w, 14r, 14w, 15r, and 15w and passes it to the PCIe end point 17.

  At this time, as shown in FIG. 3, the PCIe bus 5 has a write command WC1, a write data WD1, a read command RC1, a write command WC2, a write data WD2, a read command RC2, and a write command in the Tx transmission path on the write side. WC3, write data WD3... Are accessed, and in the read Rx transmission path, read data RD1 by read command RC1 and read data RD2 by read command RC2 are executed.

  However, since the PCIe bus 5 is a split transaction bus as described above, the arbiter 16 simply arbitrates access from the plurality of DMACs 13r, 13w, 14r, 14w, 15r, and 15w, and the Tx transmission line and the Rx The efficiency of the transmission line becomes worse.

  That is, the read request time interval tr is variable, and becomes larger (longer) depending on the number of DMACs 13r, 13w, 14r, 14w, 15r, and 15w connected to the arbiter 16, the request issuing capability, and the operation of the image forming apparatus 1. Or smaller (shorter). For example, when one of the read DMACs 13r, 14r, and 15r, for example, the read DMAC 13r and the plurality of write DMACs 13w, 14w, and 15w are operated in parallel, the arbiter 16 performs a plurality of write DMACs 13w during a read request from the read DMAC 13r. , 14w, and 15w are interrupted, and the read request time interval tr increases. Further, when the operation of the write DMACs 13w, 14w, and 15w is one, the read request and the write request are processed alternately, and the read request time interval tr becomes substantially equal to the transfer time of the write packet size.

  Therefore, the ASIC 4 of this embodiment determines the transmission efficiency of the PCIe bus 5 based on the read request time interval tr and the operation state of the external interface, and reads the read data from the DMACs 13r, 13w, 14r, 14w, 15r, and 15w. Divided transmission is performed in which the data is divided into a predetermined divided data amount and transmitted to the main memory 3 via the PCIe bus 5.

  That is, the arbiter 16 temporarily stores the write data received from the write DMACs 13w, 14w, and 15 by the write packet buffer 21, and the read request monitoring circuit 23 measures the read request time interval tr from the arbiter 16, 24 is compared with the efficiency decrease determination time interval tp stored in 24. As shown in FIG. 4, when the read request time interval tr exceeds the efficiency decrease determination time interval tp (long), and the read request time interval tr continues for a time, the read request monitoring circuit 23 increases the efficiency of the read transaction of the PCIe bus 5. It is determined that the transmission rate has decreased, and a transmission efficiency decrease notification is sent to the write packet size control circuit 22.

  The write packet size control circuit 22, when notified of a decrease in transmission efficiency from the read request monitoring circuit 23, sets the write data (write packet) stored in the write packet buffer 21 in the register 24 as shown in FIG. The data is divided according to the divided size and transmitted from the arbiter 16 to the PCIe end point 17.

  Accordingly, the write packet size on the PCIe bus 5 is reduced in accordance with the division size, and the state on the PCIe bus 5 is shortened as shown in FIG. Transfer efficiency is improved.

  Further, the arbiter 6 of the ASIC 4 acquires the operating state of the external interface, determines the transmission efficiency of the transmission path using the predetermined operating state as a transmission efficiency determination criterion, and writes the write packet buffer. It is determined whether the write data stored in 21 is divided and sent to the PCIe end point 17 or not.

  The operation state of the external interface can correspond to various states. First, as shown in FIG. 6, the operation state of the Ethernet interface 11 and the USB I / F 12 is acquired to control the division of the write data. The case will be described.

  In FIG. 6, in the image forming apparatus 1, an Ethernet 31 is connected to the Ethernet I / F 11 of the ASIC 4, and a personal computer (PC) 32 is connected to the USB I / F 12. The arbiter 16 acquires the operation state of the external interface from the Ethernet I / F 11 and the USB I / F 12 which are external interfaces. That is, the Ethernet 31 connected to the Ethernet I / F 11 can operate in the full-duplex mode and the half-duplex mode, and the arbiter 16 can select either the full-duplex mode or the half-duplex mode from the Ethernet I / F 11. Gets working on Further, it acquires whether the Ethernet 31 is a high-speed 1000BASE-T or a relatively low-speed 100BASE-T.

  When the Ethernet 31 is in the half duplex mode, transmission and reception are not performed at the same time. Therefore, a read request is made on the Tx transmission line of the PCIe bus 5 between the PCIe end point 17 and the CPU chipset 2. Although it is not disturbed by the write request and the write data, when the Ethernet 31 is in the full duplex mode, transmission and reception are performed at the same time, so that the balance on the PCIe bus 5 is deteriorated.

  Therefore, as shown in FIG. 7, the read request monitoring circuit 23 fetches the status signal (operation status) of the external interface (step S101), and the Ethernet 31 connected to the Ethernet I / F 11 is in the full duplex mode. Is checked (step S102). If the Ethernet 31 is in the half-duplex mode in step S102, the read request is not obstructed by the write request and the write data in the Tx transmission path of the PCIe bus 5, and the transmission efficiency is reduced in the write packet size control circuit 22. Without performing the notification, the write packet size control circuit 22 transmits the write data (write packet) to the PCIe endpoint 17 without dividing the write data (step S103).

  If the Ethernet 31 is in the full-duplex mode in step S102, the read request monitoring circuit 23 checks whether the communication speed of the Ethernet 31 is a high speed 1000BASE-T (step S104). It is determined that the efficiency of the bus 5 does not deteriorate to the extent that the packet is divided, and the write packet size control circuit 22 does not notify the write packet size control circuit 22 of the transmission efficiency reduction. Is transmitted to the PCIe end point 17 without performing (step S103).

  In step S104, if the communication speed of the Ethernet 31 is 1000BASE-T, which is a high speed, the read request monitoring circuit 23 determines that the read request time interval tr is an efficiency decrease determination time interval tp that is a set value set in the register 24. If the read request time interval tr is equal to or less than the efficiency decrease determination time interval tp, it is determined that the efficiency of the PCIe bus 5 has not decreased, and the transmission efficiency is transmitted to the write packet size control circuit 22. Without performing the decrease notification, the write packet size control circuit 22 transmits the write data (write packet) to the PCIe end point 17 without dividing the write data (step S103).

  In step S105, when the read request time interval tr is longer than the efficiency decrease determination time interval tp, the read request monitoring circuit 23 determines that the efficiency of the PCIe bus 5 is decreasing, and sends it to the write packet size control circuit 22. The write packet size control circuit 22 divides the write data (write packet) division according to the division size set in the register 24 and transmits it to the PCIe endpoint 17 (step S106). ).

  As described above, the ASIC 4 of this embodiment temporarily stores the write data for the write access to the main memory 3 received from the DMAC connected to the external interface in the write packet buffer 21, and the read request monitoring circuit 23 uses the PCIe. The transmission efficiency of the bus 5 is determined based on a predetermined transmission efficiency determination criterion, and the write data stored in the write packet buffer 21 is divided into a predetermined divided data amount based on the determination result via the PCIe bus 5 Is transmitted to the main memory 3.

  Therefore, by dividing the transmission of write data from the DMAC according to the transmission efficiency of the PCIe bus 5, the usage efficiency of the PCIe bus 5 can be improved with a simple configuration, and the throughput of processing using the PCIe bus 5 can be improved. Can be improved.

  In the ASIC 4, the USB I / F 12 may acquire the communication state with the personal computer 32 connected to the USB I / F 12 and perform split transmission of the write data.

  For example, the arbiter 16 acquires information on whether or not the USB I / F 12 is operating to process plotter printing from the personal computer 32 and whether to transmit scanner data to the personal computer 32. , Control whether to divide and transmit the write data from the write DMACs 14w and 15w from the USB I / F 12.

  That is, when plotter printing data is received from the personal computer 32 and the plotter printing operation is being performed using the data, but the data read by the scanner operation is not being transmitted to the personal computer 32, the data is read from the personal computer 32. Since the print data is received, that is, only write processing to the memory 3 by the write DMACs 14w and 15w is performed, the arbiter 16 transmits the write data (write packet) to the PCIe end point 17 without performing division.

  Further, when the plotter printing operation for receiving and printing the plotter print data from the personal computer 32 is being performed and the scanner data is being transmitted to the personal computer 32, the balance on the PCIe bus 5 is poor. Therefore, the arbiter 16 determines to divide the write packet, which is plotter print data from the personal computer 32, divides the write packet into divided sizes, and transmits the divided packet to the PCIe end point 17.

  In this way, the balance on the PCIe bus 5 can be improved, and the plotter processing from the personal computer 32 and the scanner data transmission operation to the personal computer 32 can be performed efficiently.

  Furthermore, as an operation state of the external interface, not only the communication state thereof but also, for example, as shown in FIGS. 8 and 9, the ASIC 40 includes a video-in I / F 41 and a video-out I / F 42 as external interfaces. Write DMAC 43w for video-in I / F 41, four read DMACs 44r to 44C corresponding to C (cyan), M (magenta), Y (yellow), and K (black) plates for video-out I / F 42, 47r is mounted, and the operation state of the scanner 51 and the plotter 52 as external devices connected to the video-in I / F 41 and the video-out I / F 42 is acquired to control the division of the write data. Good.

  That is, the video-in I / F 41 is connected to a scanner 51 that reads an image of a document and inputs the read image data to the video-in I / F 41. The video-out I / F 42 includes an image from the video-out I / F 42. A plotter 52 for forming an image on a sheet based on the data is connected. Then, the write DMAC 43 w issues a write command to the main memory 3 to the arbiter 16, and passes the image data captured by the video-in I / F 41 from the scanner 51 to the arbiter 16 as write data. The read DMACs 44 r to 47 r issue a read command to the arbiter 16, take in the image data of the main memory 3 as read data, pass it to the video-out I / F 42, and the video-out I / F 42 outputs it to the plotter 52.

  The arbiter 16 acquires the operation state signal of the plotter 52 from the video-out I / F 42 and the operation state signal of the scanner 51 from the video-in I / F 41 to control the division of the write data.

  That is, as shown in FIG. 9, the read request monitoring circuit 23 of the arbiter 16 takes in the status signals (operation status) of the video-in I / F 41 and the video-out I / F 42 that are external interfaces (step S201), and outputs the video out. It is checked whether the plotter 52 connected to the I / F 42 is operating (step S202). In step S202, when the plotter 52 is not in operation, the read request monitoring circuit 23 does not send a read command to the write packet size control circuit 22 because no read command is generated, and the write packet size control circuit 22 The data (write packet) is transmitted to the PCIe end point 17 without being divided (step S203).

  If the plotter 52 is operating in step S202, the read request monitoring circuit 23 checks whether the scanner 51 connected to the video-in I / F 41 is operating (step S204), and the scanner 51 is operating. If not, a write command is not generated, so the write packet size control circuit 22 does not notify the write packet size control circuit 22 and the write packet size control circuit 22 does not divide the write data (write packet) and sends it to the PCIe end point 17. Transmit (step S203).

  In step S204, if the scanner 51 is operating, that is, if the copy application, the printer application, and the scanner application are in a multi-operation (combined operation), the read request monitoring circuit 23 sets the read request time interval tr in the register 24. It is checked whether it is longer than the efficiency decrease determination time interval tp that is the set value (step S205). If the read request time interval tr is equal to or less than the efficiency decrease determination time interval tp, the efficiency of the PCIe bus 5 is decreased. Therefore, the write packet size control circuit 22 transmits the data to the PCIe end point 17 without dividing the write data (write packet) (step S1). S203).

  In step S205, when the read request time interval tr is longer than the efficiency decrease determination time interval tp, the read request monitoring circuit 23 determines that the efficiency of the PCIe bus 5 is decreasing, and sends it to the write packet size control circuit 22. The write packet size control circuit 22 notifies the transmission efficiency decrease, and divides the division of the write data (write packet) according to the division size set in the register 24 and transmits it to the PCIe endpoint 17 (step S206). ).

  In this way, the write packet can be divided according to the operating state of the external interface to improve the balance between the transmission efficiency of Tx and Rx of the PCIe bus 5 and can operate at a relatively high linear speed. 51 and the plotter 52 can be appropriately operated to improve the throughput.

  Further, as described above, the video-in I / F 41 and the video-out I / F 42 are in operation as applied to the write DMAC 43w for video input from the scanner 51 and the read DMACs 44r to 47r for video output to the plotter 52. Information on whether or not there is obtained is obtained as a criterion for determining transmission efficiency, and it is determined whether or not to split the write packet.

  Therefore, data transfer between the scanner 51 and the plotter 52 and the main memory 3 via the PCIe bus 5 can be performed efficiently, and the operation performance of the scanner 51 and the plotter 52 operating at higher speed can be improved. Throughput can be further improved.

  Further, the present invention can be similarly applied when the semiconductor integrated circuit is an image processing ASIC 60 equipped with an image processing module as shown in FIG. In FIG. 10, the same components as those in FIGS. 1 and 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  10, the image processing ASIC 60 includes an arbiter 16 and a PCIe end point 17 similar to those in FIG. 1, a video in I / F 41, a video out I / F 42, and a write DMAC 43w for the video in I / F 41 similar to those in FIG. In addition to the read DMACs 44r to 47r for the out I / F 42, the compression / decompression unit 61, the rotator 62, the hard disk (HDD) I / F 63, the memory clear 64, the write DMAC 65w for the compression / decompression unit 61, the read DMAC 65r, the rotation A write DMAC 66w, a read DMAC 66r for the storage device 62, a write DMAC 67w for the hard disk I / F, a read DMAC 67r, and a write DMAC 68w for the memory clear 64. The video-in I / F 41 includes a scanner 51, a video-out I / F On F42 , Plotter 52, the hard disk I / F 63, a hard disk (HDD) 71 are connected.

  The image processing ASIC 60 acquires operation state signals from the video-in I / F 41, the video-out I / F 42, and the hard disk I / F 63, which are external interfaces, and controls divided transmission of write data. For example, in the case of a copy operation, the image processing ASIC 60 writes the image data from the scanner 51 to the main memory 3 by the write DMAC 43w via the video-in I / F 41. Next, the image processing ASIC 60 reads the image data stored in the main memory 3 with the read DMAC 65r, sends it to the compression / decompression device 61, encodes it, and writes the code data into the main memory 3 with the write DMAC 65w. Next, the image processing ASIC 60 allows the hard disk I / F 63 to read the code data written in the main memory 3 by the read DMAC 67r in order to enable reprinting without a jam backup or scanning by the document box. Store in the hard disk 71. In the image processing ASIC 60, the hard disk I / F 63 writes the code data stored in the hard disk 71 to the main memory 3 by the write DMAC 75w, reads the code data written to the main memory 3 by the read DMAC 65r, and compresses / decompresses the code data. The image data decoded by the device 61 is written to the main memory 3 again by the write DMAC 65w. Next, the image processing ASIC 60 reads the image data on the main memory 3 by the read DMAC 66r as necessary when the direction of the printing paper is different from the direction of the image data developed on the main memory 3, and the like. The rotation is performed by the rotator 62 so as to match the direction of the paper, and the data is written to the main memory 3 again by the write DMAC 66w. Next, in the image processing ASIC 60, the video-out I / F 42 reads the image data of each CMYK plate on the main memory 3 by the read DMACs 44 r to 47 r and outputs it to the plotter 52. The memory clear 64 is used for initializing a reserved memory area (page memory) when each function writes image data or code data onto the main memory 3.

  In the above processing, the arbiter 16 performs a scanner operation and a printing operation from the document box, that is, a write operation to the main memory 3 of the image data read by the reading operation of the scanner 51 and a print output of the image data of the hard disk 71 by the plotter 52. When the printing operations to be performed in parallel are performed, the main memory 3 is subjected to writing of the image data read by the scanner 51 by the write DMAC 43w for the video-in I / F 41 and the code data by the write DMAC 67w for the hard disk I / F 63. Write, read of code data (small amount) by the read DMAC 65r for the compression / decompressor 61, write of image data by the write DMAC 65w, write and video data for initialization of the page memory area by the write DMAC 68w for the memory clear 64 Each memory access of the image data read occurs due to lead DMAC44r~47r for DOO I / F 42.

  Since such memory access occurs, the number of write requests on the PCIe bus 5 is larger than the number of read requests, the efficiency of the PCIe bus 5 is reduced, and the response to the read request is delayed. As a result, the supply of image data to the video out I / F 42 may not be in time between the line syncs of the plotter 52, and an abnormal image may be generated during printing.

  Therefore, the arbiter 16 acquires an operation state signal indicating whether or not data is being output from the video-out I / F 42 to the plotter 52, and outputs data from the video-out I / F 42 to the plotter 52 and other operations described above. When performing parallel operation, while the read DMACs 44r to 47r of the video out I / F 52 are reading image data, write packets from the other write DMACs 43w, 65w, 66w, 67w, and 68w are divided into packets. The data is divided and transmitted to the PCIe end point 17.

  In this way, the response speed to the read request from the read DMACs 44 r to 47 r of the video out I / F 42 can be increased, and image data can be supplied between the line syncs of the plotter 52. As a result, an abnormal image at the time of printing can be avoided.

  In particular, even in the case of a high-speed image forming apparatus in which the line sync time of the plotter 52 is short, image data can be supplied between the line syncs, and the occurrence of abnormal images during printing can be avoided appropriately. Further, when the plotter 52 is a model in which the distance between the four CMYK drums is physically separated, the start timings by the read DMACs 44r to 47r for each version of the video out I / F 42 do not overlap, and the lead DMACs 44r to A state in which another write request interrupts between 47r read requests is likely to occur, but such a state can be appropriately solved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention can be used for a semiconductor integrated circuit such as an ASIC and a memory access control method for efficiently accessing an external memory via a split transaction transmission line such as PCIe.

1 Image forming apparatus 2 CPU chip set 3 Main memory 4 ASIC
5 PCIe bus 11 Ethernet I / F
12 USB I / F
13r Lead DMAC
13w light DMAC
14r, 15r Read DMAC
14w, 15w light DMAC
16 Arbiter 17 PCIe End Point 21 Write Packet Buffer 22 Write Packet Size Control Circuit 23 Read Request Monitor Circuit 24 Register tr Read Request Time Interval tp Efficiency Decrease Determination Time Interval 31 Ethernet 32 Personal Computer 40 ASIC
41 Video in I / F
42 Video Out I / F
43w light DMAC
44r to 47r Lead DMAC
51 Scanner 52 Plotter 60 Image Processing ASIC
61 Compressor / Expander 62 Rotator 63 Hard Disk (HDD) I / F
64 Memory clear 65w Write DMAC
65r Lead DMAC
66w light DMAC
66r Lead DMAC
67w light DMAC
67r Lead DMAC
68w light DMAC
71 Hard disk (HDD)

JP 2008-250985 A

Claims (5)

In a semiconductor integrated circuit that performs write access and read access from a DMA controller connected to an external interface to an external memory via a split transaction transmission path,
Data storage means for temporarily storing write data for write access to the external memory received from the DMA controller;
Determination means for determining the transmission efficiency of the transmission line based on a predetermined transmission efficiency determination criterion;
A divided transmission control unit that divides the write data stored in the data storage unit based on a determination result of the determination unit into a predetermined divided data amount and transmits the divided data to the external memory via the transmission path;
A semiconductor integrated circuit comprising:   The determination unit monitors a request time interval of a read request received from the DMA controller and output to the transmission line side, and a predetermined reference time interval in which the request time interval is preset is used as the transmission efficiency determination criterion. 2. The semiconductor integrated circuit according to claim 1, wherein the transmission efficiency of the transmission path is determined.   The determination unit acquires an operation state of the external interface, and determines the transmission efficiency of the transmission line using the operation state as a reference for setting the transmission efficiency as a predetermined operation state. The semiconductor integrated circuit according to claim 1 or 2.   The semiconductor integrated circuit includes one or more of a network interface, a scanner interface, a plotter interface, and an external memory interface as the external interface, and the determination means includes a communication mode of the network interface, the scanner interface 4. The semiconductor integrated circuit according to claim 3, wherein a state indicating whether the plotter interface is operating or not is acquired as the operating state. In a memory access control method in a semiconductor integrated circuit in which write access and read access from a DMA controller connected to an external interface to an external memory are performed via a split transaction transmission path,
A data storage processing step for temporarily storing write data of write access to the external memory received from the DMA controller in a data storage unit;
A determination processing step of determining the transmission efficiency of the transmission path based on a predetermined transmission efficiency determination criterion;
A divided transmission control processing step of dividing the write data stored in the data storage means into a predetermined divided data amount based on the determination result in the determination processing step and transmitting the write data to the external memory via the transmission path; ,
A memory access control method comprising:

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