JP2010205871A - Electrostatic protection circuit, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect static electricity applied between terminals striding over an electrical power system by ensuring sufficient discharging ability while compressing a packaging area by combining semiconductor layers with one another in a semiconductor device including a plurality of electrical power systems. <P>SOLUTION: The semiconductor device includes: a first diode portion having a first P-type semiconductor layer, a second N-type semiconductor layer disposed within the first semiconductor layer, and a third N-type semiconductor layer surrounding the first semiconductor layer; and a second diode portion having a fourth P-type semiconductor layer, a fifth N-type semiconductor layer disposed within the fourth semiconductor layer, and a sixth N-type semiconductor layer surrounding the fourth semiconductor layer. In connection among the semiconductor layers, the first and fifth semiconductor layers are connected with a first reference voltage, the second and fourth semiconductor layers are connected with a second reference voltage, the third semiconductor layer is connected with a second supply voltage, and the sixth semiconductor layer is connected with a first supply voltage. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an electrostatic protection circuit and a semiconductor device.

  The semiconductor device disclosed in Patent Document 1 includes clamp circuits [1] to [3] for the purpose of preventing electrostatic breakdown that occurs between a plurality of power supply systems. The clamp circuit [1] clamps between the power supply voltage Vdd1 and the reference voltage Vss2. The clamp circuit [2] clamps between the power supply voltage Vdd2 and the reference voltage Vss1. The clamp circuit [3] clamps between the reference voltage Vss1 and the reference voltage Vss2. The clamp circuits [1] to [3] are configured with, for example, diodes.

  Further, Patent Document 2 is disclosed as another related document.

JP 2006-100606 A JP 2004-146440 A

  However, in the related art, when a clamp circuit for protecting against electrostatic breakdown is formed of a diode, there is no disclosure or suggestion about the device structure of the diode.

  The electrostatic protection circuit needs to efficiently discharge static electricity applied to the terminals in a short time. Therefore, the discharge capability of the discharge current path is important. This is because when the discharge capability of the current path is insufficient, the voltage generated by applying static electricity may exceed the withstand voltage of the protected circuit. If the applied voltage exceeds the withstand voltage of the protected circuit, there is a risk of causing irreparable damage such as dielectric breakdown or deterioration of the withstand voltage characteristics inside the semiconductor device.

  In order to prevent such damage and realize a sufficient electrostatic protection function, the diode constituting the electrostatic protection circuit needs to have a device structure in which the discharge capability of the discharge path is sufficiently ensured.

  In the background art that does not disclose or suggest the device structure of the diode, it is impossible to provide a suitable diode configured in an electrostatic protection circuit.

  The electrostatic protection circuit disclosed in the present application includes a first power supply system including a first power supply voltage and a first reference voltage, and a second power supply system including a second power supply voltage and a second reference voltage. The electrostatic protection circuit is mounted on a semiconductor device, and includes a P-type first semiconductor layer, an N-type second semiconductor layer disposed in the first semiconductor layer, and a first semiconductor. A first diode portion comprising an N-type third semiconductor layer surrounding the layer, a P-type fourth semiconductor layer, an N-type fifth semiconductor layer disposed in the fourth semiconductor layer, And a second diode portion including an N-type sixth semiconductor layer surrounding the fourth semiconductor layer. As for the connection between the semiconductor layers, the first semiconductor layer and the fifth semiconductor layer are connected to the first reference voltage, the second semiconductor layer and the fourth semiconductor layer are connected to the second reference voltage, The third semiconductor layer is connected to the second power supply voltage, and the sixth semiconductor layer is connected to the first power supply voltage.

  According to the electrostatic protection circuit disclosed in the present application, the diode constituting the electrostatic protection circuit can be disposed with the mounting area compressed while securing the discharge capability.

1 is a configuration example of a semiconductor device including an electrostatic protection circuit of an embodiment. It is a cross-sectional structure of the electrostatic protection circuit of the embodiment. It is a top view of the 1st and 2nd diode part which comprises an electrostatic protection circuit. It is a top view (1st modification) of the 1st and 2nd diode part which comprises an electrostatic protection circuit. It is sectional structure (2nd modification) of the electrostatic protection circuit of embodiment.

  FIG. 1 is a configuration example of a semiconductor device having a first power supply system 1 and a second power supply system 2. Each of the first power supply system 1 and the second power supply system 2 includes a power supply voltage and a reference voltage individually. That is, the first power supply system 1 includes the first power supply voltage VDD1 and the first reference voltage VSS1, and the second power supply system 2 includes the second power supply voltage VDD2 and the second reference voltage VSS2. It consists of

  As for electrostatic protection for a semiconductor device including a plurality of power supply systems 1 and 2 shown in FIG. 1, a protection circuit is provided between terminals belonging to each of the power supply systems 1 and 2, and an electrostatic protection circuit 3 is provided between terminals straddling the power supply system. is required.

  The electrostatic protection circuit 3 includes four types of diode elements for each combination between terminals across the power supply systems 1 and 2.

  The diode element D11 and the diode element D21 are connected in opposite directions between the first reference voltage VSS1 of the first power supply system 1 and the second reference voltage VSS2 of the second power supply system 2. Yes. Thereby, a discharge path of static electricity applied between the first reference voltage VSS1 and the second reference voltage VSS2 is ensured.

  In addition, between the first reference voltage VSS1 of the first power supply system 1 and the second power supply voltage VDD2 of the second power supply system 2, the first reference voltage VSS1 is used as an anode terminal and the second power supply A diode element D12 having the voltage VDD2 as a cathode terminal is connected. As a result, a positive voltage electrostatic discharge path applied to the first reference voltage VSS1 with respect to the second power supply voltage VDD2 is secured. In addition, regarding the negative static electricity applied to the first reference voltage VSS1 with respect to the second power supply voltage VDD2, the second reference is supplied from the second power supply voltage VDD2 via an electrostatic protection circuit (not shown). The voltage VSS2 is discharged, and a discharge path from the second reference voltage VSS2 through the diode element D21 is secured.

  In addition, between the second reference voltage VSS2 of the second power supply system 2 and the first power supply voltage VDD1 of the first power supply system 1, the second reference voltage VSS2 is used as an anode terminal and the first power supply voltage is set. A diode element D22 having VDD1 as a cathode terminal is connected. As a result, an electrostatic discharge path of positive voltage applied to the second reference voltage VSS2 with respect to the first power supply voltage VDD1 is secured. Regarding the negative static electricity applied to the second reference voltage VSS2 with respect to the first power supply voltage VDD1, the first reference is supplied from the first power supply voltage VDD1 via an electrostatic protection circuit (not shown). The voltage VSS1 is discharged, and a discharge path from the first reference voltage VSS1 through the diode element D11 is secured.

  By the electrostatic protection circuit 3, the first power supply voltage VDD1 and the first reference voltage VSS1 provided in the first power supply system 1, and the second power supply voltage VDD2 and the second reference provided in the second power supply system 2 are provided. For any combination with voltage VSS2, a discharge path for the application of static electricity is ensured. In a semiconductor device including two power supply systems, a discharge path is secured against static electricity applied between terminals straddling the power supply system.

  FIG. 2 shows a configuration example of a device structure in a semiconductor device that realizes the electrostatic protection circuit 3. The device structure shown in FIG. 2 is conveniently formed on a P-type substrate. This is because the electrostatic protection circuit 3 can be arranged with high area efficiency by being formed on the P-type substrate.

  The four types of diode elements D11, D12, D21, and D22 are configured to be separated into two diode portions for each connection destination of the anode terminal. The first diode portion D1 includes diode elements D11 and D12. The second diode portion D2 includes diode elements D21 and D22. In order to configure the first and second diode portions D1 and D2 on the P-type substrate, it is necessary to form a region electrically insulated from the P-type substrate and to dispose the diode element in the region. It is the N-type semiconductor layer that insulates this internal region from the P-type substrate. N well regions 14, 15, 24 and 25 shown in FIG. 2 correspond to this. The N well regions 14, 15, 24, and 25 are N type semiconductor layers that insulate the internal regions where the diode elements D11, D12, D21, and D22 are disposed from the P type substrate, and the cathode terminals of the diode elements D12 and D22. It can also be used as an N-type semiconductor layer.

  The first diode part D1 and the second diode part D2 have the same device structure. The general procedure is as follows. First, a deep N well region 14 (24) is formed on a P-type substrate. Next, an N well region 15 (25) is formed which overlaps with the deep N well region 14 (24) at the lower end and electrically insulates the region directly above the deep N well region 14 (24) from the surrounding P-type substrate region. To do. In addition, a P well region 11 (21) is formed in an inner region surrounded by the deep N well region 14 (24) and the N well region 15 (25). A P-type diffusion region 12 (22) and an N-type diffusion region 13 (23) are formed inside the P well region 11 (21). Here, the P-type diffusion region 12 (22) is formed with the N-type diffusion region 13 (23) interposed therebetween. An N-type diffusion region 16 (26) is formed in the N well region 15 (25). Here, the P-type diffusion region 12 (22), the N-type diffusion regions 13 (23), and 16 (26) are arranged for ohmic connection with the metal wiring layer.

  The P-type diffusion region 12 and the N-type diffusion region 23 are connected to the first reference voltage VSS1. The N-type diffusion region 13 and the P-type diffusion region 22 are connected to the second reference voltage VSS2. The N-type diffusion region 16 is connected to the second power supply voltage VDD2. The N-type diffusion region 26 is connected to the first power supply voltage VDD1.

  Accordingly, the diode element D11 having the P-type diffusion region 12 as an anode terminal and the N-type diffusion region 13 as a cathode terminal is connected to the first reference voltage VSS1 as an anode terminal and the second reference voltage VSS2 as a cathode terminal. . The diode element D21 having the P-type diffusion region 22 as an anode terminal and the N-type diffusion region 23 as a cathode terminal is connected to the second reference voltage VSS2 as an anode terminal and the first reference voltage VSS1 as a cathode terminal.

  In addition, the diode element D12 having the P-type diffusion region 12 as an anode terminal and the N-well region 15 and the N-type diffusion region 16 as a cathode terminal, the first reference voltage VSS1 as an anode terminal, and the second power supply voltage VDD2 as a cathode terminal. Connected as Further, the diode element D22 having the P-type diffusion region 22 as an anode terminal and the N-well region 25 and the N-type diffusion region 26 as a cathode terminal, the second reference voltage VSS2 as an anode terminal, and the first power supply voltage VDD1 as a cathode terminal. Connected as

  The first diode part D1 is provided with diode elements D11 and D12, and the second diode part D2 is provided with diode elements D21 and D22.

  FIG. 3 is a plan view of the first and second diode portions D1 and D2. A P-type diffusion region 12 (22) is disposed surrounding the N-type diffusion region 13 (23). Here, the N type diffusion region 13 (23) and the P type diffusion region 12 (22) are arranged in the P well region 11 (21). An N well region 15 (25) and an N type diffusion region 16 (26) are arranged on the outer periphery of the P type diffusion region 12 (22) so as to surround the P type diffusion region 12 (22).

  Of these semiconductor layers, the N-type diffusion region 13 (23), the P-type diffusion region 12 (22), and the N-type diffusion region 16 (26) have contact layers for ohmic connection with the metal wiring layer. C is provided. Via the contact layer C, an unillustrated metal wiring layer and the N-type diffusion region 13 (23), the P-type diffusion region 12 (22), and the N-type diffusion region 16 (26) are ohmically connected.

  In the plan view of FIG. 3, since the P-type diffusion region 12 (21) is disposed in the P well region 11 (21), the PN junction constituting the diode element D11 (D21) is connected to the P well region 11 ( It exists in the whole of the N-type diffusion region 13 (23) in contact with 21). The same applies to the diode element D12 (D22). In the diode elements D11 (D12) and D12 (D22) constituting the electrostatic protection circuit 3, an allowable current capability of flowing through the elements must be ensured in order to quickly discharge static electricity. Here, the current flowing through the element flows in a concentrated manner in a path having a small resistance value when the current flows.

  In the diode element D11 (D12), the contact layer C of the P-type diffusion region 12 (22) and the contact layer C of the N-type diffusion region 13 (23) are arranged close to each other in the region L1. . The resistance value is small in the region L1, and a main current path is formed in the region L1. The discharge current during static electricity flows around the region L1.

  Similarly, in the diode element D12 (D22), the contact layer C of the P-type diffusion region 12 (22) and the contact layer C of the N-type diffusion region 16 (26) are arranged close to each other in the region L2. Has been. The resistance value is small in the region L2, and a main current path is formed in the region L2. The discharge current during static electricity flows around the region L2.

  Here, since the regions L1 and L2 share the contact layer C of the P-type diffusion region 12 (22), the lengths of both the regions L1 and L2 are substantially the same. The diode element D11 (D21) and the diode element D12 (D22) have substantially the same allowable current capability. Equivalent discharge capacity against static electricity can be ensured.

  In FIG. 4, as a first modification, the planar shape of the diode element is different from that in FIG. The shape of the N-type diffusion region 13 (23) is the same as that in FIG. 3, but the other semiconductor layers are extended by ΔL in the left-right direction. Further, in the extended P-type diffusion region 12a (22a) and the N-type diffusion region 16a (26a), the contact layer C is disposed in the extended region (ΔL).

  Thus, for the diode element D11 (D21), the opposing region L1 between the contact layer C of the P-type diffusion region 12a (22a) and the contact layer C of the N-type diffusion region 13 (23) is the N-type diffusion region 13 ( 23) is limited to the contact layer C and has the same opposing length as in FIG.

  On the other hand, in the diode element D12 (D22), the opposing region L2a between the contact layer C of the P-type diffusion region 12a (22a) and the contact layer C of the N-type diffusion region 13 (23) is extended. Since the contact layer C is newly arranged in the region (ΔL), the facing length of the region L2a is longer by (2 · ΔL) than in the case of FIG.

  In the diode elements D11 (D12) and D12 (D22) constituting the electrostatic protection circuit 3, the opposing region of the contact layer C having a small resistance value of the current path is an important region in order to quickly discharge static electricity. That was mentioned above. In addition to this, the impurity concentration of the P-type semiconductor layer and / or the N-type semiconductor layer constituting the diode elements D11 (D12) and D12 (D22) may be affected. In general, a diode element is known to have a property of showing a current characteristic that rises sharply with respect to a forward bias as the concentration of impurities constituting the PN junction increases.

  In FIG. 4, diode elements D11 (D12) and D12 (D22) have a P-type diffusion region 12a (22a) and a P well region 11 (21) common to both diode elements. On the other hand, the N-type diffusion region is different. The diode element D11 (D12) is an N-type diffusion region 13 (23), and the diode element D12 (D22) is an N-type well region 15 (25) and an N-type diffusion region 16 (26). In this case, when attention is paid to a semiconductor layer that is in direct contact and forms a PN junction, the P-type semiconductor layer is common to the P well region 11 (21). On the other hand, the N-type semiconductor layer is the N-type diffusion region 13 (23) in the diode element D11 (D12), and the N-type well region 15 (25) in the diode element D12 (D22). Comparing the impurity concentration of the N-type diffusion region 13 (23) with the impurity concentration of the N-type well region 15 (25), the latter is considered to have a lower concentration. When this density difference is a significant density difference as a difference in the allowable current capability between the diode elements, it can be considered that the discharge capability of the diode element D12 (D22) is smaller than that of the diode element D11 (D12).

  The first modification shown in FIG. 4 shows a configuration example for eliminating the difference in allowable current capability between diode elements due to the device structure. That is, in order to offset the difference in allowable current capacity per unit facing length, a difference is provided in the facing length. That is, the semiconductor layer excluding the N-type diffusion region 13 (23) has a shape extended by ΔL in the left-right direction, and a contact layer C is provided in the extended region (2 · ΔL), whereby the diode element D11 (D12). The opposing region L2 of the diode element D12 (D22) is made to be the opposing length (2 · ΔL) longer than the opposing region L1. As a result, the allowable current capability of the diode element D12 (D22) is increased and the discharge capability of the diode element D11 (D12) is balanced.

  By expanding and contracting the opposing length to be extended according to the impurity concentration, it is possible to balance the discharge current capability between the diode elements.

  In the second modification shown in FIG. 5, a P well region 31 and a P type diffusion region 32 are provided between the first diode portion D1 and the second diode portion D2. The P-type diffusion region 32 is biased to the third reference voltage VSS3. Thereby, between the 1st diode part D1 and the 2nd diode part D2 can be insulated reliably. It is possible to suppress noise from being mixed during discharge due to application of static electricity. By suppressing the mixing of noise, unexpected operation of a circuit sensitive to noise can be prevented.

  Here, in the first diode portion D1, the P-type diffusion regions 11 and 12 are an example of a P-type first semiconductor layer. The N-type diffusion region 13 is an example of an N-type second semiconductor layer. The deep N well region 14, the N well region 15, and the N type diffusion region 16 are an example of an N type third semiconductor layer.

  In the second diode portion D2, the P-type diffusion regions 21 and 22 are an example of a P-type fourth semiconductor layer. The N-type diffusion region 23 is an example of an N-type fifth semiconductor layer. The deep N well region 24, the N well region 25, and the N type diffusion region 26 are an example of an N type sixth semiconductor layer.

  As described above in detail, according to the present embodiment, the first diode part D1 and the second diode part D2 each include two types of diode elements D11 and D12, and D21 and D22. Of these, the two diode elements D11 and D21 connect the first reference voltage VSS1 in the first power supply system 1 and the second reference voltage VSS2 in the second power supply system 2 in the respective directions. The remaining two diode elements D12 and D22 are connected to each of a direction from the first reference voltage VSS1 to the second power supply voltage VDD2 and a direction from the second reference voltage VSS2 to the first power supply voltage VDD1. The In this case, the N type diffusion regions 13 and 23 are disposed so as to be surrounded by the P well regions 11 and 21 and the P type diffusion regions 12 and 22.

  The P well regions 11 and 21 and the P type diffusion regions 12 and 22 are disposed so as to be surrounded by the deep N well regions 14 and 24, the N well regions 15 and 25, and the N type diffusion regions 16 and 26.

  Further, when a P-type substrate is used as a semiconductor device, deep N well regions 14, 24, N, which are N-type semiconductor layers that insulate internal regions where the diode elements D11, D12, D21, D22 are disposed from the P-type substrate. The well regions 15 and 25 and the N-type diffusion regions 16 and 26 can also be used as cathode terminals of the diode elements D12 and D22.

  In the first diode part D1 and the second diode part D2, each of the two types of diode elements D11, D12, and D21, D22 is arranged in a compact manner using a semiconductor layer in which the arrangement relation is inclusive. . In a semiconductor device provided with two power supply systems of the first power supply system 1 and the second power supply system 2, the electrostatic protection circuit 3 can be disposed with a reduced mounting area while ensuring sufficient discharge capability. .

  Further, as shown in the plan view of FIG. 3, it is important that the discharge capacity of the diode elements D11 (D12) and D12 (D22) constituting the electrostatic protection circuit 3 is small in the resistance value of the current path flowing through the elements. It is. In view of this, in the diode element D11 (D12), the contact layer C of the P-type diffusion region 12 (22) and the contact layer C of the N-type diffusion region 13 (23) are arranged close to each other in the region L1. Has been. As a result, the resistance value is reduced in the region L1, and a main current path is formed. The discharge current during static electricity flows around the region L1. Similarly, the diode elements D12 (D22) are arranged close to each other with the contact layers C facing each other in the region L2. In the region L2, the resistance value becomes small and a main current path is formed. The discharge current during static electricity flows around the region L1.

  From another viewpoint, the allowable current capability of the diode elements D11 (D12) and D12 (D22) constituting the electrostatic protection circuit 3 may be influenced by the impurity concentration of the semiconductor layer forming the PN junction. In view of this, as shown in the plan view of FIG. 4, the discharge capacity between the diode elements can be balanced by adjusting the facing length in which the contact layers face each other according to the impurity concentration.

  According to the above-described embodiment, each of the first diode unit and the second diode unit includes two types of diodes, and the first diode unit and the second diode unit have four types in total. Diodes are provided. Two of these diodes connect the first reference voltage in the first power supply system and the second reference voltage in the second power supply system in each direction. The remaining two diodes are connected to each of a direction from the first reference voltage toward the second power supply voltage and a direction from the second reference voltage toward the first power supply voltage. In this case, the N-type second semiconductor layer is surrounded by the P-type first semiconductor layer, and the P-type first semiconductor layer is further surrounded by the N-type third semiconductor layer. Similarly, the N-type fifth semiconductor layer is surrounded by the P-type fourth semiconductor layer, and the P-type fourth semiconductor layer is also surrounded by the N-type sixth semiconductor layer. The two kinds of diodes provided in the first diode part and the two kinds of diodes provided in the second diode part are each compactly arranged using a semiconductor layer in an inclusion relationship.

  As described above, in the semiconductor device including the two power supply systems, the first power supply system and the second power supply system, the electrostatic protection applied between the terminals straddling the power supply system can be achieved by combining the semiconductor layers. Sufficient discharge capacity can be secured while compressing.

Needless to say, the present invention is not limited to this embodiment, and various improvements and modifications can be made without departing from the spirit of the present application.
For example, in the present embodiment, one N-type diffusion region 13 and 23 is disposed in each of the first and second diode portions D1 and D2, and a P-type / N-type semiconductor layer is disposed so as to surround it. Although the case has been described, the present invention is not limited to this. A plurality of N-type diffusion regions arranged at the center of the first and second diode portions D1 and D2 may be arranged, and accordingly, a plurality of semiconductor layers arranged around the N-type diffusion regions may be arranged. Needless to say.

DESCRIPTION OF SYMBOLS 1 1st power supply system 2 2nd power supply system 3 Static electricity protection circuit 11, 21, 31 P well area | region 12, 12a, 22, 22a, 32 P type diffusion area | region 13, 16, 16a, 23, 26, 26a N type Diffusion region 14, 24 Deep N well region 15, 25 N well region C Contact layer D1 First diode part D2 Second diode part D11, D12, D21, D22 Diode element VDD1 First power supply voltage VDD2 Second power supply Voltage VSS1 First reference voltage VSS2 Second reference voltage VSS3 Third reference voltage

Claims (7)

An electrostatic protection circuit mounted on a semiconductor device including a first power supply system having a first power supply voltage and a first reference voltage, and a second power supply system having a second power supply voltage and a second reference voltage Because
A P-type first semiconductor layer; an N-type second semiconductor layer disposed in the first semiconductor layer; and an N-type third semiconductor layer surrounding the first semiconductor layer. A first diode portion;
A P-type fourth semiconductor layer; an N-type fifth semiconductor layer disposed in the fourth semiconductor layer; and an N-type sixth semiconductor layer surrounding the fourth semiconductor layer. A second diode part;
The first semiconductor layer and the fifth semiconductor layer are connected to the first reference voltage;
The second semiconductor layer and the fourth semiconductor layer are connected to the second reference voltage,
The third semiconductor layer is connected to the second power supply voltage;
6. The electrostatic protection circuit according to claim 6, wherein the sixth semiconductor layer is connected to the first power supply voltage.   The electrostatic protection circuit according to claim 1, wherein the first and fourth semiconductor layers are P-wells, and the third and sixth semiconductor layers are N-wells.   The facing width between the first semiconductor layer and the third semiconductor layer is longer than the facing width between the first semiconductor layer and the second semiconductor layer, and the fourth semiconductor layer and the sixth semiconductor layer are 3. The electrostatic protection circuit according to claim 1, wherein a facing width of the semiconductor layer is longer than a facing width of the fourth semiconductor layer and the fifth semiconductor layer.   The electrostatic protection circuit according to claim 3, wherein the facing width is a length along a surface of the semiconductor device in a region where two semiconductor layers face each other.   5. The electrostatic protection according to claim 4, wherein the facing width is a length of a region in which two contact layers facing each other face a contact layer connecting the semiconductor layer with another layer. 6. circuit. A third reference voltage of a different system from the first and second reference voltages;
6. The at least one of claims 1 to 5, wherein the third reference voltage is connected to a P-type semiconductor layer sandwiched between the first diode portion and the second diode portion. The electrostatic protection circuit described in the section. A first power supply system comprising a first power supply voltage and a first reference voltage;
A second power supply system comprising a second power supply voltage and a second reference voltage;
A direction from the first reference voltage toward the second power supply voltage, a direction from the second reference voltage toward the first power supply voltage, and the first reference voltage and the second reference voltage. With a static electricity protection circuit with a diode in each of the two-way between,
The electrostatic protection circuit is
A P-type first semiconductor layer; an N-type second semiconductor layer disposed in the first semiconductor layer; and an N-type third semiconductor layer surrounding the first semiconductor layer. A first diode portion;
A P-type fourth semiconductor layer; an N-type fifth semiconductor layer disposed in the fourth semiconductor layer; and an N-type sixth semiconductor layer surrounding the fourth semiconductor layer. A second diode part;
The first semiconductor layer and the fifth semiconductor layer are connected to the first reference voltage;
The second semiconductor layer and the fourth semiconductor layer are connected to the second reference voltage,
The third semiconductor layer is connected to the second power supply voltage;
The semiconductor device, wherein the sixth semiconductor layer is connected to the first power supply voltage.

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