JP2000357775A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress electrostatic breakdown of an LSI and prevent bad influence on internal circuits even if a high-voltage input signal is received, by connecting an end of a pair of two diodes series-connected in mutually opposite direction to a pad while the other end is connected to a power source line, wherein the diodes are formed in a well region of an input protection circuit. SOLUTION: Because of the presence of diodes D1, D2 that are reverse biased in both directions between an input pad 5a and a power source line +VDD, an input signal can be received in the voltage range up to the voltage at which either of the diodes breaks down without being influenced by the bilaterally reverse-biased diodes. Clamping of the input signal is not generated with this configuration. In addition, since the diodes D1, D2 are formed in a well region W, the substrate is reverse biased, and the influence on the circuits formed in other regions can be suppressed. Moreover, breakdown of the diodes due to electrostatic breakdown voltage is predominantly taken place in the diodes D1, D2 in the well region W, and adequate electrostatic protection can be prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an operating power supply voltage lower than that of another LSI.
The present invention relates to a semiconductor device including an electronic device including an SI that has an input protection circuit that suppresses electrostatic breakdown of the LSI and that does not adversely affect the operation of an internal circuit when receiving a high-voltage input signal.

[0002]

2. Description of the Related Art In recent years, personal computers (PCs), portable personal computers (notebook PCs), mobile electronic devices, mobile telephones, PHSs, and the like have internal DSPs (Digital Signal Processors) to reduce power consumption. ) And other LSIs operating at about 1.8V
Is built-in. Moreover, in order to ensure long-time operation, a battery used is a lithium battery or the like, and its power supply voltage is +4.0 V or more. In addition, various digital ICs such as a controller have an operating voltage of 3 V to 5 V, and as a result, ICs having a plurality of power supply voltage specifications are mixed therein. On the other hand, in an LSI device, the breakdown voltage against electrostatic breakdown tends to decrease due to the miniaturization of the formed pattern.

Normally, a diode connected to an input terminal or an input / output signal terminal (I / O terminal) of a conventional LSI chip is provided with a diode in a forward direction to a power supply side and a diode in a reverse direction to a ground side. Inserted as a circuit. As a protection circuit against electrostatic breakdown of an open drain output terminal, a circuit in which diodes connected in series in opposite directions are inserted between an output terminal and a power supply line is known in Japanese Patent Application Laid-Open No. 5-121679.

[0004]

In an LSI operating at a power supply of about 1.8 V, the input terminal voltage may be higher than the power supply voltage in relation to other LSIs. In the circuit, a diode inserted in the forward direction on the power supply side is omitted. This is to prevent the input signal from being clamped by the power supply voltage. In particular, when the power supply voltage is reduced by a battery, the input analog voltage and the like are clamped, so that the above-described diode cannot be inserted. Further, in a semiconductor device (circuit) including an LSI (or IC) for this kind of analog signal processing, a level conversion circuit is usually required on one output side or input side between LSI devices having different operation power supply voltages. Become. However, there is a problem that such insertion of a circuit causes a reduction in an integrated area of a circuit originally required.

Therefore, it is conceivable to insert diodes connected in series in opposite directions between the input terminal and the power supply line as disclosed in Japanese Patent Application Laid-Open No. 5-121679. However, as shown in FIGS. 6A and 6B, since the power supply line is a semiconductor substrate (substrate), an electrostatic breakdown current is generated on the semiconductor substrate side. 1.8V because it flows to other circuits
However, there is a problem that sufficient electrostatic protection cannot be performed in a circuit in which LSIs that operate at the same level are mixed. In addition, FIG.
FIG. 1B is a circuit diagram as an example of the embodiment of FIG.
FIG. 3 is a cross-sectional view of the diode formation region. By the way, in the electrostatic breakdown test, in order to approximate the actual state when the electrostatic breakdown voltage is applied, the power supply line + Vcc
Are tested for each LSI. In a circuit in which an LSI that operates at a power supply of about 1.8 V is mixed as described above, the LSI has a higher electrostatic breakdown voltage than a voltage applied from an input terminal having no diode inserted in the power supply side in the forward direction. And has a problem of being weak to electrostatic breakdown. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and to reduce the operating power supply voltage of other LSIs.
It is an object of the present invention to provide a semiconductor device having an input protection circuit that suppresses electrostatic breakdown of an LSI and that does not adversely affect the operation of an internal circuit when receiving a high-voltage input signal in an electronic device including I.

[0006]

In order to achieve this object, a semiconductor device according to the present invention comprises a well region formed in a semiconductor substrate and a well region formed in the well region and connected in series in opposite directions to each other. And an input protection circuit having one end connected to a pad and the other end connected to a power supply line.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention having such a configuration, a diode is bidirectionally reverse-biased between an input pad and a power supply line. A bias operation is performed, and an input signal can be received in a range up to a voltage at which any diode breaks down. As a result, no input signal is clamped. In a semiconductor substrate, a power supply line or a ground line is usually taken on a substrate (substrate), so that when a high voltage is applied to an input terminal, a current caused by the circuit is simultaneously supplied to other circuits formed through the substrate. Although the flow may be adversely affected, the formation of the diode in the well region causes the substrate to be in a reverse-biased state, thereby suppressing the influence on circuits formed in other regions. Moreover, the breakdown of the diode due to the electrostatic breakdown voltage is performed preferentially by the diode in the well region. As a result, the operating voltage is different from other circuits, for example,
Even in a circuit in which LSIs operating at about 1.8 V coexist, it is possible to realize a circuit capable of sufficiently protecting the static electricity without providing a level conversion circuit on the input side.

[0008]

1 is an explanatory diagram of a circuit configuration of a semiconductor device to which the semiconductor device of the present invention is applied, FIG. 2 is an explanatory diagram of a manufacturing process thereof, and FIG. 3 is a diagram to which the semiconductor device of the present invention is applied. FIG. 4 is an explanatory diagram of a circuit configuration of another semiconductor device, and FIG. 4 is an explanatory diagram of a manufacturing process thereof. In FIG. 1, reference numeral 1 denotes an LSI having a built-in analog signal processing circuit operating at a power supply voltage of 5V.
Reference numeral 2 denotes a DSP that operates at a power supply voltage of 1.8 V. Reference numeral 3 denotes a power supply circuit IC having a regulator, a DC / DC converter, and the like for supplying power of the respective operating voltages thereto. 4 is a battery.
Here, a signal is serially input from an output terminal 1a of the LSI 1 to an input terminal 2a of the DSP 2, and data of a processing result is returned from the output terminals 2b to 2n of the DSP 2 to another circuit or the LSI 1 via the bus 7. It is. In such a semiconductor device, an input protection circuit 5 is provided at the input terminal 2a of the DSP 2. This input protection circuit 5
Is the pad 5a connected to the input terminal 2a and the input circuit 6
And connected to the connection line 5b with the gate of the n-channel MOS transistor Q. This circuit comprises diodes D1, D2 connected in series in the opposite direction between the connection line 5b and the power supply line + VDD, and a diode D3 inserted in the opposite direction to the connection line 5b and the ground GND. Become. In the connection line 5b, the resistor R provided before the gate of the transistor Q is a protection resistor.

Here, the diodes D1 and D2 are formed inside a well region W in which the cathodes are connected to each other and are in a floating state. Here, since the reverse breakdown voltage of the reverse diode D2 connected to the power supply line + VDD side is about 14V to 15V, its protection breakdown voltage is 1Vf (0.7) plus 15V to
It becomes about 16V. Thus, the output signal from the output terminal 1a of the LSI 1 having the built-in analog signal processing circuit is
Diodes D2 in opposite directions between power supply line VDD
Therefore, even if the voltage of the battery 4 or the like drops, it is not clamped, and LS
It is possible to directly connect the I1 and the DSP2 in and out. The reverse withstand voltage for the power supply line VDD is 15 V
Since it becomes about 16 V, it operates as a protection circuit against a normal electrostatic breakdown voltage. Moreover, these diodes D1 and D2 act on both positive and negative voltages applied between the power supply line and the input terminal. As a result, the input signal is set to L in a state similar to a state where the diode is not connected.
It can be received from SI1. Next, formation of such diodes D1 and D2 will be described. The diode D3 is allocated and formed in another region on the semiconductor substrate. However, since this is the same as the conventional one, the description is omitted. FIG. 2 is a cross-sectional view of a process of forming the diodes D1 and D2. It should be noted that a masking process using a resist or an insulating film, an edging process for the resist or the insulating film, and the like are well known and have been omitted. Hereinafter, only the main part of each step will be described.

As an input protection circuit 5, an N buried layer (B / L) 51 is formed on a P-sub (P-type substrate) semiconductor substrate (hereinafter referred to as a substrate) 50, and is thermally diffused to form a buried layer (B). / L) P ^{+ is} implanted or applied as a P layer forming region around the periphery of 51 (step (A)). Next, a buried layer (B / L) 51 and a P ⁺ layer 51a for element isolation are formed by epitaxial growth (step (B)). Then N ^- N epitaxial layer as (Epi) ^- a region where the region 52 is formed over an oxide layer, and P ⁺ implant or applied to the P layer forming region on P-sub substrate 50, followed by oxidation The film is removed to form an N ⁻ region 52 as an N ⁻ epitaxial layer, and further an element isolation layer (ISO) 52 b outside the N ⁻ region 52.
Are formed respectively. Further, an N ⁺ diffusion separation region 53 is formed as a diffusion separation region inside the outer peripheral side surface of the N ⁻ region 52 with the N buried layer 51 as a bottom surface (step (C)).
This diffusion isolation region 53 becomes a wall on the outer periphery of a circular or rectangular side surface when viewed from a plane with respect to the N ⁻ region 52,
Well region W is formed with the buried layer 51 as a bottom surface,
The layer formed therein is brought into a floating state.
At this time, the outside and the element isolation layer (ISO) 52
b, an epitaxial layer 52 is formed at the same time.

The diffusion isolation region 53 is provided around the side surface of the N ⁻ region 52 corresponding to the width of the N buried layer 51. In this case, the N ⁻ region 52 is When a bipolar transistor is formed, the collector wall (collect
to wall). Next, P ^{+ is} implanted or coated on the surface side of the N ⁻ region 52 and diffused to form P-type base regions 54a and 54b (step (D)). Then, these base regions 54a, 5
4b, an insulating oxide film 56 is provided.
Wiring layers 55a and 55b are formed on the etched portions of insulating oxide film 56 provided on the upper surfaces of a and 54b (step (E)). In this case, the base regions 54a, 54
No emitter region is formed in b.

Thus, N^-The region 52 is a well region W
And it becomes the collector of a bipolar transistor.
Between the base regions 54a and 54b.
Becomes the cathode of each diode, the base is an anode
The diodes D1 and D2 of FIG.
It is formed (see FIG. 5A). Such a diode
Regarding D1 and D2, for example, as shown in FIG.
Connecting wiring layer 55a to pad 5a and connecting line 5b
And the wiring layer 55b is connected to the power supply line + VDD.
Connect to As a result, the pad 5a is connected to the power supply line + VDD.
As the height increases, the well region W (N ^-Area 52) is sub
The voltage is higher than the straight (p-sub) 50
And the substrate (p-sub) 50 side is reverse biased.
State and the diodes D1 and D2 are
It will be in a floating state. At this time,
The side of the base region 54b forming the base D2 is also a reverse via.
State. The breakdown due to reverse bias voltage
Inside the same well region W than the P layer on the straight 50 side
P2 of the base of diode D2
The base region 54 is close to the base region 54a of D1.
a and the contact area with the base region 54a
Because it is small, surrender first. As a result, it will cause electrostatic breakdown
Substrate (p-sub) even when receiving high voltage
It is hard to affect other circuits through 50,
Easily protected. Also, if a high voltage below the breakdown voltage is
Substrate 50 will be in reverse bias
And has little effect on circuits formed in other areas.
No.

FIG. 4 shows an example of diodes D1 and D2 in which anodes are connected to each other and connected in series in opposite directions. The operation is the same as that of FIG. Note that this is an example in which an npn-type transistor is formed in a vertical type and is used as two diodes connected in opposite directions. FIG. 5 shows the steps of manufacturing these diodes. Steps (A) to (C) are the same as those in FIG. In the step (D), N ⁻
P type (P ⁺ ) diffused and formed on the surface side inside the region 52
Is provided. Then, an N ⁺ emitter region 57 is provided by being diffused inside the surface of the P-type base region 54. At the same time, an N ⁺ contact region 53a is also formed at this time in the diffusion isolation region 53 forming the collector wall (step (E)). An insulating oxide film 56 is provided on the emitter region 57 and the contact region 53a, and the insulating oxide film 56 on the upper surface of the emitter region 57 and the contact region 53a is etched to form wiring layers 58a and 58b (step). (F)).

Thus, N^-The region 52 is a well region W
And a collector, and the emitter region 57 and the base region 5
4 and between the base region 54 and the collector (N^-
4. The diode D of FIG.
1 and D2 are formed (see FIG. 5B). Such a da
Regarding the ions D1 and D2, for example, as shown in FIG.
Then, the wiring layer 58b is connected to the pad 5a, and the connection line is connected.
5b is an internal wiring, and the wiring layer 58a is a power supply line.
Connect to + VDD. As a result, the pad 5a is connected to the power line
+ VDD, the well region W (N ^-Region 52)
Has a higher voltage than the substrate (p-sub) 50
Therefore, a reverse bias state occurs, and the diodes D1 and D2
The well region W enters a floating state. This and
The base region 54 forming the diode D1
It becomes a reverse bias state. Breakdown by applying reverse bias voltage
Comes first on the base region 54 side. It is usually semi-conductive
When forming transistors in the body, the substrate
Base area in the same well W than the P layer on the 50 side
The area is P⁺Is high. That is, the concentration
The higher base side surrenders first. As a result, electrostatic breakdown
Substrate (p-su)
b) It is less likely to affect other circuits via 50,
Roads are easily protected. Also, a high voltage below the breakdown voltage
Substrate 50 is in a reverse bias state
Therefore, there is almost no effect on circuits formed in other areas.
Absent. It should be noted that, contrary to the above, this circuit
Side to the pad 5a, and the inside as a connection line 5b.
Wiring, and connect the wiring layer 58b to the power supply line + VDD.
Then, the emitter-base is reverse biased.
The relationship between the concentration of the emitter region and the concentration of the base region.
A circuit with a protection voltage of around 10 V and a lower breakdown voltage
You can use it. Therefore, the withstand voltage of the protection circuit
If low, such a connection is valid.

As described above, in the embodiment of FIG.
A well region is formed with respect to the P-sub substrate, a diode forming a protection circuit is formed in a floating state, and the diode is broken down to perform electrostatic protection so as not to affect the P-sub substrate. In the embodiment, the transistor is formed vertically in the well region so as not to affect the P-sub substrate, but the present invention can be applied even if the substrate is an N-sub substrate. In this case, each N-type region becomes a P-type region, and each P-type region becomes an N-type region.

[0016]

As can be understood from the above description, in the present invention, since the diode is bidirectionally reverse-biased between the input pad and the power supply line,
Reverse bias operation is performed in both directions, and an input signal can be received in a range up to a voltage at which any diode breaks down. As a result, no input signal is clamped. In a semiconductor substrate, a power supply line or a ground line is usually taken on a substrate (substrate), so that when a high voltage is applied to an input terminal, a current caused by the circuit is simultaneously supplied to other circuits formed through the substrate. Although the flow may be adversely affected, the formation of the diode in the well region causes the substrate to be in a reverse-biased state, thereby suppressing the influence on circuits formed in other regions. Moreover, the breakdown of the diode due to the electrostatic breakdown voltage is performed preferentially by the diode in the well region. As a result, the operating voltage is different from other circuits, for example, 1.8
Even in a circuit in which LSIs operating at about V are mixed, it is possible to realize a circuit capable of sufficiently protecting the static electricity without providing a level conversion circuit on the input side.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a circuit configuration of a semiconductor device to which a semiconductor device of the present invention is applied.

FIG. 2 is an explanatory view of the manufacturing process.

FIG. 3 is an explanatory diagram of a circuit configuration of another semiconductor device to which the semiconductor device of the present invention is applied.

FIG. 4 is an explanatory diagram of the manufacturing process.

FIGS. 5A and 5B are explanatory diagrams of a wiring form of the formed protection diode, wherein FIG. 5A is an explanatory diagram corresponding to the manufacturing process of FIG. 2, and FIG. It is a corresponding explanatory view.

FIGS. 6A and 6B are explanatory diagrams of an example of a conventional output-side protection circuit section. FIG. 6A is a circuit diagram thereof, and FIG. 6B is a cross-sectional view of a diode forming region thereof.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI, 2 ... DSP, 2a ... input terminal, 3 ... power supply circuit, 4 ... battery, 5 ... input protection circuit, 5a ... pad, 5b
... connection line, 6 ... input circuit, 50 ... semiconductor substrate (P-
sub), 51: buried layer (B / L), 10: input protection circuit, 51: buried layer (B / L), 52: N ^- region, 5
3 ... diffusion isolation region, 52 ... N ^- region, 53 ... diffusion isolation region, 54 ... N ⁺ emitter region, 54, 54a, 54b
... Base region, 55a, 55b. Wiring layer, 58. Emitter region, D1, D2, D3.

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5F038 BE07 BH02 BH04 BH06 BH12 BH13 CA10 EZ01 EZ14 EZ20 5F048 AA02 AC07 AC10 BA12 BE03 BH01 CA03 CA07 CA12 CC01 CC06 CC15

Claims (4)

[Claims] 1. A semiconductor device having a semiconductor substrate in which an input protection circuit is formed for a pad for receiving an input signal, wherein a well region formed in the semiconductor substrate and a well region formed in the well region are serially connected in opposite directions. A semiconductor device comprising: two connected diodes; one end of each of the diodes being connected to the pad, and the other end being connected to a power supply line. 2. The semiconductor device according to claim 1, wherein a voltage of the power supply line is lower than a voltage of a power supply line of another semiconductor device. 3. A bipolar transistor in which two base regions are formed on the surface side of the well region, and a bipolar transistor having the well region as a collector is formed without forming an emitter region in the two base regions. 3. The semiconductor device according to claim 2, wherein in the bipolar transistor, the base region serves as each anode, and the collector region serves as a commonly connected cathode, and a collector wall is formed in the wall region. 4. A bipolar transistor is formed by sequentially forming an emitter region and a base region in the vertical direction from a surface side of the well region, and a bipolar transistor having the well region as a collector is formed. 3. The semiconductor device according to claim 2, wherein a collector region serves as each cathode, and the base region serves as an anode connected in common, and a collector wall is formed in the wall region.