JP2010204000A - Rotational angle detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a rotational angle detector for improving detection precision of a rotational angle of a rotor. <P>SOLUTION: When the edge level of a pulse signal input to an input terminal 50 changes to a high level, the output of a DFF circuit 21 becomes a high level but the output of a DFF circuit 22 becomes a low level, so that the output of an XOR circuit 25 becomes a high level. Thus, a DFF circuit 23 holds a high level and a DFF circuit 24 outputs a high level. Since the input of the DFF circuit 23 is fixed to a high level, a level change by noise after first detecting an edge level occurs, and the DFF circuit 23 keeps holding a high level even if the output level of the XOR circuit 25 changes. Then, when the measurement time of a timer circuit 70 reaches standby time tb, the DFF circuit 24 is reset and the DFF circuit 24 outputs a low level. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a rotation angle detection device that detects a rotation angle of a rotating body, and more particularly to a rotation angle detection device that is suitably used for an engine control device in a vehicle.

  Conventionally, a crank angle sensor for detecting the crank angle of an engine is known as this type of rotation angle detection device. FIG. 6 is an explanatory diagram showing a main electrical configuration of a conventional crank angle sensor. FIG. 7 is an explanatory diagram showing the relationship between the rotor and the detection signal.

  The conventional crank angle sensor shown in FIG. 6 includes magnetic sensors 1 and 2, an amplifier 3, a comparator 4, a filter circuit 5, an N-type MOSFET 6, and resistors R1 to R4. The rotor 10 shown in FIG. 7 is inserted and fixed to the crankshaft of the engine, and crests (teeth, convex portions) 11 and troughs (concave portions) 12 formed of a magnetic material are alternately formed along the outer periphery. . The magnetic sensors 1 and 2 are, for example, magnetoresistive elements, and are arranged to face the outer periphery of the rotor 10 so that the passage of the peaks 11 and valleys 12 of the rotor 10 can be detected.

  When the rotor 10 rotates in accordance with the rotation of the crankshaft and the peaks 11 and valleys 12 of the rotor 10 pass in front of the magnetic sensors 1 and 2, the magnetic resistance of the magnetic sensors 1 and 2 passes through the peaks 11 and valleys 12. Correspondingly changes periodically. The magnetic sensors 1 and 2 periodically output an analog signal corresponding to the change in magnetic resistance to the amplifier 3 as a detection signal. The amplifier 3 amplifies the analog signal output from the magnetic sensors 1 and 2. The comparator 4 compares the voltage V1 of the amplified signal output from the amplifier 3 with the threshold voltage Vth generated at the midpoint of the dividing resistors R1 and R2, and a pulse signal (binarized signal) corresponding to the comparison result. Is output (FIG. 7).

For example, as shown in FIG. 7, the pulse signal output from the comparator 4 changes to a high level when the voltage V1 of the amplified signal exceeds the threshold voltage Vth, and when the voltage V1 of the amplified signal is less than the threshold voltage Vth. Changes to low level.
The pulse signal generated by the comparator 4 is input to the filter circuit 5, and noise components superimposed on the pulse signal are removed to some extent. The filter circuit 5 is a low-pass filter or a high-pass filter such as a CR filter circuit. The pulse signal output from the filter circuit 5 is applied to the gate of an N-type MOSFET 6 that is an output transistor, and the N-type MOSFET 6 is turned on while the pulse signal is at a high level. Flows.

  The change in current is detected as a change in voltage on the ECU (electronic control unit) side via the pull-up resistor R4. The ECU measures the detected voltage change timing interval based on the clock signal, calculates the rotation speed of the rotor 10 based on the measured timing interval, and calculates the crank angle based on the rotation speed. . The ECU controls engine ignition timing, fuel injection timing, and the like based on the calculated crank angle.

JP-A-58-118908 (page 2, lower left column to page 4, upper left column, FIGS. 1 to 7).

  FIG. 8 is a schematic diagram showing a state where a pulse signal (comparator output) output from the comparator 4 becomes abnormal due to noise that has entered the crank angle sensor. At the timing when the rotor 10 is switched from the crest 11 to the trough 12 or from the trough 12 to the crest 11 on the front surface of the magnetic sensors 1 and 2, noise enters, the threshold voltage Vth changes, and the level of the amplified signal from the amplifier 3 May change. When such a situation occurs, the comparator 4 would normally output a pulse signal that repeats the high level and the low level, although it must output a pulse signal that continues the high level from the above timing. For this reason, since the ECU includes the edge level (voltage indicated by the edge of the pulse signal) generated by noise in the calculation of the crank angle, an error occurs in the calculated crank angle.

Further, it may be possible to remove the noise by increasing the time constant (for example, CR time constant) of the filter circuit 5, but if the time constant is increased, the timing of outputting the pulse signal to the ECU is delayed. End up.
In particular, with the recent advancement of engine control, it is required to detect the crank angle at a high speed, so it is difficult to increase the time constant of the filter circuit.

  Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to realize a rotation angle detection device capable of increasing the detection accuracy of the rotation angle of a rotating body.

  In order to achieve the above object, a first feature of the present invention is that the detectors (1, 2, 2) that output an analog signal whose magnitude periodically changes in accordance with a change in the rotation angle of the rotating body (10). 3), a pulse signal generation circuit (4) that compares the analog signal output from the detection unit with a predetermined reference value (Vth) and generates a pulse signal according to the comparison result, and the pulse signal generation circuit Detects an initial edge level of a pulse signal generated first in a half cycle of the analog signal, and holds the detected first edge level for a predetermined time (ta) from the detection timing. , 22, 23, 25, 60, 70) and a signal output circuit (24) for outputting a signal having an edge level held in the edge level holding circuit. Level holding circuit, at least until the signal output circuit is a timing for outputting the signal is to become configured to ignore edge level other than the first edge level the detected.

  According to a second feature of the present invention, in the first feature described above, the edge level holding circuit (21, 22, 23, 25, 60, 70) determines the detected first edge level from the detection timing. Within the period until the next half cycle of the analog signal is started, the analog signal is configured to hold the predetermined time (ta) from the detection timing.

  According to a third feature of the present invention, in the first or second feature described above, the signal output circuit (24) outputs a signal having an edge level held by the edge level holding circuit to the predetermined time. It is configured to output before the passage.

  According to a fourth feature of the present invention, in any one of the first to third features described above, the edge level holding circuit (21, 22, 23, 25, 60, 70) includes the pulse signal generation circuit. The edge level detection circuit (21, 22, 25) for detecting the edge level of the pulse signal generated in (4), the time measurement circuit (70) for measuring the predetermined time (ta), and the edge level detection circuit And a holding circuit (23) for holding the first edge level of the detected first pulse signal until the time measured by the time measuring circuit reaches the predetermined time.

  According to a fifth feature of the present invention, in the fourth feature described above, the time measuring circuit (70) has the predetermined time (ta) and the timing at which the signal output circuit (24) outputs the signal (tb). ) And is configured to measure.

  According to a sixth feature of the present invention, in any one of the first to fifth features described above, the end of the predetermined time (ta) is after the signal output circuit (24) outputs the signal. There is to be.

  The seventh feature of the present invention is that the detectors (1, 2) for outputting an analog signal whose magnitude periodically changes in accordance with the change in the rotation angle of the rotating body (10), and the detectors output the analog signals. The analog signal is compared with a predetermined reference value (Vth), and a pulse signal generation circuit (4) for generating a pulse signal according to the comparison result, and the pulse signal generation circuit is first attached to a half cycle of the analog signal. The timing at which the first edge level of the generated pulse signal is detected, and the detected first edge level signal is output by the detection unit in the next half cycle from the detection of the first edge level. And a signal output circuit (21, 22, 24, 60, 70) that continuously outputs for a predetermined time (ta) until the time is reached.

  An eighth feature of the present invention is that, in the seventh feature described above, the signal output circuit (21, 22, 24) detects an edge level of a pulse signal generated by the pulse signal generation circuit (4). A level detection circuit (21, 22) and a time measurement circuit (70) for measuring the predetermined time (ta), and the first edge level of the first pulse signal detected by the edge level detection circuit is detected. It is configured to continuously output the signal having the time measured by the time measuring circuit until the predetermined time is reached.

  According to a ninth feature of the present invention, there is provided the filter circuit (5) for filtering the pulse signal generated by the pulse signal generation circuit (4) in any one of the first to eighth features described above. The first edge level of the first pulse signal output from the filter circuit is detected.

  The edge level holding circuit in the first to sixth features described above holds the first edge level of the pulse signal generated first for a half period of the analog signal output from the detection unit for a predetermined time. Further, edge levels other than the detected first edge level are ignored at least until the signal output circuit reaches a timing for outputting a signal having the edge level held in the edge level holding circuit.

  Therefore, if any one of the first to sixth features described above is used, the pulse signal is affected by noise, and the level changes in the portion after the first edge level in the half cycle of the pulse signal. Even in such a case, since the level change does not appear in the output signal output from the signal output circuit, the detection accuracy of the rotation angle of the rotating body can be improved.

  In particular, if the second feature is used, it can be held for a predetermined time from the detection timing within the period from the detection timing of the first edge level to the timing at which the next half cycle of the analog signal is started. it can.

  Further, if the third feature is used, the signal having the edge level held by the edge level holding circuit can be output before the predetermined time elapses. It is possible to prevent the output signal from being reliably output.

  According to the fourth feature, since the holding circuit includes a time measuring circuit that measures a predetermined time during which the first edge level of the first pulse signal is held, the predetermined time is determined according to the specifications of the rotating body. Can be changed.

  Further, if the fifth feature is used, a time measurement circuit that measures a predetermined time during which the holding circuit holds the first edge level of the first pulse signal and a timing at which the signal output circuit outputs a signal is provided. The predetermined time and timing can be changed according to the specifications of the rotating body.

If the sixth feature is used, the holding circuit can hold the first edge level of the first pulse signal until after the signal output circuit outputs the signal.
Therefore, there is no possibility that the edge level held by the holding circuit changes before the signal output circuit outputs a signal.

  According to the seventh aspect of the present invention, the signal output circuit detects the first edge level of the pulse signal generated first in the half cycle of the analog signal output from the detection unit, and detects the detected first edge. The level signal is continuously output for a predetermined time from when the first edge level is detected until when the detection unit outputs the analog signal in the next half cycle.

  Therefore, if the seventh feature is used, even if the pulse signal is affected by noise and the level changes in a portion after the first edge level in the half cycle of the pulse signal, Since the level change does not appear in the output signal, the detection accuracy of the rotation angle of the rotating body can be improved.

  In particular, according to the eighth feature, since the signal output circuit includes a time measuring circuit that measures a predetermined time during which the signal having the first edge level of the first pulse signal is continuously output, It can be changed according to the specifications of the rotating body.

  In addition, if the ninth feature is used, even if the pulse signal that has passed through the filter circuit includes noise, there is no risk of being affected by the noise. Can be increased.

  In addition, the code | symbol in each said parenthesis shows the correspondence with the specific means as described in embodiment mentioned later.

It is explanatory drawing which shows the main electrical structures of the crank angle sensor which concerns on 1st Embodiment of this invention. 3 is a circuit diagram showing a configuration of an edge level holding circuit 20. FIG. 3 is a timing chart of signals generated at each point of the edge level holding circuit 20; It is a circuit diagram which shows the structure of the edge level holding circuit 20 with which the crank angle sensor which concerns on 2nd Embodiment was equipped. 3 is a timing chart of signals generated at each point of the edge level holding circuit 20; It is explanatory drawing which shows the main electrical structures of the conventional crank angle sensor. It is explanatory drawing which shows the relationship between a rotor and a detection signal. It is a schematic diagram which shows the state in which the pulse signal (comparator output) which the comparator 4 outputs became abnormal by the noise which invaded the crank angle sensor.

<First Embodiment>
An embodiment of a rotation angle detection device according to the present invention will be described with reference to the drawings. In the following embodiments, a crank angle sensor that detects the crank angle of an engine will be described as an example of the rotation angle detection device according to the present invention. FIG. 1 is an explanatory diagram showing the main electrical configuration of the crank angle sensor according to this embodiment. The same components as those of the conventional crank angle sensor shown in FIG.

(Main composition)
The crank angle sensor includes an edge level holding circuit 20 connected to the output side of the filter circuit 5, a clock generation circuit 60 connected to the edge level holding circuit 20, and a timer circuit 70.

  The edge level holding circuit 20 has a function of detecting the edge level of the pulse signal that has passed through the filter circuit 5. The edge level holding circuit 20 has a function of holding only the first edge level of the half cycle of the pulse signal that has passed through the filter circuit 5 among the detected edge levels for a predetermined time. Since the pulse signal that has passed through the filter circuit 5 corresponds to an analog detection signal that is periodically output by the magnetic sensors 1 and 2, the edge level holding circuit 20 has a half cycle of the detection signal that is output by the magnetic sensors 1 and 2. Only the first edge level of the pulse signal corresponding to is held.

The edge level holding circuit 20 has a function of outputting a pulse signal having the held edge level to the N-type MOSFET 6 that is an output transistor when a predetermined time elapses.
The clock generation circuit 60 generates a clock signal that serves as a reference when the edge level holding circuit 20 executes various processes, and a clock signal that serves as a reference for the measurement time of the timer circuit 70. The timer circuit 70 outputs a pulse signal having a time corresponding to the time during which the edge level holding circuit 20 holds the edge level (hereinafter referred to as holding time) and the edge level held by the edge level holding circuit 20. The waiting time (hereinafter referred to as the waiting time) is measured until the timing is reached.

  The holding time and standby time measured by the timer circuit 70 can be changed according to the specifications of the engine in which the crank angle sensor is arranged. Further, instead of the N-type MOSFET, a P-type MOSFET or a bipolar transistor can be used as the output transistor.

(Edge level holding circuit)
FIG. 2 is a circuit diagram showing a configuration of the edge level holding circuit 20. The edge level holding circuit 20 includes five input terminals 50 to 54, four DFF (Delay Flip-Flop) circuits 21 to 24, one XOR (Exclusive-OR) circuit 25, and two NAND circuits 26 and 27. And five NOT circuits 28 to 32 and two output terminals 55 and 56.

  The input terminal 50 is connected to the output of the filter circuit 5 and receives the pulse signal output from the filter circuit 5. In this embodiment, the time constant of the filter circuit 5 is set to two clock cycles generated by the clock generation circuit 60. For this reason, the pulse signal output from the filter circuit 5 has a pulse width of at least two cycles of the clock (pulse signal indicated by IN in FIG. 3).

  The input terminal 51 is connected to the output of the clock generation circuit 60 and receives the clock signal generated from the clock generation circuit 60. The input terminals 52 and 53 are connected to the output of the timer circuit 70, and the input terminal 52 inputs a signal indicating that the measurement time of the timer circuit 70 has reached a preset holding time. The input terminal 53 receives a signal indicating that the measurement time of the timer circuit 70 has reached a preset standby time. The input terminal 54 receives a reset signal output from a reset circuit (not shown) such as a power-on reset circuit.

  The input terminal 50 is connected to the input terminal D of the DFF circuit 21. The input terminal 51 is connected to the clock terminal C of the DFF circuit 21 and is further connected to the clock terminal C of the DFF circuit 22 via the NOT circuit 29. The input terminal 52 is connected to one input of the NAND circuit 26. The input terminal 53 is connected to one input of the NAND circuit 27. The input terminal 54 is connected to each reset bar terminal RB of the DFF circuits 21 and 22 via the NOT circuit 28. The input terminal 54 is connected to the other inputs of the NAND circuits 26 and 27 via the NOT circuit 32.

  The output terminal Q of the DFF circuit 21 is connected to the input terminal D of the DFF circuit 22. The output terminals Q of the DFF circuits 21 and 22 are connected to the input of the XOR circuit 25, and the output of the XOR circuit 25 is connected to the clock terminal C of the DFF circuit 23. The output terminal Q of the DFF circuit 23 is connected to the clock terminal C of the DFF circuit 24, and is further connected to the output terminal 56 via the NOT circuit 31. The output terminal 56 is connected to the timer circuit 70.

  The output terminal Q of the DFF circuit 24 is connected to the output terminal 55 via the NOT circuit 30. The output terminal 55 is connected to an N-type MOSFET 6 that is an output transistor. The reset bar terminal RB of the DFF circuit 23 is connected to the output of the NAND circuit 26, and the reset bar terminal RB of the DFF circuit 24 is connected to the output of the NAND circuit 27.

The DFF circuits 21 and 22 and the XOR circuit 25 detect the edge switching timing of the pulse signal input to the input terminal 50.
The DFF circuit 23 holds only the edge level switched first in the half cycle of the input pulse signal among the edge levels switched at the detected edge switching timing until the holding time elapses.

  Further, the DFF circuit 23 prevents the currently held edge level from changing even when a new edge switching timing is detected during the holding time in which the edge level is held. In other words, the DFF circuit 23 does not accept (ignore) a new level change while the edge level is held.

  The DFF circuit 24 is a pulse signal having the same level as the edge level held by the DFF circuit 23 when the standby time has elapsed, and the pulse signal input from the input terminal 50 is affected by noise. A pulse signal having the same pulse width as the original pulse width in the case where there is no pulse is generated and output from the output terminal 55 via the NOT circuit 30. The pulse width of the output pulse signal is determined by the pitch of the peaks 11 of the rotor 10 and varies depending on the specifications of the engine provided with the crank angle sensor. Further, after the DFF circuit 24 outputs the pulse signal, the DFF circuit 23 transitions to a state in which the next edge level can be held when the holding time has elapsed.

(Crank angle sensor operation)
Next, the operation of the crank angle sensor will be described with reference to the drawings. FIG. 3 is a timing chart of signals generated at each point of the edge level holding circuit 20.

  When the rotor 10 (FIG. 1) rotates and the peaks 11 and valleys 12 formed on the outer periphery of the rotor 10 pass through the magnetic sensors 1 and 2, the respective magnetic resistances of the magnetic sensors 1 and 2 correspond to the passage. The magnetic sensors 1 and 2 output analog detection signals corresponding to the changes. The detection signals output from the magnetic sensors 1 and 2 are input to the amplifier 3 and amplified with a predetermined amplification factor. The amplified signal output from the amplifier 3 is input to the comparator 4, the voltage V1 of the amplified signal is compared with the threshold voltage Vth, and a pulse signal (binarized signal) corresponding to the comparison result is output (comparator output). ).

  The pulse signal output from the comparator 4 is input to the filter circuit 5 and noise components are removed to some extent. The filter circuit 5 is a low-pass filter or a high-pass filter such as a CR filter circuit. The pulse signal output from the filter circuit 5 is input from the input terminal 50 of the edge level holding circuit 20 to the input terminal D of the DFF circuit 21. When the input signal input to the input terminal D changes to high level, the DFF circuit 21 outputs when the clock signal input to the clock terminal C changes to high level (time t1 in FIG. 3). A high level signal is output from the terminal Q.

  The output high level signal is input to the input terminal D of the DFF circuit 22 and the XOR circuit 25. The DFF circuit 22 outputs a low level signal from the output terminal Q because the clock signal input to the clock terminal C is at the low level at the timing when the high level signal is input to the input terminal D.

  Therefore, since the inputs of the XOR circuit 25 are the high level “1” and the low level “0”, the XOR circuit 25 outputs a high level signal (indicated by EDGE in FIG. 3) (time t1). That is, the XOR circuit 25 detects the timing at which the pulse signal input from the input terminal 50 is switched from the low level to the high level.

  The high level signal output from the XOR circuit 25 is input to the clock terminal C of the DFF circuit 23. The input terminal D of the DFF circuit 23 is connected to a power source, and a high level is constantly applied. Therefore, the high level signal is continuously output from the output terminal Q triggered by the input of the high level signal to the clock terminal C.

  That is, the DFF circuit 23 holds the high level signal from the output terminal Q during the holding time (ta) from when the high level signal is output from the XOR circuit 25 until the low level reset signal is input to the reset bar terminal RB. Output continuously. In other words, the DFF circuit 23 uses the high level when the pulse signal input from the input terminal 50 is switched from the low level to the high level as an edge level and holds it until the above holding time (ta) elapses.

  Here, a case where the pulse signal input from the input terminal 50 changes due to the influence of noise will be described. The “noise period” shown in FIG. 3 indicates a period in which the pulse signal (IN) changes due to the influence of noise. In the noise period, the pulse signal originally has to continue to be in a high level state, but has changed twice from a high level to a low level due to the influence of noise.

Since the DFF circuits 21 and 22 process the level change due to noise in the same manner as a normal pulse signal, the DFF circuits 21 and 22 output a signal corresponding to the level switching due to noise. For this reason, the XOR circuit 25 also outputs a signal corresponding to the switching of the noise level.
However, since the high level signal is continuously input to the input terminal D of the DFF circuit 23, the output terminal is independent of the input level of the clock terminal C until the reset signal is input to the reset bar terminal RB. A high level signal is continuously output from Q.

  In other words, the DFF circuit 23 ignores the level change even if the pulse signal input to the input terminal 50 changes the level due to the influence of noise, and the pulse signal is low at the beginning of the half cycle. The first edge level (high level) when switching from the level to the high level can be held until the holding time (ta) elapses (time t1 to t14).

  The high level signal output from the output terminal Q of the DFF circuit 23 is input to the clock terminal C of the DFF circuit 24. The input terminal D of the DFF circuit 24 is also connected to a power source, and a high level signal is continuously input. Therefore, the high level signal is continuously output from the output terminal Q triggered by the input of the high level signal output from the output terminal Q of the DFF circuit 23 to the clock terminal C. The output high level signal is changed to a low level signal by the NOT circuit 30 and output to the N-type MOSFET 6 as an output transistor via the output terminal 55.

  The high level signal output from the output terminal Q of the DFF circuit 23 is changed to a low level signal by the NOT circuit 31 and output from the output terminal 56 to the timer circuit 70. Thereby, the timer circuit 70 starts measuring the holding time ta and the standby time tb. This holding time ta is set to a time shorter than the time corresponding to the pitch of the peaks 11 formed on the rotor 10 by the magnetic sensors 1 and 2. When the noise period can be specified, the certain time can be set to a time longer than at least the noise period and shorter than the time corresponding to the pitch.

  Further, by setting the holding time ta to be longer than the standby time tb, it is possible to prevent a signal affected by noise within the standby time tb from being output to the ECU. In other words, by setting the standby time tb to a time shorter than the holding time ta, the pulse signal having the same level as the edge level held by the DFF circuit 23 is surely received before the holding time ta elapses. In addition, the output from the DFF circuit 24 can be performed quickly.

  When the measurement time of the timer circuit 70 passes the standby time tb (time t12), the timer circuit 70 outputs a high level signal (shown for PWM output in FIG. 3) to the input terminal 53. As a result, the output of the NAND circuit 27 changes to low level, the DFF circuit 24 is reset, and the level of the output terminal Q changes to low level. As a result, the output level of the output terminal 55 changes to a high level (time t12).

  When the measurement time of the timer circuit 70 passes the holding time ta (time t14), a high level signal is output from the timer circuit 70 to the input terminal 52. As a result, the output of the NAND circuit 26 changes to high level, the DFF circuit 23 is reset, and the level of the output terminal Q changes to low level. Further, the output level of the output terminal 56 changes to high level (time t14), and the timer circuit 70 is reset.

  When the pulse signal input to the input terminal 50 changes from the high level to the low level in the next half cycle, the high level at the switching timing is held by the DFF circuit 23 for the holding time ta, and the holding is performed. During the waiting time tb, the DFF circuit 24 outputs a high level signal.

  Thereafter, the edge level holding circuit 20 repeats the above processing for the pulse signal input from the input terminal 50. On the other hand, the ECU measures the output time interval of the high level signal, calculates the rotation angle of the rotor 10 based on the measured value, and calculates the crank angle based on the calculated value.

[Effect of the first embodiment]
As described above, if the crank angle sensor according to the first embodiment is used, even if the level of the pulse signal output from the filter circuit 5 changes due to the influence of noise, the change in the level is transmitted to the ECU. Therefore, the ECU can accurately calculate the crank angle.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to the drawings. The crank angle sensor according to this embodiment is characterized in that a signal of the same level can be continuously output from the switching timing of the crest 11 and the trough 12 of the rotor 10 to the next switching timing. FIG. 4 is a circuit diagram showing a configuration of the edge level holding circuit 20. FIG. 5 is a timing chart of signals generated at each point of the edge level holding circuit 20. Since the configuration other than the configuration of the edge level holding circuit 20 is the same as that of the first embodiment described above, the same reference numerals are used for the same configurations, and description thereof is omitted.

(Edge level holding circuit)
The edge level holding circuit 20 provided in the crank angle sensor according to this embodiment includes four input terminals 50, 51, 52, 54, six DFF circuits 21, 22, 24, 33, 34, 39, 2 One AND circuit 35, 36, two NAND circuits 37, 38, two OR circuits 40, 41, one XOR circuit 25, one NOR circuit 42, and six NOT circuits 28, 29, 31, 32, 43, 44 and two output terminals 55, 56.

  An input terminal 50 for inputting a pulse signal (binarized signal) output from the filter circuit 5 (FIG. 1) is connected to the input terminal D of the DFF circuit 21. The input terminal 51 for inputting the clock signal output from the clock generation circuit 60 is connected to the clock terminal C of the DFF circuit 21, and further connected to the clock terminal C of the DFF circuit 22 via the NOT circuit 29.

  The output terminal Q of the DFF circuit 21 is connected to the input terminal D of the DFF circuit 22. The output terminal Q of the DFF circuit 21 is connected to one input of each of the AND circuits 35 and 36 and the XOR circuit 25. The output terminal Q of the DFF circuit 22 is connected to the other input of the AND circuit 35 via the NOT circuit 43, is connected to the other input of the AND circuit 36 via the NOT circuit 44, and further, XOR The other input of the circuit 25 is connected.

  The output of the XOR circuit 25 is connected to the input terminal D of the DFF circuit 39, and the clock terminal C of the DFF circuit 39 is connected to the input terminal 51. The output terminal Q of the DFF circuit 39 is connected to the clock terminal C of the DFF circuit 33, and the output terminal Q of the DFF circuit 33 is connected to one input of each of the OR circuits 40 and 41. The output of the AND circuit 35 is connected to the other input of the OR circuit 40, and the output of the AND circuit 36 is connected to the other input of the OR circuit 41.

  The output of the OR circuit 41 is connected to one input of the NOR circuit 42, and the output of the NOR circuit 42 is connected to the reset bar terminal RB of the DFF circuit 24. The output of the OR circuit 40 is connected to the clock terminal C of the DFF circuit 24. The output terminal Q of the DFF circuit 24 is connected to the output terminal 55.

  The output of the XOR circuit 25 is connected to the clock terminal C of the DFF circuit 34, and the output terminal Q of the DFF circuit 34 is connected to the output terminal 56 via the NOT circuit 31. The output terminal 56 is connected to the timer circuit 70. The input terminals 52 and 54 are connected to one input of the NAND circuits 37 and 38, respectively.

  The input terminal 54 is connected to each reset bar terminal RB of the DFF circuits 21, 22, 39 via the NOT circuit 28. Further, the input terminal 54 is connected to the other inputs of the NAND circuits 37 and 38 and the NOR circuit 42 via the NOT circuit 32. The output of the NAND circuit 37 is connected to the reset bar terminal RB of the DFF circuit 34, and the output of the NAND circuit 38 is connected to the reset bar terminal RB of the DFF circuit 33.

(Crank angle sensor operation)
Next, the operation of the crank angle sensor will be described with reference to the drawings. FIG. 5 is a timing chart of signals generated at each point of the edge level holding circuit 20.

  The pulse signal output from the filter circuit 5 is input from the input terminal 50 of the edge level holding circuit 20 to the input terminal D of the DFF circuit 21. When the input signal input to the input terminal D changes to high level, the DFF circuit 21 outputs when the clock signal input to the clock terminal C changes to high level (time t1 in FIG. 5). A high level signal is output from the terminal Q.

  The output high level signal is input to the input terminal D of the DFF circuit 22, the AND circuits 35 and 36, and the XOR circuit 25. The DFF circuit 22 outputs a low level signal from the output terminal Q because the clock signal input to the clock terminal C is at the low level at the timing when the high level signal is input to the input terminal D.

  Accordingly, since the inputs of the XOR circuit 25 are the high level “1” and the low level “0”, the XOR circuit 25 outputs a high level signal (indicated by EDGE in FIG. 5) (time t1). That is, the XOR circuit 25 detects the timing at which the pulse signal input from the input terminal 50 is switched from the low level to the high level.

  The low level signal output from the output terminal Q of the DFF circuit 22 becomes a high level signal by the NOT circuit 43 and is input to the AND circuit 35. The high level signal output from the output terminal Q of the DFF circuit 21 is input to the AND circuit 35. Therefore, the AND circuit 35 outputs a high level signal (indicated by REDGE in FIG. 5) (time t1).

  The low level signal output from the output terminal Q of the DFF circuit 22 is input to the AND circuit 36. The high level signal output from the output terminal Q of the DFF circuit 21 is changed to a low level signal by the NOT circuit 44 and input to the AND circuit 36. Therefore, the AND circuit 36 outputs a low level signal (indicated by FEDGE in FIG. 5).

  The high level signal output from the XOR circuit 25 is input to the input terminal D of the DFF circuit 39, and the high level signal is output from the output terminal Q of the DFF circuit 39. The high level signal is input to the clock terminal C of the DFF circuit 33. An input terminal D of the DFF circuit 33 is connected to a power source, and a high level signal is constantly applied. For this reason, the DFF circuit 33 continuously outputs a high level signal (indicated by A in FIG. 5) from the output terminal Q triggered by the input of the high level signal to the clock terminal C.

  The high level signal output from the output terminal Q of the DFF circuit 33 is input to the OR circuits 40 and 41. At this time, since the high level signal is input to the OR circuit 40, the OR circuit 40 outputs a high level signal (indicated by RPULSE in FIG. 5) (time t1). The high level signal is input to the clock terminal C of the DFF circuit 24. The input terminal D of the DFF circuit 24 is connected to a power source, and a high level signal is constantly applied. Therefore, the DFF circuit 24 continuously outputs a high level signal (indicated by OUT in FIG. 5) from the output terminal Q triggered by the input of the high level signal to the clock terminal C.

  That is, in the DFF circuit 24, when the high level signal is output from the OR circuit 40, the crest 11 and the trough 12 of the rotor 10 are switched in the next cycle, and the pulse signal input to the input terminal 50 becomes low level. The high level signal is continuously output from the output terminal Q for the time until the reset signal is input to the reset bar terminal RB.

  Here, a case where the pulse signal input from the input terminal 50 changes due to the influence of noise will be described. The “noise period” shown in FIG. 5 indicates a period in which the pulse signal (IN) changes due to the influence of noise. The pulse signal in the noise period is supposed to continue to be in a high level if it is originally, but has changed twice from a high level to a low level due to the influence of noise.

Since the DFF circuits 21 and 22 process the level change due to noise in the same manner as a normal pulse signal, the DFF circuits 21 and 22 output a signal corresponding to the level switching due to noise. For this reason, the OR circuit 40 also outputs a signal corresponding to the switching of the noise level.
However, since the high level signal is continuously input to the input terminal D of the DFF circuit 24, the output terminal is not related to the input level of the clock terminal C until the reset signal is input to the reset bar terminal RB. A high level signal is continuously output from Q.

  That is, the DFF circuit 24 switches the pulse signal from the low level to the high level at the beginning of the half cycle even when the level of the pulse signal input to the input terminal 50 changes due to the influence of noise. It is possible to continuously output a signal having the first edge level (high level) (time t1 to t14).

  The high level signal output from the XOR circuit 25 is also input to the clock terminal C of the DFF circuit 34. The input terminal D of the DFF circuit 34 is connected to a power source, and a high level signal is constantly applied. Therefore, the DFF circuit 34 outputs a high level signal from the output terminal Q triggered by the input of the high level signal to the clock terminal C. The output high level signal is changed to a low level signal (indicated by TSTA in FIG. 5) by the NOT circuit 31, and is output to the timer circuit 70 via the output terminal 56 (time t1).

  Thus, the timer circuit 70 starts measuring the holding time ta during which the DFF circuit 24 holds the high level signal. This time ta is set to a time shorter than the time corresponding to the pitch of the peaks 11 formed in the rotor 10 by the magnetic sensors 1 and 2. When the noise period can be specified, the certain time can be set to a time longer than at least the noise period and shorter than the time corresponding to the pitch.

  When the measurement time of the timer circuit 70 has passed the holding time (time t12), the timer circuit 70 outputs a high level signal for releasing the holding state of the edge level so that the next edge level can be held. It is output to the input terminal 52. As a result, the outputs of the NAND circuits 37 and 38 change to high level, the DFF circuits 34 and 33 are reset, and the level of each output terminal Q changes to low level. When the DFF circuit 33 is reset, a low level signal is output from the output terminal Q of the DFF circuit 33 to the OR circuit 41 (time t12).

  At this stage, since the pulse signal input from the input terminal 50 has not yet changed to the low level, the AND circuit 36 outputs the low level signal. Therefore, since the OR circuit 41 outputs a low level signal and the NOR circuit 42 outputs a high level signal, the DFF circuit 24 is not reset and continuously outputs a high level signal (time t12).

  When the pulse signal input from the input terminal 50 changes to a low level after a half cycle has elapsed, the output of the output terminal Q of the DFF circuit 21 changes from a high level to a low level, and the output terminal of the DFF circuit 22 The output of Q changes from low level to high level (time t14). As a result, the output of the AND circuit 35 changes from high level to low level, and the output of the AND circuit 36 changes from low level to high level.

  Accordingly, since the output of the OR circuit 41 changes from the low level to the high level, the output of the NOR circuit 42 changes from the high level to the low level, and the DFF circuit 24 is reset. Further, since the output of the OR circuit 40 changes from the high level to the low level, the DFF circuit 24 outputs a low level signal from the output terminal Q. The DFF circuit 24 continuously outputs the low level signal until the input of the clock terminal C changes to the high level in the next half cycle.

  Thereafter, the edge level holding circuit 20 repeats the above processing for the pulse signal input from the input terminal 50. On the other hand, the ECU measures the time interval between the high level signal and the low level signal output from the edge level holding circuit 20, calculates the rotation angle of the rotor 10 based on the measured value, and determines the crank angle based on the calculated value. Calculate the corner.

[Effects of Second Embodiment]
As described above, when the crank angle sensor of the second embodiment is used, even if the level of the pulse signal output from the filter circuit 5 changes due to the influence of noise, the change in the level is transmitted to the ECU. Therefore, the ECU can accurately calculate the crank angle.

  The rotation angle detection device according to the present invention can be applied to an engine rotation sensor, a cam angle sensor, a vehicle speed sensor, an AT sensor, a wheel speed sensor and the like in addition to a crank angle sensor.

1, 2, ... Magnetic sensor, 3 ... Amplifier, 4 ... Comparator, 5 ... Filter circuit,
6 .. Output transistor, 10... Rotor, 20 .. Edge level holding circuit.

Claims (9)

A detection unit that outputs an analog signal whose magnitude periodically changes according to a change in the rotation angle of the rotating body;
A pulse signal generation circuit that compares the analog signal output from the detection unit with a predetermined reference value and generates a pulse signal according to the comparison result;
An edge level holding circuit that detects a first edge level of a pulse signal that is first generated by the pulse signal generation circuit over a half cycle of the analog signal, and holds the detected first edge level for a predetermined time from the detection timing. When,
A signal output circuit that outputs a signal having an edge level held in the edge level holding circuit, and
The edge level holding circuit is
The rotation angle detection device is configured to ignore edge levels other than the detected first edge level at least until the signal output circuit outputs the signal. The edge level holding circuit is
The detected first edge level is within a period from the detection timing to the timing when the next half cycle of the analog signal is started, and is configured to hold the predetermined time from the detection timing. The rotation angle detection device according to claim 1, wherein The signal output circuit is
The rotation angle according to claim 1 or 2, wherein a signal having an edge level held by the edge level holding circuit is output before the predetermined time has elapsed. Detection device. The edge level holding circuit is
An edge level detection circuit for detecting an edge level of the pulse signal generated by the pulse signal generation circuit;
A time measuring circuit for measuring the predetermined time;
2. A holding circuit that holds the first edge level of the first pulse signal detected by the edge level detection circuit until the time measured by the time measurement circuit reaches the predetermined time. The rotation angle detection device according to any one of claims 1 to 3.   The rotation angle detection device according to claim 4, wherein the time measuring circuit is configured to measure the predetermined time and a timing at which the signal output circuit outputs the signal.   6. The rotation angle detection device according to claim 1, wherein the end of the predetermined time is after the signal output circuit outputs the signal. A detection unit that outputs an analog signal whose magnitude periodically changes according to a change in the rotation angle of the rotating body;
A pulse signal generation circuit that compares the analog signal output from the detection unit with a predetermined reference value and generates a pulse signal according to the comparison result;
The pulse signal generation circuit detects the first edge level of the pulse signal generated first in the half cycle of the analog signal, and the signal of the detected first edge level is detected from when the first edge level is detected. A signal output circuit that continuously outputs a predetermined time until the detection unit outputs an analog signal in the next half cycle; and
A rotation angle detection device comprising: The signal output circuit is
An edge level detection circuit for detecting an edge level of the pulse signal generated by the pulse signal generation circuit;
A time measuring circuit for measuring the predetermined time, and the time measured by the time measuring circuit for the signal having the first edge level of the first pulse signal detected by the edge level detecting circuit is the predetermined time. 8. The rotation angle detection device according to claim 7, wherein the rotation angle detection device is configured to output continuously until time is reached. A filter circuit for filtering the pulse signal generated by the pulse signal generation circuit;
9. The rotation angle detection device according to claim 1, wherein the rotation angle detection device is configured to detect a first edge level of the first pulse signal output from the filter circuit. .

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