JP2010200083A - Mos transistor circuit and cmos transistor circuit using double gate field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS transistor circuit and a CMOS transistor circuit using a double gate field effect transistor, which suitably changes an operation mode of the double gate field effect transistor constituting a circuit after setting up the circuit. <P>SOLUTION: The MOS transistor circuit using the double gate field effect transistor applies a first input signal in1 to a primary gate G1 of a double gate field effect transistor X1 (21). A selection circuit 11a is connected to a secondary gate G2. The first input signal in1 and a second input signal in2 are applied to the selection circuit 11a. The first input signal in1 or the second input signal in2 is selected by the selection circuit 11a and is applied to the secondary gate G2. A three-terminal operation or a four-terminal operation is performed according to the input signal which is input by changing into the secondary gate G2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a MOS transistor circuit and a CMOS transistor circuit using a 4-terminal double gate field effect transistor, and more particularly to an improvement of a CMOS inverter circuit using a 4-terminal double gate field effect transistor.

The double gate field effect transistor is said to be effective as a structure that suppresses the short channel effect accompanying miniaturization.
Double gate field effect transistors are roughly divided into two structures. One is a three-terminal double-gate field effect transistor that uses both the first gate and the second gate for signal input, the other uses the first gate for signal input, and the second gate has a predetermined constant potential (constant potential). 4 terminal for controlling the threshold voltage as viewed from the first gate to an optimum value by changing the value of the threshold voltage from time to time, including the case where it is maintained at least at a constant potential for a period sufficiently longer than the input signal period. Double gate field effect transistors are known (see, for example, Patent Documents 1 and 2).

  A circuit for delaying the rising and falling operations by inserting an integrating circuit into the second gate of the four-terminal double-gate field effect transistor in order to control the threshold voltage arbitrarily and accurately as disclosed in Patent Document 1 Compared with a three-terminal double-gate field effect transistor, the gate amplitude (S factor) becomes larger, but the S-factor than when a constant potential is applied to the second gate with a four-terminal double-gate field effect transistor. Becomes smaller. In addition, since the threshold voltage can be shifted in the positive direction at the time of rising, the noise margin can be increased.

  In order to be able to control the threshold voltage seen from the other gate by the potential of one gate electrode as shown in Patent Document 2, a differentiating circuit is provided on the second gate of the four-terminal double-gate field effect transistor. The S-factor is smaller than when a constant potential is applied to the second gate using a four-terminal double-gate field effect transistor, and the second gate capacitance is not directly charged by the input signal. Since Ion cannot be increased, it may not be suitable for driving a high load capacity device.

  An inverter constituting a buffer in a reconfigurable integrated circuit such as an FPGA (Field Programmable Gate Array Integrated Circuit) as shown in Non-Patent Document 1 has a large wiring capacity to drive and a large fan-out. Therefore, an inverter is inevitably designed with a transistor of a large size. Furthermore, in a reconfigurable integrated circuit, there are buffers that are not used at all by the circuit designer depending on the design, and this unused buffer is seen as a simple load capacitance from the drive inverter. This large and unused buffer is particularly problematic because it causes an increase in power consumption due to leakage current.

Japanese Patent Application Laid-Open No. 2004-296795 JP 2006-166384 A

Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Satoshi Nakagawa, Toshihiro Sekikawa, Kouhei Koike, "Consistent simulation evaluation from circuit level to chip level of Flex Power FPGA" IEICE Transactions D, vol. J89-D, no. 6, pp. 1071-18101, 2006.

In circuit design using conventional double-gate field effect transistors, the circuit designer decides in advance whether to use a 3-terminal double-gate field effect transistor or a 4-terminal double-gate field effect transistor at the time of circuit design. It was.
In many circuit designs, an optimum circuit design is possible with this design method. However, after the circuit design, for example, a three-terminal mode in which the same signal is connected to both gates of a four-terminal double-gate field effect transistor, If it is possible to switch between the four-terminal mode in which different signals are connected to the gate, it is possible to design a circuit that realizes a more complicated function.
In a reconfigurable integrated circuit represented by an FPGA (Field Programmable Gate Array Integrated Circuit), since the circuit is dynamically changed, it is not known in advance where the critical path is. It is not possible to appropriately select whether the design is the 3-terminal mode or the 4-terminal mode.

For example, the inverter of the buffer that drives the wiring in the FPGA has a large load capacity. If all the inverters are designed in the three-terminal mode, the driving capability increases, but the input load capacity also increases.
On the other hand, if all inverters are designed in the 4-terminal mode, the driving capability is reduced compared to the 3-terminal mode, but the input load capacity is halved. Therefore, if an appropriate mode can be selected for the characteristic of the signal flowing inside after circuit design, it is considered that an FPGA that operates at higher speed and lower power consumption can be designed.
Thus, the conventional circuit cannot be operated by appropriately changing the operation mode after the circuit is assembled.

  In view of the above problems, an object of the present invention is to provide a MOS transistor circuit and a CMOS using a double gate field effect transistor in which the operation mode of the double gate field effect transistor constituting the circuit can be appropriately changed after circuit assembly. It is to provide a transistor circuit.

  In the MOS transistor circuit using the double gate field effect transistor of the present invention, the first input signal is applied to the first gate of the double gate field effect transistor, and the selection circuit is connected to the second gate. The first input signal and the second input signal are added, and the selection circuit selects the first input signal or the second input signal and applies it to the second gate. A three-terminal operation or a four-terminal operation is performed in accordance with an input signal input by switching to the second gate.

Specifically, the following means are adopted to achieve the above object.
(1) MOS transistor circuit
A functional block composed of a field effect transistor including a four-terminal double gate field effect transistor, and a selection circuit;
A first gate of a four-terminal double-gate field effect transistor in the functional block is connected to a first input signal terminal, and a second gate of the four-terminal double-gate field effect transistor in the functional block is connected to a selection circuit. It is connected to an output terminal, and input signal terminals of two or more different signals including the first input signal terminal are connected to an input terminal of the selection circuit.
(2) In the MOS transistor circuit described in (1) above,
The selection circuit commonly connects the output terminals of two same-conductivity-type transistor switches, connects the memory to the gate of one of the transistor switches so that the contents can be read, and connects the memory to the gate of the other transistor switch. Are connected via an inverter so that the contents of the memory are inverted and read out,
The input terminals of the two transistor switches are used as input signal terminals for the two different signals,
The commonly connected output terminal of the two transistor switches is connected to the second gate of the four-terminal double gate field effect transistor.

(3) In the MOS transistor circuit described in (1) above,
The selection circuit commonly connects the output terminals of two different conductivity type transistor switches, and connects the memory to the gates of both of the transistor switches so that the contents can be read.
Each input terminal of the two transistor switches is connected to an input signal terminal of the two different signals,
The commonly connected output terminal of the two transistor switches is connected to the second gate of the four-terminal double gate field effect transistor.
(4) In the MOS transistor circuit described in (1) above,
The selection circuit commonly connects the output terminals of two identical transmission gate type transistor switches in which N-channel and P-channel field effect transistors are connected in parallel.
A memory is connected to the gate of the N-channel field effect transistor which is the one transmission gate type transistor switch and the gate of the P-channel field effect transistor which is the other transmission type transistor switch so that the contents can be read. The gate of a P-channel field effect transistor, which is a transmission gate type transistor switch, and the gate of an N-channel field effect transistor, which is the other transmission type transistor switch, are connected via an inverter to invert the contents of the memory. Configured to be read,
Each input terminal of the two transmission type transistor switches is used as an input signal terminal for the two different signals,
The output terminal connected in common between the two transmission type transistor switches is connected to the second gate of the four-terminal double-gate field effect transistor.

(5) In the MOS transistor circuit described in (1) above,
The functional block has a first gate of one or more four-terminal double-gate field effect transistors as an input terminal, a second gate connected to the output of the selection circuit, a source connected to a first power supply, and a drain connected The output terminal is connected to a second power source through a load element.
(6) In the MOS transistor circuit described in (1) above,
The two or more different input signal terminals are connected to a power source voltage source having a constant potential not exceeding a threshold voltage of the four-terminal double gate field effect transistor.
(7) In the MOS transistor circuit described in (1) above,
The two or more different input signal terminals receive a pulse signal.
(8) In the MOS transistor circuit described in (1) above,
A transistor of the selection circuit is a field effect transistor having a high ON resistance.

(9) In the CMOS transistor circuit, a 4-terminal double-gate field effect transistor having a conductivity type opposite to the 4-terminal double-gate field effect transistor or a field effect transistor having a conductivity type opposite to the 4-terminal double-gate field effect transistor is used as the load element according to (5). And one of these gates is connected to the first gate of the four-terminal double-gate field effect transistor.
(10) In the CMOS transistor circuit, a four-terminal double-gate field effect transistor having a conductivity type opposite to the four-terminal double-gate field effect transistor is connected to the load element according to (5), and A first gate of a four-terminal double-gate field effect transistor is connected to the first gate of the four-terminal double-gate field effect transistor, and a second gate of the opposite-conductivity-type four-terminal double-gate field effect transistor is connected to the first gate. It is characterized by being connected to another selection circuit having the same function as the selection circuit.

(11) A CMOS transistor circuit includes two MOS transistor circuits according to any one of the above (1) to (8), the four-terminal double-gate field effect transistors having different conductivity types,
Combining the 4-terminal double gate field effect transistors X1 and X2 to form a CMOS inverter circuit,
A CMOS inverter circuit in which the CMOS inverter circuit is connected to operate in a three-terminal mode or a four-terminal mode by selectively reading out the memory contents of four transistor switches TS1, TS2, TS3, and TS4 each consisting of a transistor. And
The source of the one four-terminal double-gate field effect transistor X2 and the drain of the other four-terminal double-gate field effect transistor X1 are connected to form an output terminal, and the four-terminal double-gate field effect transistors X2 and X1 Connect both first gates as input terminals,
The transistor switch TS1 is connected to a first input signal terminal and a second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS2 is connected to a first input signal terminal and a second gate of the four-terminal double gate field effect transistor X1,
The transistor switch TS3 is connected to a second input signal terminal and a second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS4 is connected to a third input signal terminal and a second gate of the four-terminal double gate field effect transistor X1,
The memory is directly connected to the gates of the transistor switch TS1 and the transistor switch TS2, and is connected to the gates of the transistor switch TS3 and the transistor switch TS4 via an inverter.
Each input signal from the first to third input signal terminals is selectively input to the second gates of the transistor switches TS1 and TS2 or TS3 and TS4 transistors.

(12) In the CMOS transistor circuit according to any one of (9) to (11), the two or more different input signal terminals exceed a threshold voltage of the four-terminal double-gate field effect transistor. It is connected to a power source voltage source having no constant potential.
(13) In the CMOS transistor circuit according to any one of (9) to (11), the two or more different input signal terminals receive a pulse signal.
(14) In the CMOS transistor circuit described in any one of (9) to (11) above, the transistor of the selection circuit is a field effect transistor having a high ON resistance.

The MOS transistor circuit and the CMOS transistor circuit using the four-terminal double-gate field effect transistor of the present invention have higher flexibility and can realize complicated functions. In particular, by using the wiring drive buffer of a reconfigurable integrated circuit typified by an FPGA, a user-designed circuit can have higher performance in terms of operation speed and power consumption. For example, in a FPGA where the timing margin is large and high-speed operation is not required, the bias voltage is set to suppress the leakage current in the 4-terminal mode to achieve low power consumption, or the timing margin is small and the switching probability is low. Increases the drive current in the 3-terminal mode to achieve higher speed, or uses the differential circuit mode described later for the portion with a small timing margin and high switching probability, thereby reducing the input capacitance and the S factor from the 4-terminal mode. It is possible to realize a high-energy efficiency by reducing the size, or by combining these, it is possible to realize a user-designed circuit that meets the system requirements.
Further, in the conventional circuit, the operation mode was appropriately changed after the circuit was assembled, but the MOS transistor circuit and the CMOS transistor circuit using the double gate field effect transistor of the present invention were The operation mode of the double gate field effect transistor constituting the circuit can be appropriately changed after the circuit is assembled.

The block diagram of Example 1 of this invention is shown. It is an example of a change of the selection circuit of FIG. It is a block diagram of Example 2 of this invention. It is a block diagram of Example 3 of this invention, and is an inverter circuit. In the configuration diagram of the fourth embodiment of the present invention, it is a buffer circuit. It is a block diagram of Example 5 of this invention, and is an inverter circuit. In the configuration diagram of the sixth embodiment of the present invention, it is a buffer circuit. In the configuration diagram of the seventh embodiment of the present invention, it is a buffer circuit. It is a block diagram of Example 8 of this invention, and is a buffer circuit.

  Embodiments of the present invention will be described in detail with reference to the drawings.

The first embodiment relates to a MOS transistor circuit and a CMOS transistor circuit using the double gate field effect transistor of the present invention.
1 is a configuration diagram of a MOS transistor circuit according to a first embodiment of the present invention.
FIG. 1 shows a functional block 10 that has a MOS transistor circuit or a CMOS transistor circuit using a double gate field effect transistor of the present invention and a selection circuit 11 connected in series and that has a predetermined basic function. FIG.
Each input signal is inputted from each signal terminal (not shown) to a signal terminal (not shown) in a functional block (not shown) and a signal terminal (not shown) in the selection circuit 11 via wiring (not shown). Hereinafter, it is configured similarly).
In the functional block 10 composed of field effect transistors including a double gate field effect transistor, an input signal S1 is applied to the first gate of the double gate field effect transistor, and the second signal of the same double gate field effect transistor is applied. The output signal of the selection circuit 11 is added to the two gates.

The selection circuit 11 inputs an input signal S1 and an input signal S2 (two input signals are shown here, but actually two or more input signals may be used), and any one of these inputs is selected. And output to the first gate of the double gate field effect transistor.
Upon receiving a selection command from the outside, the selection circuit 11 selects and outputs the input signal S1 to operate the double gate field effect transistor of the functional block 10 at three terminals, and receives the input signal S2 other than the input signal S1 and the like. Selective output is performed to operate the double-gate field effect transistor of the functional block in four terminals.
The functional block 10 is a circuit configured by a field effect transistor including a double gate field effect transistor. For example, the functional block 10 is a circuit that forms a basic logic gate such as an inverter, an AND gate, an OR gate, or a circuit that combines them. Composed.
The selection circuit 11 is a circuit that selects an input signal 14 to be given to the second gate of the double gate field effect transistor of the functional block 10 from among input signal candidates 13 to the second gate. The input signal candidate 13 to the second gate is the same signal (three-terminal operation) as the input signal 12 to the first gate, or a bias that does not exceed the threshold value of the double gate field effect transistor in the functional block 10 There are arbitrary ones such as a voltage, a bias voltage via a resistor, a pulse signal, and another input signal.
The selection circuit 11 has a function of selecting one signal from a plurality of input signal candidates and conducting the path, and in addition to a memory for storing the path, a transistor switch such as a pass transistor or a transmission gate, or a CMOS logic gate It can be composed of a combination of

  This embodiment can be used for an FPGA wiring buffer, for example. In general, since the output of the wiring buffer of the FPGA is a high fanout, the wiring buffer is required to have a high driving capability. The fan-out is the number of logic signal inputs that can drive the output of the logic IC, expressed as the number of unit logic inputs. The larger the fan-out, the larger the driving capability is required, and the larger the driving capability is accompanied by higher power consumption. However, since the required driving capability for each wiring buffer to maintain a delay differs depending on the circuit in which the FPGA is mounted, the driving capability is switched by switching the input signal of the selection circuit 11 as in this embodiment. An optimum driving capability can be set, and wasteful power consumption can be suppressed. Furthermore, another wiring buffer may exist at the output destination of the wiring buffer, and when a large driving capability is not required for another wiring buffer, the input signal of the selection circuit 11 can be switched to switch the other. The input load capacity of the wiring buffer is reduced, and a circuit with higher speed and lower power consumption can be realized.

FIG. 2 is a modification of the selection circuit of FIG. Specifically, FIG. 2 is a configuration diagram of a 2-input 1-output selection circuit configured by transistor switches (transistors that operate as switches). FIG. 2 includes FIGS. 2 (a) to 2 (d) showing different embodiments of the selection circuit 11.
The selection circuit 11 having two inputs and one output includes a memory 15, transistor switches TS1 (17) and TS2 (18), and an inverter circuit 16. Depending on the contents of the memory 15, either the transistor switch TS1 (17) or TS2 (18) is selected. Is turned on, and the input a or the input b is output from the output c.
FIG. 2A shows an example in which the transistor switches TS1 (17) and TS2 (18) are configured by pass transistors of n-type MOS transistors. In the transistor switch TS1 (17), the contents of the memory 15 are directly input to the gate, and in the transistor switch TS2 (18), the contents of the memory 15 are input to the gate via the inverter circuit 16.
FIG. 2B shows an example in which the transistor switch TS1 (17) is configured by a pass transistor of an n-type MOS transistor, and the transistor switch TS2 (18) is configured by a pass transistor of a p-type MOS transistor. The inverter circuit 16 of a) is not required.

FIG. 2C shows an example in which the transistor switches TS1 (19) and TS2 (20) are configured by CMOS transmission gates combining n-type and p-type MOS transistors.
FIG. 2D shows an example in which an input signal selection operation is performed by a combination of logic circuit elements, for example, AND circuit elements and OR circuit elements. The type of logic circuit element and the logic circuit configuration can be determined by design as long as the desired selection operation is performed.
The contents of the memory 15 are directly input to the first gate of the transistor switch TS1 (19) and the second gate of the transistor switch TS2 (20), and the second gate of the transistor switch TS1 (19) and the transistor switch TS2 (20) The contents of the memory 15 are input to the first gate via the inverter 16.
In the following description, the selection circuit 11 will be illustrated and described as a pass transistor consisting of only an n-type MOS transistor. However, a p-type MOS transistor, a CMOS transmission gate combining n-type and p-type, or a three-terminal dual A gate MOS transistor may be used.

FIG. 3 is a block diagram of a second embodiment of a MOS transistor circuit using a double gate field effect transistor of the present invention.
In the four-terminal double-gate field effect transistor X1 (21), the source S is connected to the power supply Vss, and the drain D is connected to the power supply Vdd via the load element Load (L). A first input signal (in1) is applied to the first gate G1, and a selection circuit 11a is connected to the second gate G2. These configurations are configured as a functional block 10a as indicated by a dotted frame. The example of FIG. 3 basically has the configuration of FIG. 1, the functional block 10 a corresponds to the functional block 10, and the selection circuit 11 a corresponds to the selection circuit 11.
The same first input signal (in1) and second input signal (in2) as the first gate G1 are connected to the selection circuit 11a. Either one of the input signals is rendered conductive by the selection circuit 11a and applied to the second gate G2 of the double gate field effect transistor X1 (21). This embodiment operates as an inverter circuit having the first gate G1 as an input terminal. Note that the number of input signals applied to the selection circuit 11a is not limited to two, and two or more input signals including the first input signal (in1), for example, a plurality of input signals are added as in the first embodiment. May be.

The four-terminal double-gate field effect transistor X1 (21) may be N-type or P-type, but the first gate G1 is the input terminal of the two gates, and the second gate G2 is the same as the first gate G1. The first input signal (in1) or the second input signal (in2) is applied through the selection circuit 11. When the first input signal (in1) is selected by the selection circuit 11, the double gate field effect transistor X1 (21) is in the three-terminal mode and the load capacity as viewed from the first input signal (in1) side increases. However, the S factor decreases and a high Ion is obtained.
On the other hand, when the second input signal (in2) is selected by the selection circuit 11, the double-gate field effect transistor X1 (21) is in the 4-terminal mode and has a larger S factor and lower Ion compared to the 3-terminal mode. However, the load capacity seen from the first input signal (in1) side becomes small, and the threshold voltage can be controlled by the second input signal (in2). For example, if Vdd = 1V and Vss = 0V and the double gate field effect transistor X1 (21) is n-type, the second input signal (In2) is -0.5V, and if it is p-type, the second input signal (in2). If the constant potential is set to 1.5V, the threshold value decreases and the leakage current can be suppressed.
However, when such a negative bias is used, it is necessary to adjust the gate voltage of each transistor switch and the body potential of each transistor in order to perform switching reliably in the selection circuit 11a.

Further, if the ON resistance of each transistor switch or one of the transistor switches in the selection circuit 11a in FIG. 3 is designed to be high, another circuit characteristic can be obtained.
For example, when the circuit of FIG. 2A is applied as the selection circuit 11a, the ON resistance of the transistor switch on the first input signal (in1) side (for example, corresponding to TS2 of FIG. 2A) is high. Equivalent to a circuit (refer to Patent Document 1) in which an integration circuit is inserted in the second gate G2 of the four-terminal double-gate field effect transistor X1 (21) to delay rise and fall (hereinafter referred to as an integration circuit mode); Although the S factor is larger than that in the three-terminal mode, the S factor is smaller than in the case where a constant potential is applied to the second gate G2 in the four-terminal mode. In addition, since the threshold voltage can be shifted in the positive direction at the time of rising, the noise margin can be increased.
On the other hand, when the ON resistance of the transistor switch (for example, TS1 in FIG. 2A) on the second input signal (in2) side is high, the second terminal of the four-terminal double-gate field effect transistor X1 (21). It becomes equivalent to a circuit (see Patent Document 2) in which a differentiation circuit is inserted into the gate G2 (hereinafter referred to as differentiation circuit mode), and Ion cannot be increased in a steady state, but a constant potential is applied to the second gate in the 4-terminal mode. Since the S factor is smaller than the case where the capacitance of the second gate G2 is given, the capacity of the second gate G2 is not directly charged by the input signal, resulting in low power consumption. Of course, when the ON resistances of the transistor switches on both the first input signal (in1) side and the second input signal (in2) side are high, both of the above behaviors can be realized. Even if the ON resistance of the transistor switch is not consciously increased, both of the above behaviors can be realized although the effect is small as compared with the conventional method without the selection circuit 11a.

FIG. 4 is a configuration diagram of a CMOS transistor circuit using the double gate field effect transistor according to the third embodiment of the present invention.
The circuit of FIG. 4 includes a CMOS inverter circuit A composed of four-terminal double-gate field effect transistors X1 (22) and X2 (23), and transistor switches TS1 (24), TS2 (25), TS3 (26), This is a CMOS inverter circuit A capable of performance control, in which TS4 (27) is added and the CMOS inverter circuit A configured by X1 (22) and X2 (23) is operated in the three-terminal mode or the four-terminal mode depending on the contents of the memory 15 .
The transistor switch TS1 (24) is connected to the input signal in1 terminal and the second gate of the four-terminal double gate field effect transistor X2 (23),
The transistor switch TS2 (25) is connected to the input signal in1 terminal and the second gate of the four-terminal double gate field effect transistor X2 (22),
The transistor switch TS3 (26) is connected to the input signal in2p terminal and the second gate of the 4-terminal double gate field effect transistor X2 (23),
The transistor switch TS4 (27) is connected to the input signal in2n terminal and the second gate of the four-terminal double gate field effect transistor X1 (22),
The memory mem15 is directly connected to the gates of the transistor switches TS1 (24) and TS2 (25) and is connected to the gates of the transistor switches TS3 (26) and TS4 (27) via the inverter 16.

The CMOS inverter circuit A connects the drain of the n-type MOS transistor X2 (23) and the source of the p-type MOS transistor X1 (22), inputs the input signal in1 to the first gate in1 of both transistors, and inputs each input signal in2p. , In2n are selectively input to the second gate in1 of both transistors.
For example, if the output of the memory 15 is an ON signal, the transistor switches TS1 (24) and TS2 (25) are turned ON, and the input signal in1 is applied to the second gates of the transistor switches X1 (22) and X2 (23). When operating as a terminal mode CMOS inverter circuit and the output of the memory 15 is an OFF signal, the transistor switches TS3 (26) and TS4 (27) are turned on, and the four-terminal double gate field effect transistor X2 (23) The input signal in2p is applied, and the 4-terminal double gate field effect transistor X1 (22) operates as a 4-terminal mode CMOS inverter circuit to which the input signal in2n is applied. Of course, if the ON resistance of each transistor switch is set high, the differentiation circuit mode and the integration circuit mode can also be set.

The 4-terminal double gate field effect transistor X2 (23) can be described as the functional block 10b, and the 4-terminal double gate field effect transistor X1 (22) can be described as the functional block 10c. The transistor switches TS1 (24) and TS3 (26) can be described as one selection circuit 11b, and the transistor switches TS2 (25) and TS4 (27) as one selection circuit 11c. The transistor switch level is described for the reduction of 16, and the description will be made using transistor switches for the same reason.
4 is compared with the circuit of FIG. 3, the circuit is composed of the functional block 10b of the four-terminal double gate field effect transistor X2 (23) and the selection circuit 11b of the transistor switches TS1 (24) and TS3 (26). Functions as a load for the four-terminal double-gate field effect transistor X1 (22).
As can be seen from the examples shown in FIGS. 2 to 4, the embodiments shown in FIG. 5 and the subsequent examples are also composed of combinations of functional blocks and selection circuits as shown in FIG. 1.

FIG. 5 is a configuration diagram of a CMOS transistor circuit using a double gate field effect transistor according to a fourth embodiment of the present invention.
In the circuit of FIG. 5, the performance-controllable CMOS inverter circuit A of FIG. 4 is connected in series in two stages to constitute a buffer circuit. The description of the circuit of FIG. 5 uses the description of FIG. 4 and is omitted here. In the circuit of FIG. 5, the operation and operation mode of the front-stage and rear-stage CMOS inverter circuits are controlled according to the control contents stored in the memory 15.

FIG. 6 is a configuration diagram of a CMOS transistor circuit using a double gate field effect transistor according to a fifth embodiment of the present invention.
The CMOS transistor circuit of FIG.
Transistor switches TS1, TS2, TS3, TS4 are added to the CMOS inverter circuit composed of the double gate field effect transistors X1 and X2, and the CMOS composed of the double gate field effect transistors X1 and X2 according to the contents of the memory 15 This is a second performance-controllable CMOS inverter circuit B that operates the inverter circuit in different four-terminal modes.
The transistor switch TS1 is connected to the input signal in2p2 terminal and the second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS2 is connected to the input signal in2n2 terminal and the second gate of the 4-terminal double gate field effect transistor X2,
The transistor switch TS3 is connected to the input signal in2p1 terminal and the second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS4 is connected to the input signal in2n1 terminal and the second gate of the four-terminal double gate field effect transistor X1,
The memory mem15 is directly connected to the gates of the transistor switches TS1 and TS2, and is connected to the gates of the transistor switches TS3 and TS4 via the inverter 16.

Transistor switches TS1 and TS2 serve as resistors.
For example, if the output of the memory 15 is an ON signal, the transistor switches TS1 and TS2 are turned ON, the input signal in2p2 is applied to the double gate field effect transistor X2, and the input signal in2n2 is applied to the double gate field effect transistor X1. It operates as a 4-terminal mode CMOS inverter circuit to be added.
If the output of the memory 15 is an OFF signal, the transistor switches TS3 and TS4 are turned ON, the input signal in2p1 is applied to the double gate field effect transistor X2, and the input signal in2n1 is applied to the double gate field effect transistor X1. It operates as a 4-terminal mode CMOS inverter circuit.
By using four input signals in2n1, in2p1, in2n2, and in2p2, a 4-terminal mode CMOS inverter circuit with different performance can be realized, and one of the sets (eg, transistor switches TS1 and TS2 transistor switch ON resistance is designed to be high) By doing so, it is possible to switch between the normal 4-terminal mode and the differentiation circuit mode.
In the case where one set is set to the differentiation circuit mode and the operation is performed with the same voltage as the other four-terminal mode, the input signals in2n2 and in2p2 may not be provided, and the input signals in2n1 and in2p1 are added, respectively.

FIG. 7 is a configuration diagram of a CMOS transistor circuit using the double gate field effect transistor according to the sixth embodiment of the present invention.
The circuit of FIG. 7 is a buffer circuit in which the second performance controllable CMOS inverter circuit B of FIG. 6 and the performance controllable CMOS inverter circuit A of FIG. 4 are combined in a serial connection state. The description of the circuit in FIG. 7 uses the description of the circuit in FIG. 4 and the circuit in FIG. 6 and is omitted here. The front stage of the circuit of FIG. 7 is configured by the circuit of FIG. 6, and the rear stage is configured by the circuit of FIG.
By setting the front stage to the 4-terminal mode or the differentiation circuit mode, the load capacity on the input side can be reduced, and if the output side is set to the 3-terminal mode, a buffer circuit having a high Ion is obtained.

FIG. 8 is a configuration diagram of a CMOS transistor circuit using the double gate field effect transistor according to the seventh embodiment of the present invention.
The circuit of FIG. 8 is a buffer circuit that combines the CMOS inverter circuit C composed of a double gate field effect transistor fixed in the three-terminal mode and the performance-controllable CMOS inverter circuit of FIG. The CMOS inverter circuit C has a configuration in which the first gate and the second gate are short-circuited in the inverter circuit A of FIG.
Usually, the CMOS inverter circuit at the latter stage is often designed to have a large gate width in order to increase the driving force, so there is a concern about an increase in leakage current. However, if the CMOS inverter circuit at the latter stage can be set to the 4-terminal mode. Leakage current when not in use or when large driving capability is not required can be suppressed.

FIG. 9 is a configuration diagram of a CMOS transistor circuit using the double gate field effect transistor according to the eighth embodiment of the present invention.
In the circuit of FIG. 9, the second gate of each double-gate field effect transistor in the CMOS inverter circuit C of the circuit of FIG. 8 is input via resistors R1 and R2 instead of short-circuiting the first gate as shown in FIG. This is a buffer circuit combining the CMOS inverter circuit D composed of a double gate field effect transistor connected to the signals in2n2 and in2p2 terminals and fixed in the differentiation circuit mode, and the performance-controllable CMOS inverter circuit A of FIG.
(Other examples)

  5 and FIGS. 7 to 9 show the buffer circuit using the two-stage CMOS inverter circuit in the fourth and sixth to eighth embodiments. However, the number of stages may be arbitrary as long as the number is two or more. . In this case, the CMOS inverter circuit up to the 2nd to (n-1) th stage (n is a positive integer and an arbitrary number of 4 or more) may be configured by any combination of the circuits shown in the above embodiments. it can.

  In the MOS transistor circuit and the CMOS transistor circuit using the double gate field effect transistor of the present invention, the operation mode of the double gate field effect transistor constituting the circuit can be appropriately changed after the circuit is assembled. Since it is characterized by the configuration of a MOS transistor circuit and a CMOS transistor circuit using transistors, it can be applied to a technology having this feature. For example, a CMOS circuit using a field effect transistor, a CMOS cell library, an FPGA, etc. It is applicable to possible integrated circuits.

10, 10a, 10b, 10c Function blocks 11, 11a, 11b, 11c configured by field effect transistors including double gate field effect transistors Selection circuit 12 Input signal to first gate 13 Input signal candidate to second gate 14 Input signal to selected second gate 15 Memory 16 Inverter circuit G1 First gate G2 Second gate D Drain S Sources in1, in2n, in2p, in2n1, in2p1, in2n2, in2p2 Input signal out Output signal Vdd, Vss Power supply TS1, TS2, TS3, TS4, TS5, TS6, TS7, TS8 Transistor switches X1, X2, X3, X4 Double gate field effect transistors R1, R2 Resistance

Claims (14)

A functional block composed of a field effect transistor including a four-terminal double gate field effect transistor, and a selection circuit;
A first gate of a four-terminal double-gate field effect transistor in the functional block is connected to a first input signal terminal, and a second gate of the four-terminal double-gate field effect transistor in the functional block is connected to a selection circuit. A MOS transistor circuit, characterized in that an input signal terminal for two or more different signals including the first input signal terminal is connected to an input terminal of the selection circuit. The selection circuit commonly connects the output terminals of two same-conductivity-type transistor switches, connects the memory to the gate of one of the transistor switches so that the contents can be read, and connects the memory to the gate of the other transistor switch. Are connected via an inverter so that the contents of the memory are inverted and read out,
The input terminals of the two transistor switches are used as input signal terminals for the two different signals,
2. The MOS transistor circuit according to claim 1, wherein an output terminal commonly connected to the two transistor switches is connected to a second gate of the four-terminal double gate field effect transistor. The selection circuit commonly connects the output terminals of two different conductivity type transistor switches, and connects the memory to the gates of both of the transistor switches so that the contents can be read.
Each input terminal of the two transistor switches is connected to an input signal terminal of the two different signals,
2. The MOS transistor circuit according to claim 1, wherein an output terminal commonly connected to the two transistor switches is connected to a second gate of the four-terminal double gate field effect transistor. The selection circuit commonly connects the output terminals of two identical transmission gate type transistor switches in which N-channel and P-channel field effect transistors are connected in parallel.
A memory is connected to the gate of the N-channel field effect transistor which is the one transmission gate type transistor switch and the gate of the P-channel field effect transistor which is the other transmission type transistor switch so that the contents can be read. The gate of a P-channel field effect transistor, which is a transmission gate type transistor switch, and the gate of an N-channel field effect transistor, which is the other transmission type transistor switch, are connected via an inverter to invert the contents of the memory. Configured to be read,
Each input terminal of the two transmission type transistor switches is used as an input signal terminal for the two different signals,
2. The MOS transistor circuit according to claim 1, wherein an output terminal commonly connected to the two transmission type transistor switches is connected to a second gate of the four-terminal double gate field effect transistor. The functional block has a first gate of one or more four-terminal double-gate field effect transistors as an input terminal, a second gate connected to an output of a selection circuit, a source connected to a first power source, 2. The MOS transistor circuit according to claim 1, wherein the drain is used as an output terminal and is connected to a second power source through a load element. The at least one of the two or more different input signal terminals is connected to a power source voltage source having a constant potential not exceeding a threshold voltage of the four-terminal double gate field effect transistor. 2. The MOS transistor circuit according to 1. 2. The MOS transistor circuit according to claim 1, wherein the two or more different input signal terminals receive a pulse signal. 2. The MOS transistor circuit according to claim 1, wherein the transistor of the selection circuit is a field effect transistor having a high ON resistance. 6. The load element according to claim 5, wherein a four-terminal double-gate field effect transistor having a conductivity type opposite to the four-terminal double-gate field effect transistor or a field effect transistor having a conductivity type opposite to the four-terminal double-gate field effect transistor is used. A CMOS transistor circuit, wherein the CMOS transistor circuit is connected to the first gate of the four-terminal double-gate field effect transistor. 6. The load element according to claim 5, wherein a four-terminal double-gate field effect transistor having a conductivity type opposite to that of the four-terminal double-gate field effect transistor is connected to the load element according to claim 5. The first gate is connected to the first gate of the four-terminal double gate field effect transistor, and the second gate of the opposite conductivity type four-terminal double gate field effect transistor has the same function as the selection circuit. A CMOS transistor circuit characterized by being connected to another selection circuit. Two said MOS transistor circuits of any one of Claims 1 thru | or 8, The 4-terminal double gate field effect transistor is made into the mutually different conductivity type,
Combining the 4-terminal double gate field effect transistors X1 and X2 to form a CMOS inverter circuit,
A CMOS inverter circuit in which the CMOS inverter circuit is connected to operate in a three-terminal mode or a four-terminal mode by selectively reading out the memory contents of four transistor switches TS1, TS2, TS3, and TS4 each consisting of a transistor. And
The source of the one four-terminal double-gate field effect transistor X2 and the drain of the other four-terminal double-gate field effect transistor X1 are connected to form an output terminal, and the four-terminal double-gate field effect transistors X2 and X1 Connect both first gates as input terminals,
The transistor switch TS1 is connected to a first input signal terminal and a second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS2 is connected to a first input signal terminal and a second gate of the four-terminal double gate field effect transistor X1,
The transistor switch TS3 is connected to a second input signal terminal and a second gate of the four-terminal double gate field effect transistor X2,
The transistor switch TS4 is connected to a third input signal terminal and a second gate of the four-terminal double gate field effect transistor X1,
The memory is directly connected to the gates of the transistor switch TS1 and the transistor switch TS2, and is connected to the gates of the transistor switch TS3 and the transistor switch TS4 via an inverter.
A CMOS transistor circuit configured to selectively input respective input signals from the first to third input signal terminals to the second gates of the transistor switches TS1 and TS2 or TS3 and TS4. 12. The two or more different input signal terminals are connected to a power source voltage source having a constant potential not exceeding a threshold voltage of the four-terminal double gate field effect transistor. A CMOS transistor circuit according to any one of the preceding claims. 12. The CMOS transistor circuit according to claim 9, wherein the two or more different input signal terminals receive a pulse signal. 12. The CMOS transistor circuit according to claim 9, wherein the transistor of the selection circuit is a field effect transistor having a high ON resistance.

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