JP2010197091A - Digital rf memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To downsize a digital RF memory device that can be frequency-modulated. <P>SOLUTION: The digital RF memory device includes: a distribution means 1 for distributing a reception IF signal; a downconversion means for downconverting the divided two reception signals to the frequency at which the signals can be processed in a digital circuit; first and second A/D conversion means 8, 9 for converting the downconverted two reception signals into first and second digital signals; a memory 10 for storing the converted first and second digital signals; a modulation-wave generating circuit means 15 for frequency-modulating the first and second digital signals stored in the memory 10; first and second D/A conversion means 18, 19 for converting into analog signals the first and second digital signals modulated by the modulation-wave generating circuit means; and a synthesizing means 24 for synthesizing outputs of the first and second D/A conversion means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital RF memory device that stores a received signal digitized by an A / D conversion circuit in a memory and performs frequency modulation at the stage of the digital circuit when the stored received signal is reproduced.

FIG. 4 is a diagram showing a configuration of a conventional digital RF memory device.
Japanese Patent Laying-Open No. 2006-153700 (Patent Document 1) describes a radar echo generation apparatus that can accurately generate a radar echo using a DRFM (digital RF memory) that stores a radio frequency waveform. .
In FIG. 4, a portion constituted by “LPF → A / D conversion circuit → memory → D / A conversion circuit” corresponds to the internal configuration of the DRFM shown in FIG. 1 of Japanese Patent Laid-Open No. 2006-153700. FIG. 1 of Japanese Patent Laid-Open No. 2006-153700 has been redrawn so that it can be easily compared with the description of the embodiment of the present application described later.

When frequency modulation is performed in the conventional digital RF memory device shown in FIG. 4, the received IF signal is divided into two by the distributor 1.
If the frequency of the received IF signal is f [Hz] and the angular velocity is ω [rad / s], there is a relationship of ω = 2πf.
One of the reception IF signals distributed by the distributor 1 is mixed by the first mixer 4 with a signal in which a phase difference of π / 2 [rad] is provided to the output of the first local oscillator 2, and the mixed signal After the harmonics generated in the first mixer 4 are removed by the first LPF 6, they are digitized by the first A / D conversion circuit 8 and stored in the memory 10 as the first digitized signal.
The other of the reception IF signals distributed by the distributor 1 is mixed with the output of the first local oscillator 2 by the second mixer 5, and harmonics generated by the second mixer 5 from the mixed signal are mixed. After removal by the second LPF 7, it is digitized by the second A / D conversion circuit 9 and stored in the memory 10 as a second digitized signal.

At the time of reproduction, the first digitized signal stored in the memory 10 is output to the first D / A conversion circuit 18 and then the output of the second local oscillator 20 is in the order of π / 2 [rad]. The signal having the phase difference is mixed with the third mixer 22, and the output of the third mixer 22 is input to the synthesizer 24.
The second digitized signal stored in the memory 10 is output to the second D / A conversion circuit 19 and then mixed with the output of the second local oscillator 20 by the fourth mixer 23. The output of the fourth mixer 23 is input to the synthesizer 24.
The signal reproduced by the synthesizer 24 is a signal having the same frequency as that of the received IF signal. When frequency modulation is performed, a modulation circuit 25 configured by a microwave circuit is provided at the subsequent stage of the synthesizer 24.
However, when the modulation circuit 25 is configured by a microwave circuit, there is a problem that the circuit scale increases and the disadvantages in mounting are large.

JP 2006-153700 A

  The present invention has been made to solve the above-described problems, and when reproducing a signal stored in a memory, the stored signal is frequency-modulated at the stage of a digital circuit before D / A conversion. Accordingly, it is an object of the present invention to provide a digital RF memory device that does not require the use of a modulation circuit having a large circuit scale constituted by a microwave circuit, and that can reduce the size of the device.

A digital RF memory device according to the present invention comprises:
Distributing means for distributing the received IF signal, down-converting means for down-converting the two distributed received signals to a frequency that can be processed by a digital circuit, and the first and second digital signals for the two down-converted received signals First and second A / D conversion means for converting into signals, a memory for storing the converted first and second digital signals, and the first and second digital signals stored in the memory Modulation wave generation circuit means for frequency modulation; first and second D / A conversion means for converting the first and second digital signals modulated by the modulation wave generation circuit means into analog signals; A combining means for combining the outputs of the first and second D / A conversion means is provided.

  According to the present invention, when a received IF signal converted into a digital signal and stored in a memory is reproduced, frequency modulation can be performed at the stage of the digital circuit before D / A conversion. There is no need to use a “modulation circuit composed of wave circuits”, and the apparatus can be miniaturized.

1 is a diagram illustrating a configuration of a digital RF memory device according to a first embodiment. 6 is a diagram illustrating a configuration of a digital RF memory device according to a second embodiment. FIG. It is a figure which shows the structure of the digital RF memory apparatus by Embodiment 3 and Embodiment 4. FIG. It is a figure which shows the structure of the conventional digital RF memory apparatus.

An object of the present invention is to reduce the size of a digital RF memory device, and is constituted by a microwave circuit whose circuit scale is increased by performing frequency modulation at the stage of the digital circuit when reproducing a received signal stored in the memory. This is realized without using a modulation circuit.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In the drawings, the same reference numerals indicate the same or equivalent ones.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a digital RF memory device according to the first embodiment.
As shown in the figure, the digital RF memory device according to the present embodiment distributes a received IF signal, and downconverts the received IF signal distributed by the distributor 1 to a frequency that can be processed by a digital circuit. The first mixer 4 and the second mixer 5, the first local oscillator 2 that supplies the local oscillation signal for the first mixer 4 and the second mixer 5, and the output of the first local oscillator 2 The first phase shifter 3 that creates a phase delay of π / 2, the first LPF 6 for removing harmonics generated by the first mixer 4 and the harmonics generated by the second mixer 5 are removed. For the first LPF 7, the first A / D conversion circuit 8 for A / D converting the signal “A 1” after passing through the first LPF 6, and the signal “B 1 after passing through the second LPF 7. A / D conversion for A / D conversion The first digital signal A / D converted by the first A / D conversion circuit 8 and the second digital signal A / D converted by the second A / D conversion circuit 9 are accumulated. The memory 10 is provided.
Note that the output “A1” of the first LPF 6 is represented by the following equation (5), and the output “B1” of the second LP7 is represented by the following equation (8).

In addition, the digital RF memory device according to the present embodiment reproduces two digital signals output from the memory 10 when the received IF signal is reproduced using the first and second digital signals stored in the memory 10. Modulation wave generation circuit 15 that generates two modulation signals (ie, “cos ω _m t” and “−sin ω _m t”) for frequency modulation, a digital signal output from the memory 10, and an output of the modulation wave generation circuit 15 The first multiplier 11, the second multiplier 12, the third multiplier 13, and the fourth multiplier 14 are provided.

Specifically, the first multiplier 11 multiplies the first digital signal output from the memory 10 by the first modulation signal “cosω _m t” output from the modulation wave generation circuit 15, and an expression (described later) The signal “C1” represented by 9) is output.
The second multiplier 12 multiplies the first digital signal output from the memory 10 and the second modulation signal “−sinω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (10) described later. The signal “D1” is output.
The third multiplier 13 multiplies the second digital signal output from the memory 10 and the first modulation signal “cosω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (11) described later. The signal “E1” is output.
The fourth multiplier 14 multiplies the second digital signal output from the memory 10 by the second modulation signal “−sin ω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (12) described later. The signal “F1” is output.

The digital RF memory device according to the present embodiment also includes a first adder 16 that adds the output “C1” of the first multiplier 11 and the output “F1” of the fourth multiplier 14, A second adder 17 for adding the output “D1” of the multiplier 12 and the output “E1” of the third multiplier 13 is provided.
The first adder 16 outputs a signal “G1” expressed by Expression (13) described later, and the second adder 17 outputs a signal “H1” expressed by Expression (14) described later. To do.
In addition, the digital RF memory device according to the present embodiment includes the first D / A conversion circuit 18 that converts the output signal “G1” of the first adder 16 into an analog signal, and the output of the second adder 17. A second D / A conversion circuit 19 for converting the signal “H1” into an analog signal is provided.

In addition, the digital RF memory device according to the present embodiment has a second local oscillator 20 that outputs a signal having the same frequency as that of the first local oscillator 2 described above, and an output of the second local oscillator 20 is π / 2. A second phase shifter 21 for creating a phase delay, a third mixer 22 for mixing the output of the first D / A converter circuit 18 and the output of the second phase shifter 21, and a second D / A conversion A fourth mixer 23 that mixes the output of the circuit 19 and the output of the second local oscillator 20, and a combiner 24 that combines the output “I1” of the third mixer 22 and the output “J1” of the fourth mixer 23. It has.
The output “I1” of the third mixer 22 is expressed by Expression (15) described later, the output “J1” of the fourth mixer 23 is expressed by Expression (16) described later, and the output “K1” of the synthesizer 24. Is represented by the following formula (17). In FIG. 1, the output of the synthesizer 24 is displayed as “K”.

In the digital RF memory device according to the first embodiment, when the memory is stored, the received IF signal is distributed by the distributor 1, the first local oscillator 2, the first phase shifter 3, the first mixer 4, and the second mixer 5. , Divided into “I component” and “Q component”, A / D converted by the first A / D conversion circuit 8 and the second A / D conversion circuit 9, respectively, and then stored in the memory 10.
The reason why the received IF signal is divided into an I component (in-phase component) and a Q component (quadrature component) is that the received IF signal has phase information so that the phase information is not lost in digital signal processing. It is.
First, the details until the “I component” and “Q component” are stored in the memory 10 are shown below.
The reception IF signal is expressed by the following equation (1).
Received IF signal: cosωt (angular velocity: ω) Equation (1)
As described above, when the angular velocity of the reception IF signal is ω [rad / s] and the frequency is f [Hz], ω = 2πf.
The outputs of the first local oscillator 2 and the second local oscillator 20 are expressed by the following equation (2).
Output of local oscillators 2 and 20: cosωLt (angular velocity: ωL) (2)
Here, assuming that the angular velocity of the signal output from the local oscillator 2 is ωL [rad / s] and the frequency is fL [Hz], ωL = 2πfL.
In each of the following equations, the angular velocity ω [rad / s] = 2πf (f: frequency [Hz]).

As for the I component, the product of the output of the distributor 1 and the output of the first phase shifter 3 appears in the output of the first mixer 4, and the I component is expressed by Expression (3).
COSωt × COSωLt = 1/2 × {COS (ω + ωL) t + COS (ω-ωL) t} Equation (3)
After passing through the first LPF 6 that removes the angular velocity ω + ωL component, only the angular velocity ω-ωL component appears and is expressed by equation (4).
1/2 × COS (ω-ωL) t ・ ・ ・ ・ ・ Formula (4)
Here, if ωd = ω−ωL, equation (4) is expressed as equation (5).
A1: 1/2 x COSωdt Equation (5)
That is, the output A1 of the first LPF 6 is represented by “1/2 × COSωdt”.

Similarly, as for the Q component, the product of the output of the distributor 1 and the output of the first local oscillator 2 appears in the output of the second mixer 5, and the Q component is expressed by Expression (6).
COSωt × −SINωLt = −1 / 2 × {SIN (ω + ωL) t−SIN (ω−ωL) t} (6)
After passing through the second LPF 7 that removes the angular velocity ω + ωL component, only the angular velocity ω-ωL component appears and is expressed by equation (7).
1/2 × SIN (ω-ωL) t ・ ・ ・ ・ ・ Formula (7)
Here, if ωd = ω−ωL, Equation (7) is expressed as Equation (8).
B1: 1/2 x SINωdt Equation (8)
That is, the output B1 of the second LPF 7 is represented by “1/2 × SINωdt”.
The I component expressed by the equation (5) and the Q component expressed by the equation (8) are respectively digitized by the first A / D conversion circuit 8 and the second A / D conversion circuit 9, and the memory 10 Accumulated in.

Next, a detailed operation during playback will be described.
At the time of reproduction, multipliers 11 to 14 multiply the output of the memory 10 and the output of the modulated wave generation circuit 15 (-SINωmt, COSωmt).
That is, as described above, the first multiplier 11 multiplies the first digital signal output from the memory 10 by the first modulation signal “cosω _m t” output from the modulation wave generation circuit 15, which will be described later. The signal “C1” represented by Expression (9) is output.
The second multiplier 12 multiplies the first digital signal output from the memory 10 and the second modulation signal “−sinω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (10) described later. The signal “D1” is output.
The third multiplier 13 multiplies the second digital signal output from the memory 10 and the first modulation signal “cosω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (11) described later. The signal “E1” is output.
The fourth multiplier 14 multiplies the second digital signal output from the memory 10 by the second modulation signal “−sin ω _m t” output from the modulation wave generation circuit 15, and is expressed by Expression (12) described later. The signal “F1” is output.

Outputs “C1” to “F1” of the first multiplier 11 to the fourth multiplier 14 are expressed by the following equations (9) to (12).
C1: 1/2 x COSωdt x COSωmt
= 1/4 x {COS (ωd + ωm) t + COS (ωd-ωm) t} Equation (9)
D1: 1/2 × COSωdt × −SINωmt
= −1 / 4 × {SIN (ωd + ωm) t−SIN (ωd−ωm) t} (10)
E1: 1/2 × SINωdt × COSωmt
= 1/4 x {SIN (ωd + ωm) t + SIN (ωd-ωm) t} (11)
F1: 1/2 × SINωdt × −SINωmt
= 1/4 × {COS (ωd + ωm) t−COS (ωd-ωm) t} (12)

Further, the output “C1” and the output “F1” are added by the first adder 16, and the output “−D1” and the output “E1” are added by the second adder 17. Here, the polarity of the output “D1” is inverted.
The output “G1” of the first adder 16 and the output “H1” of the second adder 17 are expressed by the following equations (13) and (14).
G1 (= C1 + F1): 1/2 × COS (ωd + ωm) t Equation (13)
H1 (= E1-D1): 1/2 × SIN (ωd + ωm) t Equation (14)
Equations (13) and (14) indicate that the signal of the angular velocity ωd is the I component and the Q component of the signal modulated at the angular velocity ωm, and the frequency modulation can be performed by the digital circuit.
Thereafter, the signals represented by the equations (13) and (14) are converted into analog signals by the first D / A conversion circuit 18 and the second D / A conversion circuit 19, and the third mixer is obtained. 22, the fourth mixer 23, the second local oscillator 20, the second phase shifter 21, and the combiner 24 demodulate the I component and the Q component.

The output “I1” of the third mixer 22 is the product of the output G and the output of the second phase shifter 21, and the output “J1” of the fourth mixer 23 is the output “H1” of the second local oscillator 20. This is the product of the outputs, and is expressed by equations (15) and (16).
I1: 1/2 × COS (ωd + ωm) t × COSωLt
= 1/4 × {COS ((ωd + ωm) + ωL) t + COS ((ωd + ωm) -ωL) t}
= 1/4 x {COS (ω + ωm) t + COS (ω + ωm-2ωL) t} Equation (15)
J1: 1/2 × SIN (ωd + ωm) t × −SINωLt
= 1/4 × {COS ((ωd + ωm) + ωL) t−COS ((ωd + ωm) -ωL) t}
= 1/4 x {COS (ω + ωm) t−COS (ω + ωm-2ωL) t} Equation (16)

Next, the output “I1” and the output “J1” are combined by the combiner 24, and the output “K1 (shown as K in FIG. 1)” of the combiner 24 is expressed by Expression (17).
K1: 1/4 × {COS (ω + ωm) t + COS (ω + ωm-2ωL)} t + 1/4 × {COS (ω + ωm) t−
COS (ω + ωm-2ωL) t} = 1/2 × COS (ω + ωm) t Equation (17)
As described above, a signal frequency-modulated with a modulation signal having an angular velocity ωm can be obtained without using a modulation circuit composed of a microwave circuit.

  As described above, the digital RF memory device according to the present embodiment includes the distribution unit 1 that distributes the reception IF signal, and the down conversion unit that down-converts the two distributed reception signals to a frequency that can be processed by the digital circuit. (Local oscillator 2, first phase shifter 3, first mixer 4, second mixer 5, and the like), and first and second signals that convert the two down-converted received signals into first and second digital signals Second A / D conversion means 8 and 9, a memory 10 for storing the converted first and second digital signals, and frequency modulation of the first and second digital signals stored in the memory 10 Modulated wave generating circuit means 15 for converting the first and second digital signals modulated by the modulated wave generating circuit means 15 into analog signals. A conversion means 18 and 19, and a combining means 24 for combining the outputs of said first and second D / A converting means 18 and 19.

  More specifically, the digital RF memory device according to the present embodiment includes a distributor 1 that distributes a reception IF signal to a first reception signal and a second reception signal, and a first oscillation signal that outputs a local oscillation signal having a predetermined frequency. Local oscillator 2, first phase shifter 3 that delays the output of first local oscillator 2 by π / 2 phase, the distributed first received signal and the output of first phase shifter 3 are mixed, A first mixer 4 that down-converts to a frequency that can be processed by a circuit, and a second mixer that mixes the distributed second received signal and the output of the first local oscillator 2 and down-converts to a frequency that can be processed by a digital circuit Outputs of the mixer 5, the first LPF 6 that removes the harmonic components generated in the first mixer 4, the second LPF 7 that removes the harmonic components generated in the second mixer 5, and the output of the first LPF 6 The digital signal The first A / D conversion circuit 8 for conversion, the second A / D conversion circuit 9 for converting the output of the second LPF 7 into a digital signal, and the output of the first A / D conversion circuit 8 A memory 10 is provided for storing one digital signal and a second digital signal that is the output of the second A / D conversion circuit 9.

  Further, a modulation wave generating circuit 15 for generating first and second modulation signals for frequency modulating the first and second digital signals stored in the memory 10, and a first digital signal output from the memory 10 And a first multiplier 11 that multiplies the first modulation signal output from the modulation wave generation circuit 15, a first digital signal output from the memory 10, and a second modulation signal output from the modulation wave generation circuit 15. , A second multiplier 12 that multiplies the second digital signal output from the memory 10, a third multiplier 13 that multiplies the first modulation signal output from the modulation wave generation circuit 15, and an output from the memory 10. A fourth multiplier 14 that multiplies the second digital signal to be multiplied by the second modulation signal output from the modulation wave generation circuit 15, and adds the output of the first multiplier 11 and the output of the fourth multiplier 14 First add A first adder 16, a second adder 17 for adding the output of the second multiplier 12 and the output of the third multiplier 13, and a first for converting the output of the first adder 16 into an analog signal. D / A conversion circuit 18, second D / A conversion circuit 19 that converts the output of second adder 17 into an analog signal, and a second signal that outputs a signal having the same frequency as that of first local oscillator 2 The local oscillator 20, the second phase shifter 21 that delays the output of the second local oscillator 20 by π / 2 phase, the output of the first D / A conversion circuit 18 and the output of the second phase shifter 21 are mixed. The third mixer 22, the fourth mixer 23 for mixing the output of the second D / A conversion circuit 19 and the output of the second local oscillator 20, the output of the third mixer 22 and the fourth mixer And a synthesizer 24 that synthesizes the outputs of 23.

  Therefore, according to the present embodiment, when the received IF signal converted into a digital signal and stored in the memory 10 is reproduced, it is possible to perform frequency modulation at the stage of the digital circuit before D / A conversion. Therefore, it is not necessary to use a modulation circuit composed of a conventional microwave circuit, and the apparatus can be miniaturized.

Embodiment 2. FIG.
FIG. 2 is a diagram showing a configuration of a digital RF memory device according to the second embodiment.
Compared with the configuration of the digital RF memory device according to the first embodiment (FIG. 1), in the present embodiment, the second multiplier 12, the fourth multiplier 14, the first adder 16, and the second The output “C1” of the first multiplier 11 is input to the first D / A conversion circuit 18 and only the output “E1” of the third multiplier 13 is the third. The D / A conversion circuit 19 is input.
The output “C1” of the first multiplier 11 and the input “G2” to the first D / A conversion circuit 18 are the same, and the output “E1” of the third multiplier 13 is the same as the output “G1”. The input “H2” to the D / A conversion circuit 19 is the same.

A second local oscillator 20 that outputs a signal having the same frequency as the first local oscillator 2; a second phase shifter 21 that creates a phase delay of π / 2 from the output of the second local oscillator 20; A third mixer 22 that mixes the output of the first D / A conversion circuit 18 and the output of the second phase shifter 21, the output of the second D / A conversion circuit 19, and the output of the second local oscillator 20 And a synthesizer 24 for synthesizing the output “I2” of the third mixer 22 and the output “J2” of the fourth mixer 23.
As a result, a signal frequency-modulated with a modulation angular velocity ± ωm around the angular velocity ω of the received IF signal is obtained at the output of the synthesizer 24.

In the digital RF memory device according to the second embodiment, the input “G2” to the first D / A conversion circuit 18 and the input “H2” to the second D / A conversion circuit 19 are expressed by the following equation (18 ) And formula (19).
G2 (= C1): 1/4 × {COS (ωd + ωm) t + COS (ωd−ωm) t} (18)
H2 (= E1): 1/4 × {SIN (ωd + ωm) t + SIN (ωd−ωm) t} (19)
The output “I2” of the third mixer 22 is the product of the output of the first D / A conversion circuit 18 and the output of the second phase shifter 21, and the output “J2” of the fourth mixer 23 is the second This is the product of the output of the D / A conversion circuit 19 and the output of the second local oscillator 20, and is expressed by equations (20) and (21).

I2: 1/4 × {COS (ωd + ωm) t + COS (ωd-ωm) t} × COSωLt
= 1/8 × {COS (ω + ωm) t + COS (ω + ωm-2ωL) t + COS (ω-ωm) t
+ COS (ω-ωm-2ωL) t} Equation (20)
J2: 1/4 × {SIN (ωd + ωm) t + SIN (ωd−ωm) t} × −SINωLt
= 1/8 × {COS (ω + ωm) t−COS (ω + ωm-2ωL) t + COS (ω-ωm) t
-COS (ω-ωm-2ωL) t} Equation (21)
The output “I2” and the output “J2” are combined by the combiner 24, and the output “K2” of the combiner 24 is expressed by Expression (22).
K2: 1/8 × {COS (ω + ωm) t + COS (ω + ωm-2ωL) t + COS (ω-ωm) t
+ COS (ω-ωm-2ωL) t + 1/8 × {COS (ω + ωm) t−COS (ω + ωm-2ωL) t
+ COS (ω-ωm) t−COS (ω-ωm-2ωL) t}
= 1/4 × {COS (ω + ωm) t + COS (ω-ωm) t} Equation (22)

In the first embodiment described above, the modulation angular velocity of the output “G1” of the first adder 16 and the output “H1” of the second adder 17 is only the “+ ωm” component, and “−ωm”. In contrast to the components being canceled, the second embodiment does not perform an operation for canceling the “−ωm” component.
Accordingly, both the “+ ωm” component and the “−ωm” component appear in the output of the synthesizer 24 as shown in the equation (22).
That is, in the present embodiment, a signal frequency-modulated at a modulation angular velocity ± ωm is obtained, and can be simultaneously modulated to the upper and lower frequencies with respect to the angular velocity ω of the reception IF signal.
In the conventional modulation with the microwave circuit, the upper (+ ωm) modulation circuit and the lower (−ωm) modulation circuit are switched in terms of time. However, the present invention can solve the problem that the modulation cannot be performed at the same time.

As described above, the digital RF memory device according to the present embodiment does not use the second multiplier 12, the fourth multiplier 14, the first adder 16, and the second adder 17. The output signal of the first multiplier 11 is directly input to one D / A conversion circuit 18, and the output signal of the third multiplier 13 is directly input to the second D / A conversion circuit 19.
In the present embodiment, it is possible to simultaneously modulate both the upper and lower frequencies with respect to the frequency f (= ω / 2π) of the reception IF signal.
In the conventional modulation by the microwave circuit, the upper (+ ωm) modulation circuit and the lower (−ωm) modulation circuit are switched in a time-division manner, but in this embodiment, the width of two signals (+ ωm to −ωm at the same time). ) Modulation can be applied.

Embodiment 3 FIG.
FIG. 3 is a diagram illustrating a configuration of a digital RF memory device according to the third embodiment.
The digital RF memory device according to the third embodiment sets an arbitrary amplitude coefficient with respect to the output signal (COSωmt) of the modulated wave generation circuit 15 shown in the second embodiment. A reproduction signal amplitude-modulated to amplitude can be obtained.
In the present embodiment, the reception IF signal level is expressed by the following equation (23).
Reception IF signal: R × cos ωt (amplitude: R, angular velocity: ω) (23)
In the figure, “Am” is an output (amplitude) of the modulated wave generation circuit 15.
“C3” is an output of the first multiplier 11, and “E3” is an output of the third multiplier 13.

In the digital RF memory device according to the present embodiment, the inputs “G3” and “H3” of the first D / A conversion circuit 18 and the second D / A conversion circuit 19 are expressed by the following equations (24), (25)
G3 (= C3): R × Am × 1/2 × COS (ωd) t Expression (24)
H3 (= E3): R × Am × 1/2 × SIN (ωd) t Equation (25)
The outputs “I3” and “J3” of the third mixer 22 and the fourth mixer 23 are expressed by the following equations (26) and (27).
I3: R × Am × 1/2 × COS (ωd) t × COSωLt Expression (26)
J3: R × Am × 1/2 × SIN (ωd) t × −SINωLt Expression (27)

The output “I3” and the output “J3” are combined by the combiner 24, and the output “K3” of the combiner 24 is expressed by Expression (28).
K3: R × Am × 1/2 × COS (ωd + ωL) t
= R x Am x 1/2 x COSωt Equation (28)
As a result, a reproduction signal modulated to an arbitrary amplitude width Am with respect to the reception IF signal level is obtained.
In the present embodiment, the modulation wave generation circuit 15 performs amplitude modulation. However, even if amplitude modulation is performed on the output of the memory 10, the same effect is obtained.

As described above, the modulation wave generating circuit 15 of the digital RF memory device according to the present embodiment uses only the first modulation signal for frequency-modulating the first and second digital signals stored in the memory 10. And the first modulated signal is set to an arbitrary amplitude.
In the present embodiment, an arbitrary amplitude coefficient is generated by the modulated wave generation circuit regardless of the reception IF signal level, so that a signal amplitude-modulated to an arbitrary amplitude can be obtained.

Embodiment 4 FIG.
The configuration of the digital RF memory device according to the fourth embodiment is basically the same as the configuration of the digital RF memory device according to the third embodiment (FIG. 3), but the output signal ( The difference is that COSωmt) is set to an amplitude coefficient inversely proportional to the received IF signal level (that is, the amplitude R of the received IF signal).
In the present embodiment, the output level from the synthesizer 24 is set by setting the amplitude coefficient inversely proportional to the level of the reception IF signal with respect to the output signal (Am) of the modulated wave generation circuit 15 shown in the third embodiment. Can obtain a constant reproduction signal.

A digital RF memory device according to the fourth embodiment will be described with reference to FIG.
In the digital RF memory device according to the fourth embodiment, the input “G3” to the first D / A conversion circuit 18 and the input “H3” to the second D / A conversion circuit 19 are expressed by the following equation (29 ) And the formula (30).
G3 (= C3): R × Am × 1/2 × COS (ωd) t Equation (29)
H3 (= E3): R × Am × 1/2 × SIN (ωd) t (30)
Here, if Am is set to Km / R (Am is inversely proportional to R, Km is a constant), Expressions (29) and (30) become Expressions (31) and (32) below.
G3 (= C3): Km × 1/2 × COS (ωd) t Expression (31)
H3 (= E3): Km × 1/2 × SIN (ωd) t Expression (32)
As a result, a reproduction signal having a constant output level is obtained from the synthesizer 24 regardless of the reception IF signal level.

In the present embodiment, the output “I3” of the third mixer 22 and the output “J3” of the fourth mixer 23 are expressed by the following equations (33) and (34).
I3: Km × 1/2 × COS (ωd) t × COSωLt Expression (33)
J3: Km × 1/2 × SIN (ωd) t × −SINωLt Expression (34)
The output “I3” and the output “J3” are combined by the combiner 24, and in this embodiment, the output “K3” of the combiner 24 is expressed by Expression (35).
K3: Km × 1/2 × COS (ωd + ωL) t
= Km × 1/2 × COSωt Equation (35)
Since Km is a constant, a reproduction signal having a constant output level (that is, the output “K3” of the synthesizer 24) can be obtained from the synthesizer 24 regardless of the reception IF signal level.
In the third embodiment or the fourth embodiment, amplitude modulation is performed by the modulation wave generating circuit 15, but the same effect can be obtained even if amplitude modulation is performed by the memory output.

As described above, the modulation wave generating circuit 15 of the digital RF memory device according to the present embodiment uses only the first modulation signal for frequency-modulating the first and second digital signals stored in the memory 10. The first modulated signal generated is set to an amplitude that is inversely proportional to the received IF signal level.
In the present embodiment, by generating a modulation signal having an amplitude inversely proportional to the reception IF signal level, a reproduction signal having a constant amplitude after multiplication and a constant output level can be obtained.

  The present invention is useful for realizing a digital RF memory device capable of downsizing the device without using a modulation circuit constituted by a microwave circuit.

DESCRIPTION OF SYMBOLS 1 Divider 2, 20 Local oscillator 3, 21 Phaser 4, 5, 22, 23 Mixer 6, 7 LPF 8, 9 A / D conversion circuit 10 Memory 11, 12, 13, 14 Multiplier 15 Modulation wave generation circuit 16 , 17 Adder 18, 19 D / A conversion circuit 24 Synthesizer

Claims (5)

  Distributing means for distributing the received IF signal, down-converting means for down-converting the two distributed received signals to a frequency that can be processed by a digital circuit, and the first and second digital signals for the two down-converted received signals First and second A / D conversion means for converting into signals, a memory for storing the converted first and second digital signals, and the first and second digital signals stored in the memory Modulation wave generation circuit means for frequency modulation; first and second D / A conversion means for converting the first and second digital signals modulated by the modulation wave generation circuit means into analog signals; A digital RF memory device comprising a synthesis unit for synthesizing outputs of the first and second D / A conversion units.   A distributor that distributes the reception IF signal into a first reception signal and a second reception signal, a first local oscillator that outputs a local oscillation signal of a predetermined frequency, and an output of the first local oscillator that is π / 2 A first phase shifter that delays the phase, a first mixer that mixes the distributed first received signal and the output of the first phase shifter and down-converts to a frequency that can be processed by a digital circuit; A second mixer that mixes the second received signal and the output of the first local oscillator and down-converts to a frequency that can be processed by a digital circuit, and removes a harmonic component generated by the first mixer. 1 LPF, a second LPF that removes harmonic components generated by the second mixer, a first A / D conversion circuit that converts the output of the first LPF into a digital signal, and the second 2 LPF output A second A / D conversion circuit for converting to a digital signal, a first digital signal that is the output of the first A / D conversion circuit, and a second that is the output of the second A / D conversion circuit 9 , A modulation wave generating circuit for generating first and second modulation signals for frequency-modulating the first and second digital signals stored in the memory, and an output from the memory A first multiplier that multiplies the first digital signal to be multiplied by the first modulation signal output from the modulation wave generation circuit, and a second digital signal that is output from the memory and the first digital signal output from the memory. A second multiplier that multiplies the modulation signal of the second digital signal, a third multiplier that multiplies the second digital signal output from the memory and the first modulation signal output from the modulation wave generating circuit, and the memory Second output A fourth multiplier for multiplying the digital signal by the second modulation signal output from the modulation wave generating circuit; and a first addition for adding the output of the first multiplier and the output of the fourth multiplier A second adder for adding the output of the second multiplier and the output of the third multiplier, and a first D / A for converting the output of the first adder into an analog signal A conversion circuit; a second D / A conversion circuit that converts an output of the second adder into an analog signal; a second local oscillator that outputs a signal having the same frequency as the first local oscillator; A second phase shifter that delays the output of the second local oscillator by π / 2 phase, a third mixer that mixes the output of the first D / A conversion circuit and the output of the second phase shifter, and A fourth mixer for mixing the output of the second D / A converter circuit and the output of the second local oscillator; Digital RF memory and wherein the output of the mixer with and a combiner for combining the outputs of said fourth Miki.   Without using the second multiplier, the fourth multiplier, the first adder, and the second adder, the first D / A conversion circuit includes the first multiplier. 3. The digital RF memory device according to claim 2, wherein an output signal is directly input, and an output signal of the third multiplier is directly input to the second D / A conversion circuit.   The modulation wave generation circuit generates only a first modulation signal for frequency-modulating the first and second digital signals stored in the memory, and the first modulation signal is set to an arbitrary amplitude. The digital RF memory device according to claim 3, wherein the digital RF memory device is provided. The modulation wave generation circuit generates only a first modulation signal for frequency-modulating the first and second digital signals stored in the memory, and the first modulation signal is set to a reception IF signal level. 4. The digital RF memory device according to claim 3, wherein the digital RF memory device is set to an inversely proportional amplitude.

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