JP2010186810A - Semiconductor storage device, structure, and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of suppressing characteristic variance, by which a high operation rate can be obtained, among resistance variation type nonvolatile memory elements, a structure, and a manufacturing method. <P>SOLUTION: The semiconductor storage device includes a first electrode, a second electrode opposed to the first electrode, and a metal oxide provided between the first electrode and second electrode and showing resistance variation, and the metal oxide includes both an amorphous phase and a crystal phase, the densities of metal elements included in the amorphous phase and crystal phase matching each other within a predetermined range. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, a structure, and a manufacturing method.

Non-volatile memory, which is currently the mainstream in the market, is stored in an insulating film placed above the channel, as represented by flash memory and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory. This is realized by using a technique for changing the threshold voltage of the semiconductor transistor by electric charge.
Miniaturization is indispensable for promoting the increase in capacity, but in recent years it has become difficult even to miniaturize a single semiconductor transistor having no charge storage function.

  Therefore, the transistor is only responsible for the switching function to select the memory cell to be read and written, and the memory elements are separated in the same way as DRAM (Dynamic Random Access Memory: rewritable memory whose stored contents disappear after a certain clock time). In recent years, studies are underway to continue miniaturization by further miniaturization.

When the information storage function is continuously miniaturized, it is conceivable to use, as the storage element, a resistance change element using an electronic element whose electrical resistance can be switched by two or more values by some electrical stimulation. In a method of accumulating charges in a capacitor (capacitance) such as DRAM, it is inevitable that the signal voltage decreases as the amount of accumulated charges decreases due to miniaturization, but the electric resistance is generally limited even if it is miniaturized. This is because it is considered that it is advantageous to continue miniaturization if there is a principle and material that changes the resistance value.
Such an operation of the variable resistance element is a switching operation for switching between a low-resistance ON state and a high-resistance OFF state. For example, a switch for interconnecting the wiring 1 and the wiring 2 shown in FIG. In principle, it can also be applied to a switching device for wiring configuration in a circuit.
FIG. 3 is a diagram illustrating a switch that interconnects two wirings.

  There are a plurality of existing techniques for changing the electrical resistance by electrical stimulation. Among these, the most well-studied technique is to switch the crystalline phase (amorphous or crystalline) by passing a pulse current through the chalcogenide semiconductor, and that there is a difference of 2 to 3 digits in the electrical resistance value of each crystalline phase. This is a storage device used and is generally called a phase change memory.

  On the other hand, it is known that even when a metal / metal oxide / metal (hereinafter referred to as MIM type) structure in which a metal oxide is sandwiched between electrodes is applied, a resistance change is caused by applying a large voltage or current. The present invention relates to this MIM type element.

FIG. 4 is a schematic view of a cross section of the MIM variable resistance element.
This figure shows an image of a low resistance path formed in the material.
In the figure, 1 may be an upper first electrode, 2 may be crystalline or amorphous, 3 is a lower second electrode, and 4 is a current path.
For example, a variable resistance element using nickel oxide (NiO) was reported in Solid State Electronics Vol. 7, pp. 785-797 (Solid State Electronics, Vol. 7, P.785-797, 1964.). As in the 1950s and 1960s, various materials have been reported to study the phenomenon of resistance changes with voltage and current.
The current-voltage characteristics of this MIM type resistance change element are shown in FIGS.

FIG. 5A shows a state of changing from OFF to ON, and FIG. 5B shows a state of changing from ON to OFF. 5A and 5B, the horizontal axis represents voltage, and the vertical axis represents current.
The elements shown in FIGS. 5 (a) and 5 (b) maintain the high resistance OFF state or the low resistance ON state characteristics in a nonvolatile manner even when the power is turned off. The resistance state can be switched by applying.
When a voltage higher than the threshold voltage V _t1 is applied to an element in a high resistance off state, the element changes to a low resistance on state, and the electrical characteristics shown in FIG.

Next, when a voltage larger than the threshold voltage V _t2 is applied to the on-state element of FIG. 5B, the state changes to a high-resistance off state, and the electrical characteristics of FIG. 5A are restored. It is possible to repeatedly switch between the state shown in FIG. 5A and the state shown in FIG. 5B, and use this characteristic as a nonvolatile memory cell or nonvolatile switch for circuit switching. Can do.

FIG. 5A shows a state in which a low resistance is turned on when a voltage higher than the threshold voltage V _t1 is applied in a high resistance off state, and FIG. 5B shows a state in which the low resistance is in an on state. A state in which the high resistance is switched off when a voltage higher than the threshold voltage V _t2 is applied is shown.
Here, low resistance means, for example, the order of resistivity of several Ωm, and high resistance means, for example, the order of resistivity of several MΩm.

FIG. 6 schematically shows a current path that assumes a low resistance state in a MIM type resistance change element including a metal oxide.
As shown in FIG. 6, it is not formed in the entire electrode surface, but is characterized by a local current path 4 having a diameter of about several nanometers and about several tens of nanometers at most.

FIG. 7 shows the electrode area dependence of the resistance value in the low resistance state of a parallel plate type element sandwiched between electrodes using NiO, as in the element described in the above-mentioned solid state electronics as the current path resistance change material. .
In the figure, the horizontal axis indicates the area, and the vertical axis indicates the resistance value (both the vertical axis and the horizontal axis are logarithmic axes).
FIG. 7 shows that the resistance value in the low resistance state hardly depends on the electrode area, and clearly shows that the low resistance state is carried by a locally formed current path.
Such a current path is preferentially generated at a portion having a specific crystal structure. On the contrary, in the case of a material such as NiO, when the whole oxide thin film is a completely uniform amorphous (amorphous) phase, it is difficult to form a current path as compared with a crystallized thin film. Particularly in NiO, the reason why a current path is difficult to form is that the movement of charge carriers is governed by hopping conduction, and the hopping probability decreases as a whole due to disorder of crystallinity.

  Also, when used as a switch element, the high resistance state of the element needs to realize a stable high resistance state more than 1000 times that of the memory element, and it is more important to spatially limit the position where the path is formed. become.

Here, Patent Documents 1 to 5 describe examples of technologies related to the semiconductor memory element.
The ferroelectric element disclosed in Patent Document 1 is “a first electrode formed on an insulating film, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, A film having the same composition and different crystallinity as the ferroelectric film is formed in the vicinity of the ferroelectric film.

  According to the ferroelectric element described in Patent Document 1, characteristic deterioration due to etching damage at the periphery of the capacitor is prevented in the ferroelectric element or the ferroelectric memory, and an adverse effect caused by an electric field reaching the ferroelectric around the capacitor. Can be prevented.

  The memory element of Patent Document 2 includes “a lower electrode, an upper electrode, and a memory layer that is located between the upper electrode and the lower electrode, includes a porous material, and includes a nanochannel including metal nanoparticles or metal ions. "

  According to the memory element described in Patent Document 2, it has non-volatile characteristics, can be realized with a high degree of integration, has a high capacity, has a simple manufacturing process, has a low manufacturing cost, and is in a nanochannel. The presence of metal nanoparticles or metal ions has the advantage that the charge transfer path is relatively regular, has excellent reproducibility, and is consistent in performance.

  The memory element of Patent Document 3 is a “metal / semiconductor / metal (MSM) binary switch memory element, which is a resistive memory lower electrode, a resistive memory material provided on the resistive memory lower electrode, and the resistive memory substance. Resistive memory upper electrode provided above, MSM lower electrode provided on the resistive memory upper electrode, semiconductor layer provided on the MSM lower electrode, and MSM upper electrode provided on the semiconductor layer And "."

  According to the memory element described in Patent Document 3, it is possible to prevent a read failure due to a sneak current in a cross-point memory array.

  The non-volatile memory element including the amorphous alloy oxide layer of Patent Document 4 is “in the non-volatile semiconductor memory element, a lower electrode, an oxide layer formed including an amorphous alloy oxide on the lower electrode, And an upper electrode formed on the oxide layer ”.

  According to the non-volatile memory element including the amorphous alloy oxide layer described in Patent Document 4, the structure of the non-volatile memory is very simple as a whole. It can be easily formed using a generally known semiconductor manufacturing process such as a DRAM manufacturing process.

  The multi-layered variable resistance element array of Patent Document 5 is “a first electrode group layer made up of K (K is a natural number) first electrodes arranged on the first surface and a second surface. A second electrode group layer composed of L (L is a natural number) second electrodes arranged so as to be lined up, one or more resistance change bodies whose electric resistance values change by application of an electric pulse, and K first A first plug group comprising K first lead plugs electrically connected to the electrodes, respectively, and a second plug comprising L second lead plugs electrically connected to the L second electrodes, respectively. A first electrode group layer and an access mechanism, wherein the first electrode group layer and the second electrode group layer are arranged such that the K first electrodes and the L second electrodes intersect with each other when viewed from the stacking direction. Are alternately stacked with a space between each other, and a total of three or more K electrodes, L second electrodes, A resistance change body is formed between the first electrode and the second electrode at the intersection point when viewed from the stacking direction, and a total of three or more first electrodes corresponding to a total of three or more first electrode group layers and second electrode group layers. Plug groups and second plug groups are formed, all the first lead plugs and second lead plugs are formed so as to reach the surface of the multilayer variable resistance element array, and the access mechanism is identical to all the first plug groups. Access to each first plug group of the part, and simultaneously contact and separate all the first drawer plugs of some of the first plug groups to electrically connect and disconnect all the first drawer plugs individually. All the second plug groups can be accessed every part of the second plug group and all the second lead plugs of the part of the second plug group can be simultaneously contacted and separated from all the second plug groups. With the second drawer plug S to be so "configuration so it is possible to electrically conductive and blocking.

  According to the multilayer variable resistance element array described in Patent Document 5, it is possible to provide a multilayer variable resistance element array, a variable resistance device, a multilayer nonvolatile memory element array, and a nonvolatile memory device with a simple access mechanism and high access speed. It is said that there is an effect.

JP 2004-296505 A JP 2006-222428 A JP 2007-27755 A JP 2007-227922 A JP 2007-281208 A

In general, in a variable resistance nonvolatile memory element including a metal oxide layer, the oxide layer is composed of either a uniform amorphous film, a polycrystalline film, or a laminated structure thereof. The resistance change phenomenon occurs in a place where both conditions of specific chemical composition and crystal structure are met, but it is difficult to control the spatial position and the number of such places and vary depending on the element. Variation in characteristics occurred. In particular, when the element is shaped by dry etching or the like, there is a problem that the switch characteristics are deteriorated due to damage generated on the processed end face of the variable resistance material layer.
The techniques disclosed in Patent Documents 1 to 5 have the same problem.

  Accordingly, an object of the present invention is to provide a semiconductor memory device, a structure, and a manufacturing method that can obtain a high operation rate and can suppress variation in characteristics between elements in a variable resistance nonvolatile memory element. is there.

  The apparatus according to the present invention includes a first electrode, a second electrode facing the first electrode, and a metal oxide provided between the first electrode and the second electrode and exhibiting a resistance change. The metal oxide includes both an amorphous phase and a crystalline phase, and the density of the gold electrode elements contained in the amorphous phase and the crystalline phase is matched within a predetermined range. Features.

  The structure according to the present invention includes both an amorphous phase and a crystalline phase, and the density of the gold electrode elements contained in the amorphous phase and the crystalline phase coincides within a predetermined range and exhibits a resistance change. Is sandwiched between a first electrode and a second electrode facing the first electrode.

  The manufacturing method according to the present invention includes a step of forming an amorphous variable resistance material on a lower electrode, and irradiating a portion where the variable resistance element of the variable resistance material is to be formed with an electromagnetic wave or a particle beam to change the resistance. A step of forming an element; and a step of forming an upper electrode on the variable resistance material.

  ADVANTAGE OF THE INVENTION According to this invention, provision of the semiconductor memory device, structure, and manufacturing method which can suppress the characteristic dispersion | variation between elements in a resistance change type non-volatile memory element is realizable.

(A) is side sectional drawing which shows one Embodiment of the semiconductor memory device based on this invention, (b) is the Ib-Ib sectional view taken on the line of (a). (A)-(f) is process drawing which shows an example of the manufacturing method of the semiconductor memory device shown to Fig.1 (a), (b). It is a figure which shows the switch which mutually connects two wiring. It is a mimetic diagram of a MIM type resistance change element section. (A) shows a state of changing from off to on, and (b) is a diagram showing a state of changing from on to off. It is a figure which shows the electric current path which bears a low resistance state in the MIM type resistance change element containing a metal oxide. It is a figure which shows the electrode area dependence of the resistance value of the low resistance state of the parallel plate type | mold element pinched | interposed with the electrode using NiO.

<Configuration>
1A is a side sectional view showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 1B is a sectional view taken along line Ib-Ib in FIG.
The semiconductor memory device shown in FIGS. 1A and 1B includes both an amorphous phase and a crystalline phase, and the density of the gold electrode element contained in the amorphous phase and the crystalline phase is within a predetermined range (for example, A variable resistance material 13 made of a metal oxide that exhibits a resistance change of ± 10% is sandwiched between a lower electrode 12 as a first electrode and an upper electrode 15 as a second electrode facing the lower electrode 12 It has a structure. In the figure, 10 indicates a first interlayer insulating film, and 11 indicates a part of the metal of the wiring.

The amorphous phase is arranged so as to surround the periphery of the crystal phase.
The crystal phase is formed by irradiating a spatially narrowed electromagnetic wave or particle beam to an amorphous phase that is uniformly formed in advance.
The crystal phase is in contact with the lower electrode 12 and the upper electrode 15.
The crystal phase is in contact with the lower electrode 12, and the amorphous phase is disposed between the upper electrode 15 and the thickness of 5 nm or less.

Here, the thickness of the crystal phase is set to 5 nm or less. If the thickness is 5 nm, the amorphous phase can be dielectrically broken during the first operation, and if it is more than that, a high voltage power source is required. . This is because the lower limit value may be 0, and the amorphous phase remains in view of the manufacturing method.
The cross-sectional area of the crystal phase is preferably 30 nm ² or more, and the cross-sectional area of the amorphous phase is preferably at least twice the cross-sectional area of the crystal phase.

Here, the fact that the cross-sectional area of the crystal phase is 30 nm ² or more means that it is sufficiently larger than the cross-sectional area 10 nm ² (estimated value) of the low resistance path (4 in FIG. 6). The reason why the cross-sectional area of the amorphous phase is more than twice the cross-sectional area of the crystalline phase is that a minimum thickness of 1 nm is necessary to protect the amorphous phase surrounding the crystalline phase from damage during the process. Considering that, in order to surround a crystal having a cross-sectional area of 30 nm ² , it is estimated that an area approximately twice as large as the cross-sectional area is required.

<Manufacturing method>
Next, an embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to the drawings.
2A to 2F are process diagrams showing an example of a method for manufacturing the semiconductor memory device shown in FIGS. 1A and 1B.
A metal thin film 12a for the lower electrode 12 is deposited on a substrate in which a part of the metal 11 of the wiring is sandwiched between the first interlayer insulating films 10 (FIG. 2A).

An amorphous variable resistance material 13a is formed on the metal thin film 12a (FIG. 2B).
Here, for example, when NiO is used as the resistance change material 13a, a raw material (precursor) containing an amide group and H ₂ O as an oxidizing agent are used in an ALD (atomic layer deposition) mode at a substrate temperature of 150 ° C. to 200 ° C. Can be formed. Alternatively, a precursor containing P or F may be used for vapor phase chemical reaction (CVD) using oxygen as an oxidizing agent. Alternatively, an amorphous material may be obtained by adding about 10 mol% of different metals such as Al and Ta to NiO. NiO in the amorphous phase has a high resistance, and the probability of exhibiting a resistance change phenomenon is extremely low compared to crystallized NiO.

  By applying electromagnetic waves (or particle beams) 14 to a portion where a resistance change element is to be formed and utilizing the generated heat or photochemical reaction, the chemical composition and crystal structure in which resistance change easily occurs are adjusted (FIG. 2 (c) ), (D)).

  Here, for example, a KrF excimer laser can be used as the electromagnetic wave. The pulsed laser light is preferably irradiated through an expander, the intensity is appropriately adjusted (attenuated), and the spot diameter is reduced to 0.5 μm or less through a microscopic optical system. Heating occurs in a short time in the region irradiated with the electromagnetic wave (or particle beam) 14, and NiO crystallizes due to the annealing effect. At this time, the ratio of Ni and O in the crystallization region can be adjusted to several mol% Ni deficiency by optimizing the ratio of nitrogen and oxygen and the total pressure as the atmosphere.

  A metal thin film 16a for the upper electrode 16 is deposited (FIG. 2E), and the element shape is shaped using photolithography and dry etching (FIG. 2F).

  According to the present invention, after a thin film containing the same element as the element included in the resistance change material and having a high resistance and showing no resistance change composed of an amorphous phase is formed in advance, an electromagnetic wave such as an ultraviolet ray or an X-ray, or an electron By applying a particle beam of ions or the like to a specific portion where an element is to be formed and irradiating it to a chemical composition and a crystal structure that cause a resistance change, an element that defines a spatial position where the resistance change occurs can be realized. At this time, it is important that the beam diameter of the electromagnetic wave or particle beam to be irradiated is at least 0.5 μm or less.

<Effect>
The resistance change can be caused only in the crystal region near the center of the electrode, and the spatial size can be controlled by the intensity, wavelength, irradiation time, and atmosphere of the electromagnetic wave that irradiates the space.

  Moreover, the volume which is not restrict | limited to the spatial resolution of a lithographic fee can be crystallized by these processes.

  Furthermore, when elements are formed by dry etching, it is the amorphous phase that does not show a change in resistance because of the high resistance that is exposed on the side walls of the element, and therefore has little influence on the electrical characteristics of the resistance change element, and the characteristics between the elements. There is an effect of suppressing variation.

  The additional process is one process of electromagnetic wave irradiation, the number of additional PR (process) is 0, and there is an advantage of suppressing the manufacturing cost.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

DESCRIPTION OF SYMBOLS 1 Upper first electrode in MIM type element 2 Resistance change material made of metal oxide 3 Lower second electrode in MIM type element 4 Current path responsible for on-state in MIM type resistance change element 10 First interlayer insulation Films 11 and 17 A part of metal of the wiring 12 Lower electrode 13 Resistance change material of amorphous phase 14 Electromagnetic wave or particle beam 15 Upper electrode 16 Wiring disposed on the element 18 Second interlayer insulating film

Claims (8)

A first electrode, a second electrode facing the first electrode, and a metal oxide provided between the first electrode and the second electrode and exhibiting a resistance change,
The metal oxide includes both phases of an amorphous phase and a crystalline phase, and the density of the gold electrode element contained in the amorphous phase and the crystalline phase is matched within a predetermined range. apparatus.   The semiconductor memory device according to claim 1, wherein the amorphous phase is arranged so as to surround the periphery of the crystal phase.   2. The semiconductor memory device according to claim 1, wherein the crystal phase is formed by irradiating a spatially narrowed electromagnetic wave or particle beam with respect to an amorphous phase formed uniformly in advance.   The semiconductor memory device according to claim 1, wherein the crystal phase is in contact with the first electrode and the second electrode.   2. The semiconductor memory device according to claim 1, wherein the crystalline phase is in contact with the first electrode, and an amorphous phase is disposed with a thickness of 5 nm or less between the crystalline phase and the second electrode. ^2. The semiconductor memory device according to claim 1, wherein a cross-sectional area of the crystal phase is 30 nm ² or more, and a cross-sectional area of the amorphous phase is twice or more a cross-sectional area of the crystal phase.   A metal oxide including both an amorphous phase and a crystalline phase, wherein the densities of the gold electrode elements included in the amorphous phase and the crystalline phase are matched within a predetermined range, and exhibits a resistance change, A structure of a semiconductor memory device, wherein the structure is sandwiched between second electrodes facing the first electrode. Forming an amorphous variable resistance material on the lower electrode;
Forming the resistance change element by irradiating an electromagnetic wave or a particle beam to a position where the resistance change element of the resistance change material is to be formed;
Forming an upper electrode on the variable resistance material;
A method of manufacturing a semiconductor memory device.

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