JP2010186304A - Semiconductor layout system, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor layout system for suppressing the overlap of the repeater inserting positions of parallel inter-circuit block wiring. <P>SOLUTION: A wiring information storage part 201 stores the wiring information of inter-circuit block wiring including the start point coordinates and end point coordinates of wiring. A grouping processing part 21 groups inter-circuit block wiring having wiring sections extended in parallel wherein a difference between the X-directional coordinates or Y-axial coordinates of the start point coordinates is within a prescribed distance, of repeater insertion object inter-circuit block wiring. A repeater insertion base point determination part 22 determines the coordinates of positions whose distances from the start point coordinates are different from each other as a repeater insertion base point about the inter-circuit block wiring belonging to the same group. A repeater insertion processing part 23 determines the positions of repeater cells to be inserted into the repeater insertion object inter-circuit block wiring by using the repeater insertion base point as a base point. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor layout system, method, and program, and more particularly to a semiconductor layout system, method, and program for performing hierarchical layout design.

  As a layout design method for a semiconductor integrated circuit, there is a hierarchical layout design. In the hierarchical layout design, the arrangement / wiring in the hierarchical block (circuit block) and the arrangement / wiring of the hierarchical block are performed hierarchically. In general, wiring between hierarchical blocks tends to be longer than wiring within hierarchical blocks. A long wiring such as a wiring between hierarchical blocks has a large delay due to a parasitic element of the wiring. Therefore, in order to improve the delay, it is common to insert buffers or inverter cells called repeaters at regular intervals in the middle of the wiring (see, for example, Patent Document 1).

JP 2002-313920 A

  Here, in the hierarchical layout design, there is a tendency that a plurality of wirings run in parallel from one side of a hierarchical block to a side of another hierarchical block. The wiring between the hierarchical blocks running in parallel has a similar wiring length. Generally, repeaters are inserted at equal intervals in wiring between hierarchical blocks. When a repeater is inserted into wiring between hierarchical blocks that run in parallel for the purpose of delay compensation, the repeater insertion position is close between wirings between hierarchical blocks that run in parallel.

  When repeater insertion positions are close and regions where repeater cells are arranged overlap, processing for shifting the position where repeater cells are arranged is necessary. Along with this, it is necessary to change the route of wiring between hierarchical blocks. When repeaters are inserted at close positions between wirings between parallel hierarchical blocks, the number of repeater cell arrangement positions increases, the number of repeater cells that need to be moved increases, and repeater cells move. The amount also increases. Along with this, the number of correction points for inter-layer block wiring after the repeater cell movement also increases. In addition, the layout becomes complicated, for example, many detours occur in the wiring between the hierarchical blocks.

  The present invention provides a semiconductor layout system, method, and program capable of suppressing overlap of repeater insertion positions of parallel wiring between circuit blocks when a repeater cell is inserted into wiring between circuit blocks in semiconductor layout design. Objective.

  In order to achieve the above object, a semiconductor layout system of the present invention refers to a wiring information storage unit that stores wiring information of wiring between circuit blocks including a starting point coordinate and an ending point coordinate of wiring, and between circuit blocks to which repeaters are inserted. Among the wirings, a grouping processing unit for grouping wirings between circuit blocks having wiring portions extending in parallel with each other, wherein the difference between the coordinates in the X direction or the coordinates in the Y direction of the starting point coordinates is within a predetermined distance; For the wiring between circuit blocks belonging to the same group, a repeater insertion base point determination unit that determines the coordinates of positions where the distances from the start point coordinates are different from each other as a repeater insertion base point, and stores it as repeater insertion base point position information, and the wiring information And the repeater insertion base point position information, the repeater insertion base point is used as a base point, and the repeater insertion target circuit block wiring is inserted. Determining the position of a repeater cell, characterized in that it comprises a repeater insertion processing unit for storing the layout data storage unit as the arrangement information of a repeater cell.

  In the semiconductor layout method of the present invention, the computer refers to the wiring information storage unit that stores the wiring information of the wiring between the circuit blocks including the starting point coordinates and the ending point coordinates of the wiring. A grouping step of grouping wirings between circuit blocks having wiring portions extending in parallel with each other, wherein the difference between the coordinates in the X direction or the coordinates in the Y direction of the starting point coordinates is within a predetermined distance, and the computer includes the same group Repeater insertion base point determining step for determining the coordinates of the positions where the distances from the start point coordinates are different from each other as repeater insertion base points, and storing them as repeater insertion base point position information, and the wiring information and repeater Refer to the insertion base point position information and use the repeater insertion base point as a base point to insert a repeater circuit block. Determining the location of the repeater cell to be inserted into the click between wires, and having a repeater insertion step of storing the layout information storage unit as the arrangement information of a repeater cell.

  The program of the present invention refers to a wiring information storage unit that stores wiring information of wiring between circuit blocks including wiring start point coordinates and end point coordinates in a computer. Grouping processing for grouping wiring between circuit blocks having wiring portions extending in parallel with each other, and a difference between coordinates in the X direction or Y direction coordinates within a predetermined distance, and between circuit blocks belonging to the same group For the wiring, refer to the repeater insertion base point determination process for determining the coordinates of the positions where the distances from the start point coordinates are different from each other as the repeater insertion base point, and storing them as repeater insertion base point position information, and the wiring information and the repeater insertion base point position information The position of the repeater cell to be inserted into the circuit block wiring to be inserted with the repeater insertion base point as the base point Determined, characterized in that to execute a repeater insertion procedure to be stored in the placement information storage unit as the arrangement information of a repeater cell.

  The semiconductor layout system, method, and program of the present invention can suppress the overlap of repeater insertion positions of wirings between parallel circuit blocks.

1 is a block diagram showing a semiconductor layout system according to an embodiment of the present invention. The figure which shows the example of data of a wiring information storage part. The flowchart which shows an operation | movement procedure. The figure which shows the circuit block and wiring between circuit blocks in the semiconductor device to be designed. The figure which shows a repeater insertion base point. The figure which shows the state after repeater cell insertion. The figure which shows the state after an overlap loosening process and rewiring. The figure which shows the state after repeater insertion in a comparative example. The figure which shows the state after the overlap loosening process and rewiring in a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor layout system according to an embodiment of the present invention. The semiconductor layout system includes a data processing device 20 and a storage device 200. The data processing device 20 includes a grouping processing unit 21, a repeater insertion base point determination unit 22, a repeater insertion processing unit 23, an overlap unraveling processing unit 24, and a wiring unit 25. The function of each unit in the data processing device 20 can be realized by executing a predetermined program on the data processing device 20. The storage device 200 includes a wiring information storage unit 201 and an arrangement information storage unit 202. The storage device 200 is a storage device such as a semiconductor memory or a hard disk drive.

  It is assumed that the arrangement of circuit blocks and the wiring between circuit blocks have been determined before the layout system of this embodiment performs processing. The layout system determines the layout of the circuit blocks and the wiring between the circuit blocks based on the circuit connection information. Alternatively, the arrangement of circuit blocks and the determination of wiring may be performed using a device different from the layout system. In addition, it is assumed that a wiring to be a repeater insertion target is determined among the wirings between circuit blocks. For example, timing verification is performed, and a wiring that has a long delay time and does not satisfy the timing constraint is set as a repeater insertion target. Or it is good also considering the wiring whose wiring length is more than predetermined as a repeater insertion object.

  The storage device 200 stores the result of circuit block arrangement and wiring between circuit blocks. The wiring information storage unit 201 stores information on wiring between circuit blocks. The wiring information between the circuit blocks includes the starting point coordinates, the ending point coordinates, and the route information on the way. In addition, the wiring information storage unit 201 includes information (repeater insertion base point information) regarding a repeater insertion base point that is a base point at the time of repeater insertion for the wiring between circuit blocks to be subjected to the repeater insertion process. The arrangement information storage unit 202 stores arrangement information of cells constituting the circuit block. The circuit block arrangement information includes cell arrangement coordinates and cell arrangement direction.

  FIG. 2 shows a specific example of wiring information. FIG. 2 shows wiring information of six inter-circuit block wirings from net1 to net6. The wiring between circuit blocks is represented by a set of one or more wiring segments. A pair of start point coordinates and end point coordinates is stored in the wiring segment. The wiring of the wiring segment is represented by a straight line connecting the start point coordinates and the end point coordinates. The end point coordinates of the wiring segment overlap with the start point coordinates of the next wiring segment. For example, the end point coordinate of the wiring segment 1 of the net 1 is (x2, y1), and this coordinate overlaps the start point coordinate of the wiring segment 2. By following the wiring segment 2 and the wiring segment 3 in order from the wiring segment 1, a wiring route from one circuit block to another circuit block can be configured.

  The grouping processing unit 21 refers to the wiring information storage unit 201, and among the circuit block wirings to be inserted into the repeater, between the circuit blocks having a wiring portion that has a similar position as a starting point coordinate and extends in parallel with each other. Group wiring together. Specifically, the grouping processing unit 21 is configured such that the circuit block wiring whose difference between the X-direction coordinates or the Y-direction coordinates of the start point coordinates is within a predetermined distance, and the circuit block wiring having a similar position as the start point coordinates To do. The grouping processing unit 21 further obtains the similarity of the wiring paths of the wiring between the circuit blocks, has a wiring portion extending in parallel with each other with the similar position as the starting point coordinate, and the circuit blocks having the similar wiring paths Inter-wiring may be grouped.

  The grouping processing unit 21 uses, for example, a Manhattan ratio as an index when determining the similarity of wiring routes. The Manhattan ratio is defined by the ratio between the Manhattan length and the actual wiring route length. The grouping processing unit 21 compares the values of the Manhattan ratio with each other, and groups nets with similar values of the Manhattan ratio. Specifically, a net in which the difference in the value of the Manhattan ratio is within a predetermined value is a net in which the Manhattan ratio is a similar value. Alternatively, instead of the difference, the ratio of the Manhattan ratio may be used, and a net in which the ratio falls within a predetermined range may be a net having a similar value in the Manhattan ratio.

  The repeater insertion base point determination unit 22 determines a position (repeat insertion base point) that serves as a base point when a repeater cell is inserted into the inter-circuit block wiring to be inserted. The repeater insertion base point determination unit 22 determines the coordinates of positions where the distances from the start point coordinates are different from each other for the grouped circuit block wiring as the repeater insertion base point. The repeater insertion base point determination unit 22 stores the determined repeater insertion base point in the wiring information storage unit 201 as repeater insertion base point position information. The repeater insertion base point determination unit 22 may simply notify the repeater insertion base point information to the repeater insertion processing unit 23.

  The repeater insertion processing unit 23 refers to the wiring information and the repeater insertion base point position information, and determines the position of the repeater cell to be inserted into the repeater insertion target circuit block wiring, based on the repeater insertion position. More specifically, the repeater insertion processing unit 23 calculates coordinates that are a predetermined distance from the repeater insertion base point for each repeater insertion target circuit block wiring, and determines the coordinates as the repeater cell insertion position. The repeater insertion processing unit 23 stores the determined repeater cell insertion position in the arrangement information storage unit 202.

  The overlap unraveling processing unit 24 refers to the arrangement information storage unit 202 and checks whether there is a portion where the cells overlap each other. When there is a place where the cells overlap, the overlap unraveling processing unit 24 performs the overlap unraveling process and moves the position of the repeater cell so that the cell overlap is eliminated. The overlapping unraveling processing unit 24 stores the result of the overlapping unraveling processing in the arrangement information storage unit 202. The wiring unit 25 performs rewiring between circuit blocks including repeater cells with reference to the wiring information storage unit 201 and the arrangement information storage unit 202 after the overlapping unraveling processing unit 24 performs the overlapping unraveling process. The wiring unit 25 stores the rewiring result in the wiring information storage unit 201.

  FIG. 3 shows a processing procedure for determining the repeater insertion base point. Prior to the process of determining the repeater insertion base point, the arrangement of circuit blocks and the wiring between the circuit blocks are determined and stored in the arrangement information storage unit 202 and the wiring information storage unit 201. Further, among the wirings between the circuit blocks, the wiring (net) to which the repeater is inserted is determined in advance.

  The grouping processing unit 21 acquires the start point coordinates of the repeater insertion target net from the wiring information storage unit 201. The repeater insertion base point determination unit 22 groups nets whose start points are arranged on the same straight line, that is, nets whose X coordinates or Y coordinates of the start point coordinates match (step S1). For example, when there are a plurality of repeater insertion target nets having the same X coordinate of the start point coordinates of the net, the repeater insertion base point determination unit 22 groups a plurality of nets having the same X coordinate. The X coordinate and the Y coordinate do not have to coincide completely, and may be regarded as the same coordinate if the difference is within a predetermined distance. The repeater insertion target nets grouped in step S1 correspond to group candidate nets.

  The grouping processing unit 21 obtains the lengths of the wiring portions extending in parallel with each other for each net grouped in step S1. More specifically, the grouping processing unit 21 obtains the length (parallel wiring length) of each net that runs in parallel with other nets of the same group at intervals of a predetermined interval or less. The repeater insertion base point determination unit 22 leaves a net having a parallel wiring length equal to or greater than a predetermined threshold in the group, and deletes a net having a short parallel wiring length from the group (step S2). Through the processing so far, nets having the same X-direction coordinate or Y-direction coordinate difference between the start point coordinates and having a parallel wiring length equal to or longer than a predetermined length are grouped. When the nets are grouped into a plurality of groups in step S1, the grouping processing unit 21 performs the process of step S2 for each group.

  The grouping processing unit 21 further performs grouping from the viewpoint of wiring path similarity. The grouping processing unit 21 calculates the Manhattan ratio for each net remaining in the group in step S2. The grouping processing unit 21 compares the Manhattan ratio of each net with each other. The repeater insertion base point determination unit 22 groups nets having similar Manhattan ratios (step S3). The repeater insertion base point determination unit 22 performs this process for each group generated in step S1. By executing steps S1 to S3, the grouping processing unit 21 groups nets having the same X coordinate or Y coordinate of the starting point coordinate, a long parallel wiring length, and a similar Manhattan ratio.

  The repeater insertion base point determination unit 22 receives the result of the grouping process, and determines the repeater insertion base point of the grouped net (step S4). The repeater insertion base point determination unit 22 determines, as repeater insertion base points, coordinates at positions having different distances from the start point coordinates for nets grouped in the same group. For example, the repeater insertion base point determination unit 22 sets α as a predetermined shift length and α × (i−1) (i = 1, 2,..., Circuits belonging to the same group from the start point coordinates on the net path. The number of inter-block wirings) is determined, and this is determined as the repeater insertion base point.

  Here, the shift length α is the “shift length” of the repeater insertion position. The value of the shift length α is smaller than the repeater insertion interval and larger than the larger one of the repeater cell size in the X direction or the Y direction. The operator can specify an arbitrary shift length α to the repeater insertion base point determination unit 22. Alternatively, the repeater insertion base point determination unit 22 may determine the value of the shift length α from the repeater insertion interval, the number of grouped nets, and the like.

  The repeater insertion base point determination unit 22 performs the process of step S4 for each group grouped in step S3. The repeater insertion base point determination unit 22 stores the determined repeater insertion base point in the wiring information storage unit 201 as repeater insertion base point information.

  The repeater insertion processing unit 23 selects one net from the repeater insertion target net, and reads the wiring information and repeater insertion base point information of the net from the wiring information storage unit 201. The repeater insertion processing unit 23 calculates the coordinates on the wiring of the net located on the road corresponding to the predetermined interval from the repeater insertion base point (step S5). The repeater insertion processing unit 23 stores the coordinates calculated in step S5 in the arrangement information storage unit 202 as the arrangement coordinates of the repeater cell (step S6).

  The repeater insertion processing unit 23 performs the processes of steps S5 and S6 for all repeater insertion target nets. The repeater insertion processing unit 23 uses the start point coordinates of the net as a repeater insertion base point for a net for which the repeater insertion base point has not been determined in step S4, that is, for a net that has not been grouped in the grouping of steps S1 to S3. Repeater insertion coordinates are calculated. Alternatively, in step S4, the repeater insertion base point determination unit 22 may determine a start point coordinate as a repeater insertion base point for a net that does not belong to any group and store it in the wiring information storage unit 201. .

  When the repeater insertion coordinates of the repeater insertion target net are determined, the overlap unraveling processing unit 24 refers to the arrangement information storage unit 202 and performs an overlap unraveling process for correcting the overlap between cells and the displacement and orientation of the arrangement position. The overlapping unraveling processing unit 24 stores the result of the overlapping unraveling processing in the arrangement information storage unit 202 (step S7). The wiring unit 25 refers to the wiring information storage unit 201 and the arrangement information storage unit 202, and rewires the circuit in a state after the repeater is inserted. The wiring unit 25 stores the rewiring result in the wiring information storage unit 201 (step S8).

  Hereinafter, a specific example will be described. FIG. 4 shows circuit blocks and wiring between the circuit blocks. FIG. 4 illustrates three circuit blocks of circuit blocks 501 to 503. The circuit block 501 has output terminals 504 to 508. The circuit block 503 has input / output terminals 509 to 512. Nets 513 to 518 are wirings for connecting circuit blocks. Nets 513 to 518 correspond to the net information net1 to net6 shown in FIG. In FIG. 4, the nets 513 to 518 show only the center line of the wiring.

  Each net connects between an output terminal or input / output terminal of a certain circuit block and an input terminal or input / output terminal of another circuit block. For example, the net 513 that is net 1 connects between the output terminal 508 of the circuit block 501 and the input / output terminal 510 of the circuit block 503. A net 518 that is a net 6 is a net that connects circuit blocks (not shown), and in FIG. 4, the terminals of the start point and the end point are omitted.

  The wiring information storage unit 201 stores wiring information of the nets 513 to 518. Further, the arrangement information storage unit 202 stores the arrangement positions and the arrangement directions of the circuit blocks 501 to 503. The starting point of the net is defined on the signal output side, that is, on the output terminal side. Nets 513 to 518 shown in FIG. 4 are all repeater insertion target nets.

  First, in step S1, the grouping processing unit 21 groups nets having the same X coordinate or Y coordinate of the start point. Referring to FIG. 2, the X coordinate of the start point of the nets 513 to 517 (net1 to net5) starting from the output terminals 504 to 508 of the circuit block 501 is x1. The grouping processing unit 21 groups net1 to net5 whose start point X coordinates coincide with each other. Among net1 to net6 shown in FIG. 4, net6 is excluded from the grouping target because the start point coordinates do not match.

  Next, the grouping processing unit 21 checks the parallel wiring length between the grouped net1 to net5 in step S2. Among net1 to net5, net1 to net3 and net5 have wiring portions extending in parallel within a predetermined interval and having a predetermined length or more. Therefore, the grouping processing unit 21 leaves these in the group. About net4, the part extended in parallel with net1-net3 and net5 is short. The grouping processing unit 21 removes net4 from the group. Through the processes so far, net1 to net3 and net5 are grouped.

  Subsequently, in step S3, the grouping processing unit 21 calculates the Manhattan ratio of net1 to net3 and net5. The Manhattan ratio is defined by the ratio between the Manhattan length and the actual wiring route length. Since net1 to net3 connect the circuit block 501 and the circuit block 503 through a similar path, the Manhattan ratio has a similar value. The net 5 connects the circuit block 501 and the circuit block 503 so as to bypass the circuit block 502, and the wiring path is different from the net 1 to net 3. As a result, the Manhattan ratio of net5 becomes a different value from the Manhattan ratio of net1 to net3. The grouping processing unit 21 removes net5 from the group and leaves net1 to net3 in the group.

  In the grouping in steps S1 to S3, nets that have the same X-coordinate or Y-coordinate of the start point coordinates, have some wiring portions extending in parallel, and have similar wiring routes are grouped. In step S4, the repeater insertion base point determination unit 22 determines the grouped repeater insertion base points of net1 to net3 at positions shifted by a length α on the net path from the start point coordinates. When there are a plurality of groups, the repeater insertion base point determination unit 22 determines, for each group, the position where the repeater insertion base point of the net belonging to the group is shifted by a shift length α. The repeater insertion base point determination unit 22 stores the determined repeater insertion base point in the wiring information storage unit 201.

  FIG. 5 shows the repeater insertion base point. The repeater insertion base point determination unit 22 sets net1 as the shift length = 0, and determines the start point coordinates (x1, y1) of net1 as the repeater insertion base point. The repeater insertion base point determination unit 22 sets net2 as the shift length = α, and coordinates (x2 + 2t, y1 + 2t− (α − ((x2 + 2t) −x1) located at a distance of α on the wiring path of net2 from the starting point coordinates of net2. ))) Is determined as the repeater insertion base point. The repeater insertion base point determination unit 22 sets the net3 as the shift length = 2α, and coordinates (x2 + 4t, y1 + 4t− (2α − ((x2 + 4t) −x1) located at a distance of 2α on the wiring path of the net3 from the start point coordinates of the net3. ))) Is determined as the repeater insertion base point. In FIG. 5, the repeater insertion base points of net2 and net3 are indicated by black circles on the net.

  In step S5, the repeater insertion processing unit 23 calculates, for each repeater insertion target net (net1 to net6), coordinates of a position at a predetermined interval on the route of the net from the repeater insertion base point, and the coordinates are used as the repeater cell. Is determined as the coordinates to place. For the grouped net1 to net3, the repeater insertion processing unit 23 determines the repeater insertion position from the base point using the coordinates stored as the repeater insertion position in the wiring information storage unit 201 as the repeater insertion base point. The repeater insertion processing unit 23 determines the repeater insertion position with respect to net4 to net6 that do not belong to any group, using the start point coordinates of the net as the repeater insertion base point. The repeater insertion processing unit 23 stores the determined repeater insertion position in the arrangement information storage unit 202 in step S6.

  FIG. 6 shows a state where the repeater cell is inserted. In FIG. 6, a rectangular box filled with diagonal lines represents a repeater cell. The repeater insertion processing unit 23 inserts a repeater cell from the output terminal 508 at a predetermined interval with respect to net1 with the coordinates of the output terminal 508 as a starting point as a base point. The repeater insertion processing unit 23 inserts a repeater cell at a predetermined interval from the base point, with the net2 being shifted from the output terminal 507, which is the start point, by a distance α. Further, the repeater insertion processing unit 23 inserts repeater cells at a predetermined interval from the base point, with the net3 being shifted from the output terminal 506, which is the starting point, by a distance of 2α.

  In step S7, the overlap unraveling processing unit 24 refers to the placement information storage unit 202 to check the placement coordinates of each repeater cell, and checks whether there is a repeater cell whose position overlaps. When there is a repeater cell whose position overlaps, the overlap unraveling processing unit 24 moves the repeater cell according to the cell arrangement matrix (site) to eliminate the overlap. The overlap unraveling processing unit 24 stores the coordinates of the repeated repeater cell in the arrangement information storage unit 202. The wiring unit 25 refers to the wiring information storage unit 201 and the arrangement information storage unit 202 and performs rewiring. The wiring unit 25 stores the rewiring result in the wiring information storage unit 201.

  FIG. 7 shows a state after the overlap unraveling process and rewiring. In FIG. 6, the arrangement position of the first repeater cell counted from the output terminal 506 of the net 515 (net 3) and the arrangement position of the first repeater cell counted from the output terminal 504 of the net 517 (net 5) are shown. overlapping. The overlap unraveling processing unit 24 moves at least one of the repeater cells whose positions overlap each other, and eliminates the overlap of the repeater cells. The wiring unit 25 rewires the wiring between the circuit blocks in accordance with the arrangement of the repeater cells to be inserted. The circuit shown in FIG. 7 is obtained by performing the overlapping loosening process and rewiring.

  Here, as a comparative example, consider a case where repeater insertion is performed without shifting the repeater insertion base point. FIG. 8 shows a state after the repeater cell is inserted in the comparative example. In the circuit shown in FIG. 4, when the repeater insertion base point is fixed to the start point of the wiring between the circuit blocks and the repeater cell is inserted, the result is as shown in FIG. The nets 513 to 515 (net1 to net3) have start points on the same straight line of the circuit block 501, and run adjacently in parallel. Therefore, when repeater cells are inserted at regular intervals using the start point of the net as a repeater insertion base point, as shown in FIG. 8, the repeater cell insertion positions are close to each other in the first, second, and third stages. Cells are densely arranged. FIG. 9 shows a state after the overlap unraveling process and rewiring in the comparative example. When the repeater cell is moved from the repeater cell insertion shown in FIG. 8 so that the positions of the repeater cells do not overlap and the wiring between the circuit blocks is rewired, the result is as shown in FIG.

  Comparing FIG. 6 and FIG. 8, in this embodiment, the repeater insertion positions of the nets 513 to 515 (net1 to net3) are shifted from the start point of the net by a length α, so that they are inserted into the nets 513 to 515. The repeater cells are not in close proximity. Therefore, as can be seen from a comparison between FIG. 7 and FIG. 9, in this embodiment, fewer repeater cells need to be moved in the overlapping unraveling process than in the comparative example. Further, in the comparative example, since the repeater cells are dense, the amount of movement of the repeater cell that is moved by the overlapping unraveling process becomes large. On the other hand, in the present embodiment, as shown in FIG. 6, since the repeater cells are not arranged at the overlapping positions by the repeater insertion, the movement amount of the repeater cells can be reduced. When the amount of movement of the repeater cell is large, the route change of the wiring between circuit blocks increases accordingly, and the number of detours increases in the wiring between circuit blocks after rewiring (FIG. 9). On the other hand, in the present embodiment, since the amount of movement of the repeater cell is small, the number of wiring detours is small (FIG. 7).

  The semiconductor layout system of the present embodiment includes a grouping processing unit 21, a repeater insertion base point determination unit 22, and a repeater insertion processing unit 23 as a minimum configuration. The grouping processing unit 21 refers to the wiring information storage unit 201, and among the circuit block wirings to be inserted into the repeater, the difference between the X coordinate or Y coordinate of the start point is within a predetermined distance and extends in parallel with each other. Inter-circuit block wiring having wiring portions is grouped. The repeater insertion base point determination unit 22 determines, as repeater insertion base point position information, the coordinates at positions where the distances from the start point coordinates are different from each other for the inter-circuit block wirings belonging to the same group. The repeater insertion processing unit 23 refers to the wiring information and the repeater insertion base point position information, determines the position of the repeater cell to be inserted into the inter-circuit block wiring to be inserted into the repeater, based on the repeater insertion base point, and repeater cell arrangement information And stored in the arrangement information storage unit 202.

  In the semiconductor layout system of the present embodiment, wiring between circuit blocks having a similar position as a starting point and portions extending in parallel are grouped, and the repeater insertion base point of the wiring between circuit blocks belonging to the group is set at a distance from the starting point. Set the coordinates at different positions. Thereafter, the repeater insertion position is determined based on the repeater insertion base point shifted from the start point. By doing in this way, it can prevent that a repeater insertion position overlaps between circuit blocks which have the part which extends in parallel with a similar position as a starting point. As a result, it is possible to reduce the number of repeater cells that need to be moved in the overlap unraveling process, and to reduce the amount of movement of the repeater cells. Further, by rewiring after moving the repeater cell, it is possible to reduce the number of wiring detours.

  Although the present invention has been described based on the preferred embodiment, the semiconductor layout system, method, and program of the present invention are not limited to the above embodiment, and various configurations are possible from the configuration of the above embodiment. Those modified and changed as described above are also included in the scope of the present invention.

20: data processing device 21: grouping processing unit 22: repeater insertion base point determination unit 23: repeater insertion processing unit 24: overlap unraveling processing unit 25: wiring unit 200: storage device 201: wiring information storage unit 202: arrangement information storage unit 501 to 503: circuit blocks 504 to 508: output terminals 509 to 512: input / output terminals 513 to 518: wiring between circuit blocks (net)

Claims (15)

With reference to the wiring information storage unit that stores wiring information of the wiring between the circuit blocks including the starting point coordinates and the ending point coordinates of the wiring, among the wirings between the circuit blocks to which the repeater is inserted, the starting point coordinates in the X direction coordinates or the Y direction coordinates A grouping processing unit for grouping wiring between circuit blocks having a wiring portion having a difference in coordinates within a predetermined distance and extending in parallel with each other;
For the inter-circuit block wiring belonging to the same group, the repeater insertion base point determination unit for determining the coordinates of the position where the distance from the start point coordinate is different from each other as a repeater insertion base point, and storing it as repeater insertion base point position information;
Refer to the wiring information and repeater insertion base position information, determine the position of a repeater cell to be inserted into the inter-circuit block wiring to be inserted into the repeater from the repeater insertion base point, and place information storage unit as repeater cell placement information A semiconductor layout system comprising: a repeater insertion processing unit stored in   The grouping processing unit sets, as a group candidate, an inter-circuit block wiring having a difference between the X-direction coordinate or the Y-direction coordinate within a predetermined distance among the circuit block wirings to be inserted into the repeater. 2. A length of a wiring portion extending in parallel with each other with respect to the wiring between circuit blocks is obtained, and wiring between circuit blocks having a length of the wiring portion extending in parallel with a predetermined length or more is grouped into the same group. The semiconductor layout system described in 1.   The grouping processing unit further calculates a Manhattan ratio of wiring between circuit blocks in which the length of the wiring portions extending in parallel is equal to or longer than a predetermined length, and compares the values of the Manhattan ratio with each other to determine a difference. The semiconductor layout system according to claim 2, wherein wirings between circuit blocks within a predetermined value are grouped into the same group.   The repeater insertion base point determination unit sets a predetermined shift length to α, and α × (i−1) (i = 1, 2,..., In the same group from the start point coordinates on the path between the circuit blocks. 4. The semiconductor layout system according to claim 1, wherein coordinates of a position apart from each other are determined as repeater insertion base points. 5. Referring to the wiring information storage unit and the arrangement information storage unit, an overlap unraveling process for moving the position of the repeater cell so as to eliminate the overlap between the repeater cells is performed, and a result of the overlap unraveling process is stored in the arrangement information storage An overlapping unraveling processing unit stored in the unit;
After the overlapping unraveling processing unit performs the overlapping unraveling processing, the wiring information storage unit and the placement information storage unit are referred to perform rewiring of the wiring between the circuit blocks, and the rewiring result is stored in the wiring information storage unit. The semiconductor layout system according to claim 1, further comprising a wiring unit for storing. The computer refers to the wiring information storage unit that stores the wiring information of the wiring between the circuit blocks including the starting point coordinates and the ending point coordinates of the wiring, and among the wirings between the circuit blocks to which the repeater is inserted, the coordinates in the X direction of the starting point coordinates or A grouping step for grouping wirings between circuit blocks having wiring portions that extend in parallel with each other, with a difference in coordinates in the Y direction within a predetermined distance; and
Repeater insertion base point determination step in which the computer determines the coordinates of the positions where the distances from the start point coordinates are different from each other for the inter-circuit block wirings belonging to the same group, as repeater insertion base point position information, ,
Refer to the wiring information and repeater insertion base position information, determine the position of a repeater cell to be inserted into the inter-circuit block wiring to be inserted into the repeater with the repeater insertion base point as a base point, and a placement information storage unit as repeater cell placement information A semiconductor layout method comprising: a repeater insertion step stored in the memory.   In the grouping step, the computer sets, as a group candidate, an inter-circuit block wiring having a difference between the X-direction coordinates or the Y-direction coordinates within a predetermined distance among the inter-circuit block wirings to be inserted into the repeater. Obtaining the length of the wiring portion extending in parallel with each other for the inter-circuit block wiring of the group candidate, and grouping the wiring between the circuit blocks in which the length of the wiring portion extending in parallel is equal to or longer than a predetermined length, The semiconductor layout method according to claim 6.   In the grouping step, the computer further calculates a Manhattan ratio of wiring between circuit blocks in which the length of the wiring portions extending in parallel is equal to or longer than a predetermined length, and compares the values of the Manhattan ratio with each other. The semiconductor layout method according to claim 7, wherein wiring between circuit blocks having a difference within a predetermined value is grouped into the same group.   In the repeater insertion base point determining step, the computer sets a predetermined shift length α, and α × (i−1) (i = 1, 2,...) From the start point coordinates on the path between the circuit blocks. 9. The semiconductor layout method according to claim 6, wherein the coordinates of the distant positions are determined as repeater insertion base points. The computer refers to the wiring information storage unit and the arrangement information storage unit, moves the position of the repeater cell so as to eliminate the overlap between the repeater cells, and stores the result of the movement in the arrangement information storage unit. The overlapping unwinding step to remember,
Subsequent to the overlapping unraveling step, the computer performs rewiring of the wiring between the circuit blocks with reference to the wiring information storage unit and the arrangement information storage unit, and stores the rewiring result in the wiring information storage unit. The semiconductor layout method according to claim 6, further comprising a rewiring step. On the computer,
With reference to the wiring information storage unit that stores wiring information of the wiring between the circuit blocks including the starting point coordinates and the ending point coordinates of the wiring, among the wirings between the circuit blocks to which the repeater is inserted, the starting point coordinates in the X direction coordinates or the Y direction coordinates A grouping process for grouping wiring between circuit blocks having a wiring portion having a coordinate difference within a predetermined distance and extending in parallel with each other;
For the inter-circuit block wiring belonging to the same group, the repeater insertion base point determination process for determining the coordinates of the position where the distance from the start point coordinate is different from each other as a repeater insertion base point, and storing as repeater insertion base point position information;
Refer to the wiring information and repeater insertion base position information, determine the position of a repeater cell to be inserted into the inter-circuit block wiring to be inserted into the repeater with the repeater insertion base point as a base point, and a placement information storage unit as repeater cell placement information A program for executing a repeater insertion procedure stored in the memory.   In the grouping process, among the inter-circuit block wirings to be inserted into the repeater, the inter-circuit block wirings having a difference in the X-direction coordinate or the Y-direction coordinate within a predetermined distance are set as group candidates, and the circuit of the group candidate 12. The length of the wiring part extending in parallel with each other for the inter-block wiring is obtained, and the wiring between the circuit blocks in which the length of the wiring part extending in parallel is equal to or longer than a predetermined length is grouped into the same group. The listed program.   In the grouping process, a Manhattan ratio of wiring between circuit blocks in which the length of the wiring portion extending in parallel is equal to or longer than a predetermined length is calculated, and the difference between the Manhattan ratio values is compared with each other. The program according to claim 12, wherein wiring between circuit blocks within a value of is grouped into the same group.   In the repeater insertion base point determination process, a predetermined shift length is α, and α × (i−1) (i = 1, 2,..., In the same group from the start point coordinates on the path between the circuit blocks. The program according to any one of claims 11 to 13, wherein coordinates of positions apart from each other are determined as repeater insertion base points. In the computer,
Referring to the wiring information storage unit and the arrangement information storage unit, the position of the repeater cell is moved so as to eliminate the overlap between the repeater cells, and the result of the movement is stored in the arrangement information storage unit. Processing,
Subsequent to the overlap unraveling process, rewiring is performed by referring to the wiring information storage unit and the placement information storage unit and rewiring the wiring between the circuit blocks, and storing a rewiring result in the wiring information storage unit. The program according to any one of claims 11 to 14, further executing:

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