JP2010183525A - Predistorter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively compensate distortion occurring in a second-order harmonic injection amplifier, in a predistorter for compensating for the distortions that occur in a second-order harmonic injection amplifier. <P>SOLUTION: In the predistorter (for instance, a memory-less PD 31a) for compensating for the distortions occurring in a second-order harmonic injection amplifier, an amplitude value detection means 41a (a fundamental wave amplitude detection part 51, a second-order harmonic amplitude detection part 52, a multiplier 53, an adder 54) detects the value of the result of adding amplitude, based on an input signal to amplitude based on its second-order harmonic signal; and a distortion compensation process execution means (a distortion compensation table 42, a PD executing part 43) executes processes for compensating for the distortion occurring in the second-order harmonic injection amplifier, based on the values detected by the amplitude value detection means 41a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a predistortion technique that compensates for non-linear distortion generated in, for example, a power amplifier (PA), and more particularly, to a predistorter that compensates for distortion generated in a second-order harmonic injection amplifier.

In recent years, demand for technological development for obtaining high power efficiency has been accelerated for power amplifiers for digital mobile communications. For example, various methods such as Doherty amplifier and LINC (Linear Amplifying using Nonlinear Components) have been researched and developed, and one of these methods is a second harmonic injection method (for example, Non-Patent Document 1). reference.).
In the second harmonic injection method, input waveform processing is performed by injecting a second harmonic whose amplitude and phase are adjusted to the input of an amplifier, and by performing a part of the class F operation that is a switching mode, Efficiency can be increased.

FIG. 1 shows a configuration example of a second harmonic injection amplifier.
The second-order harmonic injection amplifier of this example includes a coupler 1, a delay element (for example, delay line: Delay line) 2, a second-order harmonic generation unit 3, a combiner 4, and a power amplifier, for example. An amplifier (main amplifier) 5 is provided. The second harmonic generation unit 3 includes a square circuit 11, an amplifier 12, a variable phase shifter 3, and a variable attenuator 14.

The input signal is a radio frequency (RF) signal having a frequency f0 and is called a fundamental wave. A part of the fundamental wave is distributed by the coupler 1 and input to the delay element 2 and the second harmonic generation unit 3. In the second harmonic generation unit 3, a second harmonic is generated by the square circuit 11 for the input signal. The output signal from the square circuit 11 is a signal (second harmonic) having a frequency of 2f0. Next, the second harmonic is amplified by the amplifier 12. In order to perform the class F operation, the phase of the amplified signal is adjusted by the variable phase shifter 13 and the amplitude is adjusted by the variable attenuator 14.
Here, when the amplitude of the output signal from the square circuit 11 is sufficiently large, the amplifier 12 is unnecessary and may not be provided. Further, the variable phase shifter 13 and the variable attenuator 14 have the function of vector adjustment, and the same effect can be obtained even if the configuration order is changed.
Further, instead of the square circuit 11, for example, a configuration using a diode or a field effect transistor (FET) that generates a second harmonic may be used.

  The delay element 2 adjusts the delay time of the input signal (fundamental wave). The synthesizer 4 synthesizes the fundamental wave whose timing is adjusted by the delay element 2 and the second harmonic from the second harmonic generation unit 3 (variable attenuator 14), and the main amplifier 5 To amplify the power. At this time, the fundamental wave is output from the main amplifier (amplifier) 5 and the second harmonic is reflected and operated in class F, so that the power efficiency is improved.

  On the other hand, the power amplifier is also required to have high linearity, that is, low nonlinear distortion. The back-off method is a method in which the operating point is lowered and the linear region is used, but it cannot be adopted at a low operating point because power efficiency is lowered. The feed forward method can obtain high linearity, but it is necessary to provide an error amplifier, and power consumption increases. The pre-distortion (PD: Pre-Distortion) method is a method for compensating a nonlinear characteristic by giving an inverse characteristic of the nonlinear characteristic to an input signal of an amplifier in advance. In particular, the PD method is realized by digital signal processing. The DPD (Digital PD) method is currently mainstream because it consumes little power.

FIG. 2 shows a configuration example of a power amplifier with DPD.
The power amplifier with DPD of this example includes a digital predistortion (DPD) unit 21, a D / A (Digital to Analog) converter 22, an up converter 23, a power amplifier (PA) 24, and a directional coupler 25. A down converter 26, an A / D (Analog to Digital) converter 27, and a control unit 28.

  The DPD unit 21 is disposed in a digital unit that is upstream of the power amplifier 24, performs predistortion processing on the input signal, and outputs the signal to the D / A converter 22. The D / A converter 22 converts an output signal from the DPD unit 21 that is a digital signal into an analog signal and outputs the analog signal. The up-converter 23 converts the output signal from the D / A converter 22 into a radio frequency signal and outputs it. The power amplifier 24 performs power amplification on the output signal from the up-converter 23 and outputs it. At this time, non-linear distortion occurs in the power amplifier 24, but since the DPD unit 21 previously gives the inverse characteristic of the non-linear characteristic to the signal, the output signal from the power amplifier 24 is a signal whose distortion has been compensated.

  Part of the output signal from the power amplifier 24 is distributed by the directional coupler 25, frequency-converted by the down converter 26, converted to a digital signal by the A / D converter 27, and input (feedback) to the control unit 28. Is done. For example, the control unit 28 measures distortion power of a signal (feedback signal) from the A / D converter 27 and compares the waveform of the input signal and the feedback signal (in this case, the input signal is input to the control unit 28). The inverse characteristics of the non-linear characteristics are updated with respect to the DPD unit 21, so that the DPD unit 21 can always obtain good linearity by following the temperature change and the secular change. To control.

FIG. 3 shows a configuration example of the memoryless DPD.
The memoryless DPD of this example includes an envelope detection unit 41 as a processing unit of a memoryless predistorter (memoryless PD) 31, and a distortion compensation table 42 configured by a memory or the like, for example, configured as a LUT (Look Up Table). PD execution unit 43 is provided.
Here, the memoryless PD uses a general PD method that compensates for AM-AM conversion and AM-PM conversion that do not include a memory effect. Input signals of the memoryless PD 31 are I-phase and Q-phase digital signals, which are baseband signals.

  The amplitude of the input signal is calculated (detected) by the envelope detector 41, and the result is input to the distortion compensation table 42. In the distortion compensation table 42, output values are associated with the amplitude calculated by the envelope detector 41 as a reference argument, and an output value corresponding to the amplitude is output. Specifically, the distortion compensation table 42 stores information on the inverse characteristic of the nonlinear characteristic of the amplifier to be compensated. Generally, the AM-AM characteristic (amplitude) using the amplitude of the input signal as an index. , Information on AM-PM characteristics (phase) is stored. The PD execution unit 43 includes a complex multiplier and compensates the amplitude and phase of the input signal according to the reference result (output value) of the distortion compensation table 42.

  Although not shown, the output signal from the PD execution unit 43 is converted into an analog signal by a D / A converter and converted into a radio frequency signal by an up converter. In a signal to which the inverse characteristic of the nonlinear characteristic is given in advance by the PD method, when amplified by the amplifier, the distortion generated by the amplifier and the distortion given by the inverse characteristic cancel each other, so the output signal from the amplifier is The signal is compensated for distortion. Generally, a feedback unit is further provided, and a part of the output signal from the amplifier is fed back, and the distortion compensation table 42 is updated, so that the distortion compensation performance can be improved by adapting to temperature change and aging change. maintain.

International Publication No. 2006/087864 Pamphlet JP 2004-072331 A

"High efficiency of GaN PA using second harmonic injection", Kawanabe et al., 2008 IEICE General Conference, C-2-36, 2008

As described above, in order to achieve high power efficiency and low nonlinear distortion, studies have been made from both sides, and the technology has advanced.
However, there is a problem in that sufficient distortion compensation performance cannot be obtained with the conventional DPD method against nonlinear distortion of PA using the second harmonic injection method with good power efficiency. Specifically, since the input signal of such a PA is a signal obtained by adding the second harmonic in the analog part to the fundamental wave, AM-AM conversion and AM-PM including the amplitude of the second harmonic. Although conversion occurs, the digital unit that realizes DPD processes such a problem as it cannot process only the fundamental wave signal and compensate for distortion caused by the influence of the second harmonic.

  The present invention has been made in view of such a conventional situation, and an object thereof is to provide a predistorter capable of effectively compensating for distortion generated in a second harmonic injection amplifier.

In order to achieve the above object, in the present invention, a predistorter for compensating for distortion generated in the second harmonic injection amplifier has the following configuration.
In other words, the amplitude value detection means detects a value obtained by adding the amplitude based on the input signal and the amplitude based on the second harmonic signal (second harmonic signal of the input signal). A distortion compensation processing execution unit executes a process for compensating for distortion generated in the second harmonic injection amplifier based on the value detected by the amplitude value detection unit.
Therefore, the distortion generated in the second harmonic injection amplifier can be effectively compensated by the predistortion method.

Here, various types of second harmonic injection amplifiers to be subjected to distortion compensation may be used. It should be noted that the second harmonic injection amplifier to be subjected to distortion compensation is arranged at a stage subsequent to the predistorter (may be via another circuit).
Various predistorters may be used. For example, the predistorter compensates for distortion of the AM-AM characteristic (amplitude) and AM-PM characteristic (phase) generated in the amplifier, or is generated in the amplifier. It is possible to use one that compensates for the distortion of the memory effect, or one that compensates for both of these distortions.
Various processes may be used as a process for compensating for distortion generated in the amplifier. For example, a signal value corresponding to a value detected by the amplitude value detecting means or obtained from the signal value is used. Processing that performs a predetermined operation (for example, multiplication or addition) on the input signal using the value can be used.

As one configuration example, the predistorter according to the present invention has the following configuration.
That is, the amplitude value detecting means adjusts the amplitude of the second harmonic signal based on the amplitude ratio between the fundamental wave amplified by the second harmonic injection amplifier (its main amplifier) and the second harmonic. Having amplitude adjusting means,
As the amplitude based on the input signal, the amplitude of the input signal is used,
As the amplitude based on the second harmonic signal, the amplitude adjusted by the amplitude adjusting means is used.
Therefore, more effective distortion compensation can be performed by the amplitude adjusting means.

  As described above, according to the predistorter according to the present invention, by performing distortion compensation in consideration of the amplitude of the input signal and the second harmonic signal, distortion generated in the second harmonic injection amplifier is reduced. It can compensate effectively.

It is a figure which shows the structural example of a 2nd harmonic injection amplifier. It is a figure which shows the structural example of the power amplifier with DPD. It is a figure which shows the structural example of memoryless DPD. It is a figure which shows the structural example of the amplitude detection part which concerns on 1st Example of this invention. It is a figure which shows the structural example of the amplitude detection part which concerns on 2nd Example of this invention. It is a figure which shows the structural example of the memoryless predistorter (memoryless PD) which concerns on 3rd Example of this invention. It is a figure which shows the structural example of the memory predistorter (memory PD) which concerns on 4th Example of this invention. It is a figure which shows the structural example of the predistorter by which memoryless PD and memory PD which concern on 5th Example of this invention were arranged in series. It is a figure which shows the structural example of the predistorter by which memoryless PD and memory PD which concern on 6th Example of this invention were arranged in parallel. (A) is a figure which shows an example of a class F amplifier, (b) is a figure which shows another example of a class F amplifier, (c) is an example of the theoretical waveforms of the voltage and current in a class F amplifier FIG. It is a figure which shows the structural example of the high frequency power amplifier which uses a Doherty amplifier. It is a figure which shows the other structural example of the high frequency power amplifier which uses a Doherty amplifier.

Embodiments according to the present invention will be described with reference to the drawings.
The predistorter according to the present embodiment is intended for a second harmonic injection amplifier. As the amplitude value of the input side signal referred to by the predistorter, the amplitude of the input signal and the second harmonic signal thereof are used. A value obtained by adding the amplitude is used. As a further configuration example, the amplitude value of the added second harmonic signal is appropriately adjusted according to the amplitude ratio α of the fundamental wave and the second harmonic amplified by the main amplifier (main amplifier).
Here, the predistorter according to the present embodiment can be applied to various second harmonic injection amplifiers, and can be applied to, for example, those shown in FIG. 1, FIG. 11, and FIG. is there.

In the predistorter according to the present embodiment, the amount of amplitude and phase to be adjusted by predistortion is determined based on a value obtained by adding the amplitude of the input signal and the amplitude of the second harmonic of the input signal.
Further, the predistorter according to the present embodiment has a function of adjusting the amplitude of the second harmonic.

  In this embodiment, for example, a DPD having an amplitude detection unit (envelope detection unit) that takes into account that a second harmonic is input to a power amplifier is provided. Further, it is realized by referring to the distortion compensation table with the amplitude including the second harmonic. Also, depending on the characteristics of the power amplifier and the matching circuit, it has a function of adjusting the amplitude of the second harmonic in order to maintain the DPD performance even when the gain of the fundamental wave and the second harmonic is different.

A first embodiment of the present invention will be described.
In this example, a configuration example of the amplitude detector of the predistorter according to an embodiment of the present invention is shown.
FIG. 4 shows a configuration example of the amplitude detector.
The amplitude detection unit of this example includes a fundamental wave amplitude detection unit 51, a second harmonic amplitude detection unit 52, a multiplier 53, and an adder 54.

The fundamental wave amplitude detection unit 51 calculates the fundamental wave amplitude A1 according to (Equation 1). In (Formula 1), sqrt represents a square root (root: √). I represents the I component of the input signal, and Q represents the Q component of the input signal.
(Equation 1)
A1 = sqrt (I ² + Q ² ) (1)

The second harmonic amplitude detector 52 calculates the second harmonic amplitude A2 by (Equation 2).
(Equation 2)
A2 = I ² + Q ² .. (Formula 2)

The multiplier 53 multiplies the amplitude of the second harmonic calculated by the second harmonic amplitude detection unit 52 by the amplitude adjustment ratio α between the fundamental wave and the second harmonic. The multiplication result A3 is expressed by (Equation 3).
(Equation 3)
A3 = α · (I ² + Q ² ) (Equation 3)

Here, the amplitude adjustment ratio α is the amplitude ratio between the fundamental wave and the second harmonic of the signal amplified by the main amplifier (for example, the main amplifier 5 shown in FIG. 1), and generates nonlinear distortion (AM / AM Characteristic, AM / PM characteristic, etc.). The amplitude ratio (amplitude adjustment ratio) α varies depending on the power amplification element and the amplitude ratio between the fundamental wave and the second harmonic input to the main amplifier. Adjust for good performance.
As an example, the amplitude adjustment ratio α is previously set and stored in a memory such as a PD. As another example, a configuration in which the amplitude adjustment ratio α can be changed automatically or manually may be used.

The adder 54 adds the amplitude of the fundamental wave and the amplitude of the second harmonic whose amplitude has been adjusted. The output signal A4 from the adder 54 is expressed by (Equation 4).
(Equation 4)
A4 = sqrt (I ² + Q ² ) + α · (I ² + Q ² ) (Formula 4)

  By referring to a distortion compensation table (for example, look-up table: LUT) by the added value A4, it is possible to compensate for nonlinearity caused by the input of the second harmonic.

As described above, in the predistorter of this example, as an example, the amplitude adjustment unit that does not perform amplitude adjustment (when the multiplier 53 is not provided), as the amplitude adjustment unit 51 that calculates the amplitude of the input signal, A second harmonic amplitude detector 52 that calculates the amplitude of the second harmonic of the input signal, and an adder 54 that adds the output of the fundamental amplitude detector 51 and the output of the second harmonic amplitude detector 52. Prepared.
In addition, in the predistorter of this example, as another example, as an amplitude adjustment unit that performs amplitude adjustment, a fundamental wave amplitude detection unit 51 that calculates the amplitude of the input signal and the amplitude of the second harmonic of the input signal are calculated. The second harmonic amplitude detector 52, the multiplier 53 for adjusting the amplitude of the output of the second harmonic amplitude detector 52, the output of the fundamental amplitude detector 51 and the output of the multiplier 53 are added. An adder 54 is provided.
Therefore, in the predistorter of this example, the distortion compensation performance of the nonlinear distortion of the second harmonic injection PA can be improved, thereby achieving high power efficiency and low nonlinear distortion of the power amplifier.

A second embodiment of the present invention will be described.
In this example, a configuration example of the amplitude detector of the predistorter according to an embodiment of the present invention is shown.
FIG. 5 shows a configuration example of the amplitude detection unit.
The amplitude detection unit of this example includes a second harmonic amplitude detection unit 61, a square root calculation unit 62, a multiplier 63, and an adder 64.

The second harmonic amplitude detector 61 calculates the second harmonic amplitude A5 by (Equation 5). Here, I represents the I component of the input signal, and Q represents the Q component of the input signal.
(Equation 5)
A5 = I ² + Q ² .. (Formula 5)

The square root calculation unit 62 calculates the fundamental wave amplitude A6 by taking the square root of the second harmonic amplitude A5 according to (Equation 6). In (Expression 6), sqrt represents a square root (root: √).
(Equation 6)
A6 = sqrt (I ² + Q ² ) (Expression 6)

The multiplier 63 multiplies the amplitude of the second harmonic calculated by the second harmonic amplitude detector 61 by the amplitude adjustment ratio α between the fundamental wave and the second harmonic. The multiplication result A7 is expressed by (Equation 7).
(Equation 7)
A7 = α · (I ² + Q ² ) (Equation 7)

The adder 64 adds the amplitude of the fundamental wave and the amplitude of the second harmonic whose amplitude is adjusted. The output signal A8 from the adder 64 is expressed by (Equation 8).
(Equation 8)
A8 = sqrt (I ² + Q ² ) + α · (I ² + Q ² ) (Equation 8)

By referring to a distortion compensation table (for example, look-up table: LUT) with the added value A8, it is possible to compensate for nonlinearity caused by the input of the second harmonic.
Here, the amplitude detector shown in FIG. 4 and the amplitude detector shown in FIG. 5 have the same function as a result. The amplitude detector may be realized by other methods other than those shown in FIGS. 4 and 5. For example, the amplitude of the second harmonic whose amplitude is adjusted to the amplitude of the fundamental wave by the amplitude detector. Those having the function of outputting a value obtained by adding are included in the technical idea of the present application.

As described above, in the predistorter of the present example, as an example, a secondary that calculates the amplitude of the second harmonic of the input signal as an amplitude adjusting unit that does not perform amplitude adjustment (when the multiplier 63 is not provided). Harmonic amplitude detector 61, square root calculator 62 for calculating the square root of the output of second harmonic amplitude detector 61, and addition for adding the output of second harmonic amplitude detector 61 and the output of square root calculator A vessel 64 was provided.
Moreover, in the predistorter of this example, as another example, as an amplitude adjustment unit that performs amplitude adjustment, a second harmonic amplitude detection unit 61 that calculates the amplitude of the second harmonic of the input signal, and the second harmonic The square root calculation unit 62 for calculating the square root of the output of the amplitude detection unit 61, the multiplier 63 for adjusting the amplitude of the output of the second harmonic amplitude detection unit 61, the output of the multiplier 63 and the square root calculation unit 62 An adder 64 for adding the output is provided.
Therefore, in the predistorter of this example, the distortion compensation performance of the nonlinear distortion of the second harmonic injection PA can be improved, thereby achieving high power efficiency and low nonlinear distortion of the power amplifier.

A third embodiment of the present invention will be described.
FIG. 6 shows a configuration example of a memoryless predistorter (memoryless PD) 31a according to an embodiment of the present invention. Note that the memoryless PD 31a of this example is a DPD.
Here, the configuration of the memoryless PD 31a of this example is an example, and is not limited thereto, and may be applied to various memoryless PDs.

  The memoryless PD 31a of this example generally has a configuration similar to that shown in FIG. 3, and includes an envelope detection unit 41a, a distortion compensation table 42, and a PD execution unit 43 (for example, a complex multiplier). ). In this example, the same envelope detector 41a as the amplitude detector shown in FIG. 4 is used.

In this example, the amplitude detected by the envelope detector 41 a having the configuration shown in FIG. 4 is used as a reference argument of the distortion compensation table 42. The input signal is composed of an I component and a Q component.
The PD execution unit 43 multiplies the input signal and the output signal from the distortion compensation table 42, and outputs the result as a signal after memoryless predistortion.
Therefore, in the memoryless PD 31a of this example, the distortion compensation performance of the second harmonic injection amplifier can be improved.
Here, as another configuration example, an equivalent function can be realized even in a configuration using the envelope detection unit shown in FIG.

  As described above, in the memoryless PD 31a of this example, the data stored in the referenced memory is obtained using the output signal from the envelope detection unit (amplitude detection unit) as shown in FIG. 4 or 5 as a reference argument. A distortion compensation table 42 to output, and a PD execution unit 43 that multiplies the input signal and the output from the distortion compensation table 42 are provided.

In the memoryless PD 31a of this example (an example of a predistorter), an envelope detection comprising a fundamental wave amplitude detector 51, a second harmonic amplitude detector 52, a multiplier 53 constituting an amplitude adjusting means, and an adder 54. The amplitude value detection means is configured by the unit (amplitude detection unit) 41a, and the distortion compensation processing execution means is configured by the distortion compensation table 42 and the PD execution unit 43.
When the configuration shown in FIG. 5 is used as the amplitude value detecting means, the multiplier 63 constitutes an amplitude adjusting means.

A fourth embodiment of the present invention will be described.
FIG. 7 shows a configuration example of a memory predistorter (memory PD) 71 and an adder 72 for compensating for the memory effect according to an embodiment of the present invention. The memory PD 71 in this example is a DPD.
Here, the configuration of the memory PD 71 of this example is, for example, an example described in Patent Document 1, and is not limited thereto, and may be applied to various memories PD.

  The memory PD 71 of this example includes an envelope detection unit 81, a distortion compensation table (for example, LUT) 82 including a memory, a delay unit 83 for one sample, an adder 84, and a multiplier 85. Yes. In this example, the envelope detector 81 is the same as the amplitude detector shown in FIG.

The envelope detector 81 calculates the amplitude of the input signal composed of the I component and the Q component in consideration of the second harmonic, and outputs the result to the distortion compensation table 82.
In the distortion compensation table 82, the amplitude calculated by the envelope detector 81 is used as a reference argument, an output value for compensating for the memory effect is associated, and an output value corresponding to the amplitude is output.

The delay unit 83 delays the output signal from the distortion compensation table 82 by one sample period and outputs it to the adder 84.
The adder 84 subtracts the signal delayed by one sample period from the delay unit 83 from the output signal from the distortion compensation table 82 and outputs the result to the multiplier 85.
Multiplier 85 multiplies the input signal and the output signal from adder 84 and outputs the result to adder 72.
The adder 72 adds the input signal and the output signal from the multiplier 85, and outputs the result as a signal after predistortion related to the memory effect.

Therefore, in the memory PD 71 of this example, it is possible to effectively compensate for the nonlinear distortion generated by the memory effect of the second harmonic injection amplifier.
Here, as another configuration example, an equivalent function can be realized even in a configuration using the envelope detection unit shown in FIG.

  As described above, the memory PD 71 of this example outputs the data stored in the referenced memory using the output signal from the envelope detection unit (amplitude detection unit) as shown in FIG. 4 or 5 as a reference argument. A distortion compensation table 82 for delaying, a delay unit 83 for delaying the output from the distortion compensation table 82, and an adder (may be a subtractor) 84 for subtracting the output signal from the delay unit 83 from the output signal from the distortion compensation table 82. And a multiplier (complex multiplier) 85 that multiplies the input signal and the output signal from the adder 84, and further multiplies the input signal as a processing unit for reflecting the output from the memory PD 71 in the input signal. An adder 72 for adding the output signal from the device 85 is provided.

  In the memory PD 71 (an example of a predistorter) of this example, an envelope detection unit including a fundamental wave amplitude detection unit 51, a second harmonic amplitude detection unit 52, a multiplier 53 constituting an amplitude adjustment unit, and an adder 54. The (amplitude detection unit) 81 constitutes an amplitude value detection means, and the distortion compensation table 82, the delay unit 83, the adder 84, and the multiplier 85 (in addition, the function of the adder 72 is included in the predistorter. The distortion compensation processing execution means may be configured.

A fifth embodiment of the present invention will be described.
FIG. 8 shows a configuration example of a predistorter in which a memoryless PD and a memory PD according to an embodiment of the present invention are arranged in series.
The predistorter of this example includes, for example, a memoryless PD 31a similar to that shown in FIG. 6, and a memory PD 71 and an adder 72 similar to those shown in FIG.

The memoryless PD 31a performs processing for compensating AM-AM conversion and AM-PM conversion for a second-order harmonic injection amplifier (not shown) in the subsequent stage, which is a distortion compensation target, for an input signal composed of an I component and a Q component. And outputs the processed signal to the memory PD 71 and the adder 72.
The memory PD 71 performs a process for compensating for the memory effect related to the second-order harmonic injection amplifier (not shown) in the subsequent stage that is a distortion compensation target for the input signal from the memoryless PD 31 a and adds the signal after the process Output to the device 72.
The adder 72 adds the signal from the memoryless PD 31a and the signal from the memory PD 71 and outputs the result. This output signal is input and amplified through a D / A converter or an up-converter, for example, to a subsequent second-order harmonic injection amplifier that is a distortion compensation target.

  Therefore, the predistorter of this example can compensate for the AM-AM conversion, AM-PM conversion, and memory effect. For example, nonlinear distortion can be effectively compensated by appropriately learning the value of the distortion compensation table of the memoryless PD 31a and the value of the distortion compensation table of the memory PD 71.

A sixth embodiment of the present invention will be described.
FIG. 9 shows a configuration example of a predistorter in which memoryless PDs and memory PDs according to an embodiment of the present invention are arranged in parallel.
The predistorter of this example includes, for example, a memoryless PD 31a similar to that shown in FIG. 6, a memory PD 71a having the same configuration as that shown in FIG. 7, and an adder 72.

The memoryless PD 31a performs processing for compensating AM-AM conversion and AM-PM conversion for a second-order harmonic injection amplifier (not shown) in the subsequent stage, which is a distortion compensation target, for an input signal composed of an I component and a Q component. And outputs the processed signal to the adder 72.
The memory PD 71 a performs a process for compensating the memory effect related to the second-order harmonic injection amplifier (not shown) in the subsequent stage, which is a distortion compensation target, for the input signal, and outputs the processed signal to the adder 72. .
The adder 72 adds the signal from the memoryless PD 31a and the signal from the memory PD 71a and outputs the result. This output signal is input and amplified through a D / A converter or an up-converter, for example, to a subsequent second-order harmonic injection amplifier that is a distortion compensation target.

  Therefore, the predistorter of this example can compensate for the AM-AM conversion, AM-PM conversion, and memory effect. For example, nonlinear distortion can be effectively compensated by appropriately learning the value of the distortion compensation table of the memoryless PD 31a and the value of the distortion compensation table of the memory PD 71a.

Here, in the above embodiment, an example of DPD using a distortion compensation table (for example, LUT) has been shown, but instead, for example, a configuration in which calculation is performed by a digital circuit may be used.
Further, various other configurations (for example, various known configurations) may be used as the memoryless DPD and the memory DPD.
The processing according to the above embodiments may be realized using software, for example.

(Hereinafter, description of the second harmonic injection amplifier)
Hereinafter, the second harmonic injection amplifier will be described.
First, a class F amplifier will be described with reference to FIGS. 10 (a), 10 (b), and 10 (c).
FIG. 10A shows a configuration example of a class F amplifier.
The class F amplifier of this example includes an input terminal 101, an output terminal 102, an input matching circuit 103, a field effect transistor (FET) 104, an output matching circuit 105, and a harmonic reflection circuit 106.

  The input matching circuit 103 is an impedance conversion circuit, and realizes impedance matching between the input impedance of the FET 104 and the characteristic impedance Z0 for the input signal. The output matching circuit 105 is an impedance conversion circuit, and realizes impedance matching between the output impedance of the FET 104 and the characteristic impedance Z0 with respect to the fundamental frequency f0.

The FET 104 is an active element that amplifies and outputs an input signal, the input signal is applied to the gate terminal, and the source terminal is grounded. Here, as the active element, for example, a bipolar transistor or an electron tube may be used instead of the FET.
The harmonic reflection circuit 106 is connected to the drain terminal of the FET 104 and has an impedance characteristic that is open to the fundamental frequency and the odd-order harmonic frequency and short-circuited to the even-order harmonic frequency. . As a result, the impedance frequency characteristics of the load at the output terminal (drain terminal) of the FET 104 are matched at the fundamental frequency, short-circuited at the even-order harmonic frequency, and open at the odd-order harmonic frequency.

  An input signal is input from the input terminal 101 to the gate terminal of the FET 104 via the input matching circuit 103. The signal amplified by the FET 104 is output from the output terminal 102 via the output matching circuit 105 from the drain terminal. The odd-order harmonics generated by the FET 104 are reflected by the harmonic reflection circuit 106 and input to the FET 104 to be further amplified.

FIG. 10 (c) shows an example of theoretical waveforms of voltage and current in the class F amplifier.
As shown in FIG. 10C, when the FET 104 of the amplifier shown in FIG. 10A is operated under a class B bias condition and a sine wave having a fundamental frequency is input, theoretically, the drain terminal, the source terminal, The time waveform of the voltage between is a rectangular wave having only a fundamental wave and odd harmonic components. In addition, the time waveform of the current between the drain terminal and the source terminal is a half waveform having only the fundamental wave and the even harmonic components.

  In the operation of the FET 104 at this time, the drain voltage becomes zero when the drain current is flowing, and conversely, the drain current becomes zero when the drain voltage is applied. The power consumption can be always zero. That is, as shown in FIG. 10C, in the state where the time waveforms of voltage and current do not overlap, the power consumed by the FET 104 can be made zero, and the internal loss can be suppressed.

  Contrary to the class F amplifier described above, matching is performed at the fundamental frequency, open at the even harmonic frequency, and shorted at the odd harmonic frequency, which is the reverse of the waveform shown in FIG. Some amplifiers can obtain waveforms. In such an amplifier, the harmonic reflection circuit reflects even-order harmonics. Also in this case, the drain voltage becomes zero when the drain current is flowing, and conversely, the drain current becomes zero when the drain voltage is applied, so the power consumption between the drain terminal and the source terminal Can always be zero.

  When configuring a high-frequency class F amplifier with a harmonic reflection circuit inserted outside the package, not only the fundamental frequency but also the secondary harmonic frequency is affected by the effects of the FET package, wire bonding, etc. A circuit configuration that takes into account the presence of reactance and the impedance of the FET chip itself is required.

Here, a second-order harmonic frequency is used to avoid the effects of various stray reactances due to the presence of the FET and its package, and to improve efficiency (class F amplifier having a configuration different from the above) Class F amplifier).
FIG. 10B shows a configuration example of such a class F amplifier.
The class F amplifier of this example includes an input terminal 111, an output terminal 112, an input matching circuit 113, an FET 114, an output matching circuit 115, and a harmonic reflection circuit 116.

The harmonic reflection circuit 116 is a termination circuit connected in parallel between the output matching circuit 115 and the output terminal 112, and has a high input impedance with respect to the frequency of the input signal. And low input impedance.
The input matching circuit 113 has an impedance characteristic that conjugate-matches with the input impedance of the FET 114 for both the frequency of the input signal and its second harmonic frequency. The output matching circuit 115 has an impedance characteristic that conjugate-matches with the output impedance of the FET 114 for both the frequency of the input signal and its second harmonic frequency.
These points are different from the amplifier shown in FIG.
Then, the second harmonic signal (second harmonic) generated at the drain terminal of the FET 114 is reflected to the FET 114 by the harmonic reflection circuit 116 at the end, and the voltage waveform is made close to a rectangular wave, which is necessary for high-efficiency operation. Switching operation can be realized.

Next, a high frequency power amplifier (an example of a secondary high frequency injection amplifier) using the class F amplifier shown in FIG. 10A will be described.
The high-frequency power amplifier of this example has a configuration similar to that of the amplifier shown in FIG. The amplifier 12 may not be provided. Further, as the main amplifier 5 shown in FIG. 1, a class F amplifier shown in FIG. 10A is used. Here, description will be made using reference numerals of the respective processing units shown in FIG.

  The harmonic reflection circuit 105 of the amplifier 5 is a high frequency termination circuit having a high input impedance with respect to the fundamental frequency and a low input impedance with respect to the second harmonic frequency. The position where the harmonic reflection circuit 105 is inserted should be closer to the amplification element in consideration of the loss of the line, but may not be as difficult as the conventional class F amplifier. Further, when using a high-power amplification element, the second harmonic reflection characteristic of the internal matching circuit may be used.

The harmonic generation circuit that is a characteristic part of the amplifier of this example is a circuit that amplifies the harmonic generated by the amplifier 5. In this example, the harmonic generation circuit is composed of an analog circuit with a simple configuration, and includes a vector adjustment circuit that adjusts the phase shift between the fundamental wave and the second harmonic and the required amplitude level ratio. The output level and phase of the harmonics necessary for the amplifier 5 can be accurately adjusted, and the amplification operation in the amplifier 5 can be performed with high efficiency.
In particular, in the amplifier of this example, paying attention to the second-order harmonic having a high level among the generated harmonics, the second-order harmonic is injected into the input of the amplifier, and the second-order harmonic is efficiently output by the harmonic reflection circuit. Since it is the structure which reflects a harmonic, the effect of an efficiency improvement becomes large.

In the amplifier of this example, since the second harmonic is included in the synthesized signal, the second harmonic generated at the drain terminal of the FET 104 is at a higher level than before, and the FET has less gain with respect to the harmonic. In addition, it can operate efficiently even at the time of low output with few harmonics.
Furthermore, since the harmonic reflection circuit 106 does not act on the fundamental frequency and reflects the second harmonic frequency, the harmonic reflection level of the output is further increased to reduce the overlap of voltage and current waveforms. Can improve efficiency.

  Here, the case where the amplifier 5 shown in FIG. 10A is used as the amplifier 5 is described above. However, as another configuration example, the amplifier 5 shown in FIG. 10B can also be used. It is. In this case, the input matching circuit 113 provided in the input stage of the FET 114 has an impedance characteristic that conjugate-matches with the input impedance of the FET 114 with respect to both the fundamental wave and the second harmonic frequency thereof. The output matching circuit 115 provided at the output stage of the FET 114 has impedance characteristics that conjugate-match with the output impedance of the FET 114 for both the fundamental wave and the second harmonic frequency. In this way, when the amplifier 5 shown in FIG. 10B is used, the input matching circuit 113 is matched not only to the fundamental wave but also to the second harmonic, and therefore from the harmonic generation circuit. The injection amount of the second-order harmonic can be smaller, and higher efficiency can be achieved.

  In the above description, the configuration for injecting the second harmonic has been described. However, it is also possible to further reduce the overlapping of the current and voltage waveforms by injecting the fourth and higher even harmonics. It is. In this case, for example, a harmonic generation circuit that generates higher harmonics of the fourth order may be provided in parallel with the second harmonic generation circuit. As the configuration of each harmonic generation circuit, for example, the same one as in the second-order case can be used, and the frequency of the generated harmonics may be changed.

As described above, the high-frequency power amplifier of this example is a high-frequency power amplifier that includes an amplifying element that amplifies an input high-frequency signal and a harmonic reflection circuit that reflects a harmonic frequency output from the amplifying element. There,
In the input stage of the amplifier,
A distributor for distributing an input signal having a fundamental frequency;
A harmonic generator for generating a second harmonic from the one of the distributed fundamental signals;
A regulator for adjusting the phase and amplitude of the second harmonic generated by the harmonic generator;
A circuit having a synthesizer that synthesizes the second harmonic wave whose phase and amplitude are adjusted and the other distributed fundamental wave signal and outputs the synthesized signal to the amplifier;
The harmonic reflection circuit has a characteristic of reflecting a second harmonic frequency.
Therefore, it is possible to optimize the voltage / current waveform by increasing the output level of the second harmonic output from the amplifying element and the reflection level of the second harmonic reflected by the harmonic reflection circuit, thereby improving the power efficiency. Can be improved.

Next, a high frequency power amplifier (an example of a secondary high frequency injection amplifier) using a Doherty amplifier will be described.
FIG. 11 shows a configuration example of a high frequency power amplifier using a Doherty amplifier.
In the high frequency power amplifier of this example, in the Doherty amplifier, the carrier amplifier circuit 126 and the peak amplifier circuit 127 are provided with the harmonic reflection circuits 144 and 154 that reflect the second harmonic, and the input signal is input to the input signal before the Doherty amplifier. A harmonic generation circuit 123 for injecting harmonics is provided.

Specifically, the high frequency power amplifier of this example includes an input terminal 121, an output terminal 122, a harmonic generation circuit 123, a distributor 124, a phase shifter 125, a carrier amplifier circuit 126, and a peak amplifier circuit. 127, a transmission line 128, a synthesis point 129, and a transmission line 130.
The carrier amplifier circuit 126 includes an input matching circuit 141, an FET 142, an output matching circuit 143, and a harmonic reflection circuit 144. The peak amplifier circuit 127 includes an input matching circuit 151, an FET 152, and an output matching circuit. 153 and a harmonic reflection circuit 154.

Here, as the harmonic generation circuit 123, for example, a circuit similar to that shown in FIG. 1 can be used.
Specifically, the harmonic generation circuit 123 generates a second harmonic from the fundamental wave of the input signal, adjusts the phase and amplitude of the generated second harmonic, and synthesizes it with the fundamental wave. A combined signal containing a lot of second harmonics is output to distributor 124. The harmonic generation circuit 123 amplifies the second harmonic generated by the Doherty amplifier, and the phase and amplitude of the second harmonic injected by the harmonic generation circuit 123 is the second harmonic generated by the Doherty amplifier. Vector adjustment is performed by a variable phase shifter and a variable attenuator so as to have an optimum relationship with the phase and amplitude of the wave.

  The output signal from the harmonic generation circuit 123 is distributed by the distributor 124, and one distribution signal is input to the carrier amplifier circuit 126, amplified by the FET 142, and impedance-converted by the transmission line 128 via the output matching circuit 143. The other distribution signal is adjusted by the phase shifter 125 according to the phase of the carrier amplifier circuit 126, input to the peak amplifier circuit 127, amplified by the FET 152, and converted in impedance by the output matching circuit 153. Is output.

  The harmonic reflection circuit 144 of the carrier amplification circuit 126 and the high frequency reflection circuit 154 of the peak amplification circuit 127 have impedance characteristics that reflect the second harmonic without affecting the fundamental wave. The position where the harmonic reflection circuits 144 and 154 are inserted should be closer to the amplification element in consideration of the loss of the line, but may not be as difficult as the conventional class F amplifier. Further, when using a high-power amplification element, the second harmonic reflection characteristic of the internal matching circuit may be used.

  At the combining point 129, the output from the transmission line 128 and the output from the peak amplifier circuit 127 are combined, and further, impedance is converted by the transmission line 130 to match an output load (not shown), and output from the output terminal 122. Connected to the output load.

  Here, the FET 142 of the carrier amplifier circuit 126 is biased to class AB, and the FET 152 of the peak amplifier circuit 127 is biased to class B or class C. For this reason, the FET 142 operates alone while the input level is low and the FET 152 does not operate. When the FET 142 enters the saturation region, that is, when the linearity of the FET 142 starts to break, the FET 152 starts to operate, the output of the FET 152 is supplied to the load, and the load is driven together with the FET 142. Thereby, in the Doherty amplifier, even when the output level is lower than the maximum output level, high efficiency can be obtained.

  In the amplifier of this example, since the signals input to the carrier amplifier circuit 126 and the peak amplifier circuit 127 of the Doherty amplifier include many second harmonics, the output level of the second harmonic increases, and the carrier amplifier 126 and The second-order harmonic reflection level reflected to the FETs 142 and 152 by the harmonic reflection circuits 144 and 154 of the peak amplifier 127 can be further increased, and the overlapping of the voltage and current waveforms can be reduced to improve the power efficiency. .

Conventionally, in order to adjust the phase and amplitude of the second harmonic, the harmonic reflection circuit must be adjusted, and the output matching circuit must be adjusted at the same time. Although it was difficult to match the harmonic matching at the same time, according to the amplifier of this example, the second harmonic is added to the input signal, and the phase and amplitude of the second harmonic are adjusted by the variable phase shifter and the variable attenuator. By adjusting, it becomes easy to match the matching of the fundamental wave and the second harmonic at the same time.
Furthermore, if a harmonic generation circuit that generates even-order harmonics of the fourth or higher order is provided in parallel with the harmonic generation circuit 123, and even-order harmonics of the fourth or higher order are injected into the input of the Doherty amplifier, Efficiency can be improved.

Next, another configuration example of a high frequency power amplifier (an example of a secondary high frequency injection amplifier) using a Doherty amplifier will be described.
FIG. 12 shows another configuration example of the high-frequency power amplifier using the Doherty amplifier.
In the high frequency power amplifier of this example, the second harmonic is injected only into the input of the carrier amplifier circuit 166 as compared with the amplifier shown in FIG.

Specifically, the high-frequency power amplifier of this example includes an input terminal 161, an output terminal 162, a distributor 163, a harmonic generation circuit 164, a phase shifter 165, a carrier amplification circuit 166, and a peak amplification circuit. 167, transmission line 168, synthesis point 169, and transmission line 170.
The carrier amplifier circuit 166 includes an input matching circuit 181, an FET 182, an output matching circuit 183, and a harmonic reflection circuit 184. The peak amplifier circuit 167 includes an input matching circuit 191, an FET 192, and an output matching circuit. 193.

  The amplifier harmonic generation circuit 164 of this example has the same configuration as that of the amplifier harmonic generation circuit 123 shown in FIG. 11, for example, and applies a second harmonic to the input signal to the carrier amplification circuit 166. inject. In the harmonic generation circuit 164 of the amplifier of this example, the phase and amplitude of the second harmonic injected by the harmonic generation circuit 164 are optimally related to the phase and amplitude of the second harmonic generated by the carrier amplification circuit 166. Thus, the phase and amplitude of the injected second harmonic are adjusted with a variable phase shifter and a variable attenuator.

In the Doherty amplifier, the efficiency is originally high in the region where the peak amplifier circuit 167 operates, and since the time during which the peak amplifier circuit 167 operates is short, the influence of the efficiency of the peak amplifier circuit 167 on the whole is not so great. In the amplifier of this example, by utilizing this fact, the harmonic reflection circuit of the peak amplification circuit 167 is not required as a configuration in which the second harmonic is injected only into the carrier amplification circuit 166, and for example, as shown in FIG. The power required for the injection of the second harmonic can be reduced as compared with the amplifier.
In the case where only the carrier amplifier circuit 166 is used to inject harmonics, the peak amplifier circuit 167 may be provided with a harmonic reflection circuit.

  Both the amplifier shown in FIG. 11 and the amplifier shown in FIG. 12 can achieve higher efficiency than the conventional Doherty amplifier over a wide range from low to high input power. In particular, the amplifier shown in FIG. 12 has higher efficiency than the amplifier shown in FIG. 11 at the input level where only the carrier amplifier circuit 166 operates. When the peak amplifier circuit 167 reaches a level at which the operation starts, the efficiency is somewhat lowered, but the overall influence is small.

  Here, as still another configuration example, when harmonics are injected into both the carrier amplifier circuit and the peak amplifier circuit, in addition to the configuration shown in FIG. 12, the phase shifter 165 and the peak amplifier circuit 167 It is possible to further increase the efficiency by inserting another harmonic generation circuit (not shown) into the carrier amplifier circuit 166 and the peak amplifier circuit 167 by injecting harmonics with different injection levels. It is.

As described above, as a high-frequency power amplifier using a Doherty amplifier, a carrier amplifier circuit having a first amplifier element operating in class AB and a peak amplifier circuit having a second amplifier element operating in class B or class C And a Doherty amplifier that combines and outputs the outputs of the carrier amplifier circuit and the peak amplifier circuit,
In the input stage of the carrier amplifier circuit,
A distributor for distributing an input signal having a fundamental frequency;
A harmonic generator for generating a second harmonic from the one of the distributed fundamental signals;
A regulator for adjusting the phase and amplitude of the second harmonic generated by the harmonic generator;
A circuit having a synthesizer that synthesizes the second harmonic wave whose phase and amplitude are adjusted and the other distributed fundamental wave signal and outputs the synthesized signal to the carrier amplifier circuit;
The carrier amplification circuit includes a harmonic reflection circuit that reflects the second harmonic frequency output from the first amplification element.
Therefore, it is possible to optimize the voltage / current waveform of the carrier amplifier circuit by increasing the output level of the second harmonic output from the carrier amplifier and the reflection level of the second harmonic reflected by the harmonic reflection circuit. In particular, the power efficiency of the entire Doherty amplifier can be greatly improved in a wide input level region in which only the carrier amplification element operates.
(End of description of second harmonic injection amplifier)

Here, the configuration of the system and apparatus according to the present invention is not necessarily limited to the configuration described above, and various configurations may be used. The present invention can also be provided as, for example, a method or method for executing the processing according to the present invention, a program for realizing such a method or method, or a recording medium for recording the program. It is also possible to provide various systems and devices.
The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.
In addition, as various processes performed in the system and apparatus according to the present invention, for example, the processor executes a control program stored in a ROM (Read Only Memory) in hardware resources including a processor and a memory. A controlled configuration may be used, and for example, each functional unit for executing the processing may be configured as an independent hardware circuit.
The present invention can also be understood as a computer-readable recording medium such as a floppy (registered trademark) disk or a CD (Compact Disc) -ROM storing the control program, and the program (itself). The processing according to the present invention can be performed by inputting the program from the recording medium to the computer and causing the processor to execute the program.

1 ·· Coupler, 2 ·· Delay element 3 ·· Second harmonic generation unit 4 ·· Synthesizer 5 · Main amplifier (amplifier) 11 ·· Square circuit 12 ·· Amplifier 13 ··· Variable phase shifter, 14 ... Variable attenuator, 21 ... Digital predistortion unit, 22.D / A converter, 23 ... Frequency conversion unit (upconverter), 24 ... Power amplifier, 25 ... Directivity Coupler 26 ·· Frequency converter (downconverter) 27 · · A / D converter 28 · · Control unit 31, 31a · · Memoryless predistorter 41 · 41a · 81 · · Envelope detector ( Amplitude detector), 42, 82 .. Distortion compensation table, 43 .. PD execution unit (multiplier), 51. Fundamental wave amplitude detector, 52, 61 .. Second harmonic amplitude detector, 53, 63 , 85 .. Multiplier, 5 , 64,72,84 ... adder, 62 ... square root unit, 71, 71a ... Memory predistorter, 83 ... delay unit,
101, 111, 121, 161 ... Input terminal 102, 112, 122, 162 ... Output terminal 103, 113, 141, 151, 181, 191 ... Input matching circuit 104, 114, 142, 152, 182 , 192,..., FET, 105, 115, 143, 153, 183, 193, output matching circuit, 106, 116, 144, 154, 184, harmonic reflection circuit, 123, 164, harmonic generation circuit, 124 163, .. Divider, 125, 165 ... Phase shifter, 126, 166 ... Carrier amplification circuit, 127, 167 ... Peak amplification circuit, 128, 130, 168, 170 ... Transmission line, 129, 169 ...・ Composite point,

Claims (1)

A predistorter that compensates for distortion generated in a second harmonic injection amplifier,
An amplitude value detecting means for detecting a value obtained by adding the amplitude based on the input signal and the amplitude based on the second harmonic signal;
Distortion compensation processing execution means for executing processing for compensating for distortion generated in the second harmonic injection amplifier based on the value detected by the amplitude value detection means;
A predistorter characterized by comprising:

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