JP2010182797A - Semiconductor wafer processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer processing device, capable of performing uniform processing within a surface to be processed of the semiconductor wafer. <P>SOLUTION: A semiconductor wafer processing device 100 for performing processing on semiconductor wafers 4 includes: a wafer cassette 1 for holding the semiconductor wafers 4; planar counter electrodes 5, surfaces of which are arranged so as to be parallel relating to surfaces 3 to be processed of the semiconductor wafers 4 arranged on the wafer cassette 1; a processing tank 8 having an internal space 18 in which processing liquid 7 can be introduced and the semiconductor wafers 4, the wafer cassettes 1, and counter electrodes 5 can be arranged; and processing liquid supply ports 6 and pumps 17 for controlling such that the flow velocity of the processing liquid 7 on sides of surfaces 3a to be processed of the semiconductor wafers is faster than the flow velocity of the processing liquid 7 on sides of rear surfaces 3b of the surfaces 3a to be processed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer processing apparatus, and more particularly to a semiconductor wafer processing apparatus that performs wet processing on a semiconductor wafer.

  In a conventional semiconductor wafer processing apparatus, reduction, etching, plating, cleaning, and the like are performed on a semiconductor wafer by wet processing by applying an electric field.

  For example, Japanese Patent Laid-Open No. 11-288908 (Patent Document 1) discloses a semiconductor wafer cleaning apparatus that cleans a semiconductor wafer by a wet process by applying an electric field. In this semiconductor wafer cleaning apparatus, a conductive chemical is interposed between the semiconductor wafer and the electrode member, and a predetermined voltage is applied between the semiconductor wafer and the electrode member. The semiconductor wafer and the chemical solution are relatively moved to clean the semiconductor wafer.

  In this semiconductor wafer cleaning apparatus, a large number of semiconductor wafers are accommodated in a wafer cassette. An electrical contact portion is formed in a part of the portion of the wafer cassette that supports the edge of the semiconductor wafer. This electrical contact portion is in contact with the semiconductor wafer. The electrical contact portion and the electrode member are connected via a voltage power source. A large number of semiconductor wafers are arranged in a direction in which the front and back surfaces of the semiconductor wafer are parallel to the flow direction of the chemical solution, and are supported in parallel.

Japanese Patent Laid-Open No. 11-288908

  In the semiconductor wafer cleaning apparatus described above, the counter electrode (electrode member) and each processing surface of the plurality of semiconductor wafers are arranged in the intersecting direction. Since the distance varies depending on the position in the processing surface, the distance between the counter electrode (electrode member) and the processing surface of the semiconductor wafer is not constant.

  Further, when a processing solution such as a chemical solution is flowed into the processing tank, the semiconductor wafer is swung by the flow of the processing solution, so that the adhesion between the semiconductor wafer and the contact for electrical conduction (electrical contact portion) is deteriorated. For this reason, there is a problem that the electric potential becomes strong and weak, and an electric field distribution is generated in the processing surface of the semiconductor wafer, so that uniform processing in the processing surface of the semiconductor wafer cannot be performed.

  Furthermore, the semiconductor wafer can be prevented from shaking during processing by firmly sandwiching and fixing the semiconductor wafer at the mounting position of the semiconductor wafer support member in the processing tank, but the semiconductor wafer is firmly sandwiched and fixed. If it is done, there is a high possibility that the semiconductor wafer will break. In other words, since the semiconductor wafer is firmly sandwiched between the mounting positions of the semiconductor wafer support member, a strong force is applied to the semiconductor wafer, so that the wafer is easily cracked when the semiconductor wafer is mounted or removed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor wafer processing apparatus capable of performing uniform processing within a processing surface of a semiconductor wafer.

  The semiconductor wafer processing apparatus of the present invention is a semiconductor wafer processing apparatus for processing a semiconductor wafer, and a wafer cassette for holding the semiconductor wafer and a processing surface of the semiconductor wafer arranged in the wafer cassette, A flat counter electrode whose surfaces are arranged in parallel, an internal space into which a processing liquid can be introduced, and a processing tank in which a semiconductor wafer, a wafer cassette and a counter electrode can be arranged in the internal space, A flow rate control member for controlling the flow rate of the treatment liquid on the treatment surface side to be faster than the flow rate of the treatment liquid on the back surface side of the treatment surface.

  According to the semiconductor wafer processing apparatus of the present invention, the processing surface of the semiconductor wafer disposed in the wafer cassette and the surface of the flat counter electrode are disposed in parallel, and the flow rate of the processing liquid on the processing surface side of the semiconductor wafer Is controlled to be faster than the flow rate of the treatment liquid on the back side. Thereby, since the electric field distribution in the processing surface of the semiconductor wafer can be suppressed, uniform processing can be performed in the processing surface of the semiconductor wafer.

It is a conceptual diagram of the semiconductor wafer processing apparatus in Embodiment 1 of this invention. It is a schematic perspective view of the wafer cassette of the semiconductor wafer processing apparatus in Embodiment 1 of the present invention. It is a schematic plan view of the wafer cassette of the semiconductor wafer processing apparatus in Embodiment 1 of the present invention. It is a conceptual diagram of the semiconductor wafer processing apparatus in Embodiment 2 of this invention. It is a conceptual diagram of the semiconductor wafer processing apparatus in Embodiment 3 of this invention. It is a conceptual diagram of the semiconductor wafer processing apparatus in Embodiment 4 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, the configuration of the semiconductor wafer processing apparatus according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, a semiconductor wafer processing apparatus 100 of the present embodiment mainly includes a wafer cassette 1, a counter electrode 5, a processing liquid supply member (processing liquid supply port 6, pump 17), and a processing tank 8. ing. In FIG. 1, the semiconductor wafer 4 and the processing liquid 7 are also shown for explanation.

  The wafer cassette 1 holds the semiconductor wafer 4. A plurality of semiconductor wafers 4 are held in the wafer cassette 1 so that the processing surface 3 a of the semiconductor wafer 4 faces the energizing contact 2 attached to the wafer cassette 1.

  A counter electrode 5 is provided so as to face the processing surface 3 a of the semiconductor wafer 4. A plurality of counter electrodes 5 are provided in order to collectively process the processing surfaces 3 a of the plurality of semiconductor wafers 4. The semiconductor wafer 4 and the counter electrode 5 are arranged to face each other so that the surface of the counter electrode 5 is parallel to the processing surface 3 a of the semiconductor wafer 4.

  The counter electrode 5 is formed in a shape and size that can cover the semiconductor wafer 4 when it is superimposed on the semiconductor wafer 4. That is, the surface of the counter electrode 5 is larger than the processing surface 3 a of the semiconductor wafer 4. The counter electrode 5 is made of, for example, platinum or gold.

  The treatment tank 8 has an internal space 18 into which the treatment liquid 7 can be introduced. In the internal space 18, the wafer cassette 1 holding the plurality of semiconductor wafers 4 and the counter electrode 5 can be arranged. The processing liquid supply member has a processing liquid supply port 6 and a pump 17. A hole for inserting the processing liquid supply port 6 is formed in the processing tank 8. The processing liquid supply ports 6 are disposed on the processing surface 3a side and the back surface 3b side (opposite side of the processing surface 3a) of the semiconductor wafer 4. The processing liquid supply port 6 is arranged in front of the arrangement position of the semiconductor wafer 4 (lower side in the figure) so as to supply the processing liquid 7. A pump 17 is disposed in the flow path leading to the processing liquid supply port 6. The pump 17 is for supplying the treatment liquid 7 to the treatment tank 8.

  A treatment liquid discharge port 9 is installed at the upper part of the treatment tank 8. Thus, the processing tank 8 is configured such that the processing liquid 7 is discharged from the processing liquid discharge port 9 when the processing liquid 7 is introduced to a certain height of the processing tank 8.

  A potentiostat 10 is electrically connected to each of the energizing contact 2 and the counter electrode 5. The counter electrode 5 is connected to the cathode of the potentiostat 10, and the energizing contact 2 is connected to the anode. A reference electrode 11 is disposed on the potentiostat 10. Thereby, with reference to the reference electrode 11, the semiconductor wafer 4 is processed while the potential between the cathode and the anode is controlled to an arbitrary potential.

  Referring to FIG. 2, wafer support groove 12 is formed in wafer cassette 1. The width of the wafer support groove 12 is configured to be larger than the thickness of the semiconductor wafer 4. It is desirable that three or more wafer support grooves 12 are formed for one semiconductor wafer 4 so that the semiconductor wafer 4 is arranged more parallel to the counter electrode 5.

  Further, a counter electrode insertion opening 13 for arranging the counter electrode 5 is formed in a portion adjacent to the wafer support groove 12 in the wafer cassette 1.

  Referring to FIG. 3, wafer support groove 12 has a shape that is wide at the base of the wall forming wafer support groove 12 and narrow at the tip. The shape of the wafer support groove 12 described above is an example and may be any shape that can support the semiconductor wafer 4. The energizing contact 2 is disposed on one wall forming the wafer support groove 12. The energizing contact 2 is made of, for example, platinum or gold. The plurality of energizing contacts 2 are connected in parallel by energizing contact connection lines 14. The shape of the contact point 2 for energization is merely an example, and any shape that can energize the semiconductor wafer 4 may be used.

Next, the operation of the semiconductor wafer processing apparatus of this embodiment will be described.
Referring to FIG. 1, a semiconductor wafer 4 is prepared. The semiconductor wafer 4 is supported by the wafer cassette 1 by being inserted into the wafer support groove 12 (see FIG. 3). The counter electrode 5 is disposed so that the processing surface 3a of the semiconductor wafer 4 and the counter electrode 5 face each other. In the drawing, a conductive processing liquid 7 is supplied into the processing tank 8 from the processing liquid supply port 6 in the direction of the arrow by a pump 17. As a result, the semiconductor wafer 4 and the counter electrode 5 are immersed in the processing liquid 7.

  The counter electrode 5 may be disposed in a state where the wafer cassette 1 is disposed in the processing tank 8, and the wafer cassette 1 is disposed in the processing tank 8 in a state where the counter electrode 5 is disposed in the wafer cassette 1. Also good. Further, the processing liquid 7 may be introduced in a state where the wafer cassette 1 is disposed in the processing tank 8, and the wafer cassette 1 is disposed in the processing tank 8 in a state where the processing liquid 7 is introduced into the processing tank 8. May be.

  The processing liquid 7 is discharged in the direction of the arrow X in the figure from the processing liquid discharge port 9 installed in the upper part of the processing tank 8. The processing liquid 7 discharged from the processing liquid discharge port 9 may be introduced again into the processing liquid supply port 6. Thereby, the processing liquid 7 is reused and used effectively.

  As the treatment liquid 7, for example, an ultrapure water electrolytic solution, a plating solution, a cleaning solution, an etching solution, or the like is used. By using various processing liquids 7 such as these according to the processing application of the semiconductor wafer 4, the semiconductor wafer 4 is processed according to the processing application.

  The flow rate of the processing liquid 7 supplied from the processing liquid supply port 6b (first processing liquid supply unit) disposed on the processing surface 3a side of the semiconductor wafer 4 is disposed on the back surface 3b side (opposite side of the processing surface 3a). The pump 17a and the pump 17b are controlled so as to be faster than the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6a (second processing liquid supply unit). In this way, the processing liquid supply ports 6a and 6b and the pumps 17a and 17b are controlled so that the flow rate of the processing liquid 7 on the processing surface 3a side of the semiconductor wafer 4 is faster than the flow rate of the processing liquid 7 on the back surface 3b side. The

  Since the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6b is faster than the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6a, the semiconductor wafer 4 is attracted to the processing liquid supply port 6b side where the flow rate is fast. . As a result, the semiconductor wafer 4 is attracted to the energizing contact 2 side.

  That is, since the processing surface 3a side of the semiconductor wafer 4 has a higher flow rate of the processing liquid 7 than the back surface 3b side, the processing surface 3a side of the semiconductor wafer 4 has a lower pressure of the processing liquid 7 than the back surface 3b side. Therefore, the force acts on the processing surface 3a side where the pressure is lower than the back surface 3b side where the semiconductor wafer 4 is high pressure. As a result, the processing surface 3 a of the semiconductor wafer 4 is brought into close contact with the contact 2 for energization.

  Therefore, as shown in FIG. 3, there is a gap between the wafer support groove 12 of the wafer cassette 1 and the semiconductor wafer 4, but the semiconductor wafer 4 is pressed against the wafer cassette 1 on the energizing contact 2 side. Is prevented from tilting or shaking inside the wafer cassette 1.

  Similarly, the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6d (first processing liquid supply unit) on the processing surface 3a side of the semiconductor wafer 4 is such that the flow rate of the processing liquid supply port 6c (second second) on the back surface side of the semiconductor wafer 4 is. The pump 17c and the pump 17d are controlled so as to be faster than the flow rate of the processing liquid 7 supplied from the processing liquid supply unit.

  In this state, an arbitrary potential is applied, and the semiconductor wafer 4 is subjected to processing such as reduction, etching, plating, and cleaning.

Next, the effect of the semiconductor wafer processing apparatus of this embodiment will be described.
According to the semiconductor wafer processing apparatus 100 of the present embodiment, the processing surface 3a of the semiconductor wafer 4 disposed in the wafer cassette 1 and the surface of the counter electrode 5 on the flat plate are disposed in parallel. Thereby, the distance between the processing surface 3a of the semiconductor wafer 4 and the counter electrode 5 is constant regardless of the position in the processing surface 3a. Thereby, the inside of the processing surface 3a can be processed uniformly.

  Further, the flow rate of the processing liquid 7 on the semiconductor wafer processing surface 3a side is controlled to be higher than the flow rate of the processing liquid 7 on the back surface 3b side (the opposite side of the processing surface 3a). In this way, the processing surface 3a of the semiconductor wafer 4 is brought into close contact with the energizing contact 2 by flowing the processing solution 7 so that the flow rate of the processing solution 7 is faster on the processing surface 3a side of the semiconductor wafer 4 than on the back surface 3b side. Can be reliably contacted.

  That is, since the processing surface 3a side of the semiconductor wafer 4 has a higher flow rate of the processing liquid 7 than the back surface 3b side, the processing surface 3a side of the semiconductor wafer 4 has a lower pressure of the processing liquid 7 than the back surface 3b side. Therefore, the force acts on the processing surface 3a side where the pressure is lower than the back surface 3b side where the semiconductor wafer 4 is high pressure. Thereby, the processing surface 3a of the semiconductor wafer 4 can be brought into close contact with the contact 2 for energization. Therefore, the semiconductor wafer 4 can be reliably brought into contact with the contact 2 for energization.

  In this manner, the semiconductor wafer 4 is pressed against the wafer cassette 1 via the energizing contact 2. Thereby, it can process reliably in the state which kept the process surface 3a of the semiconductor wafer 4 and the counter electrode 5 in parallel. Therefore, the electric field distribution in the processing surface 3a of the semiconductor wafer 4 can be suppressed, and uniform processing can be performed without variation in the processing surface 3a.

  In addition, since the plurality of counter electrodes 5 are arranged to face the plurality of semiconductor wafers 4 held in the wafer cassette 1, the plurality of semiconductor wafers 4 can be processed uniformly at a time.

  Further, according to the semiconductor wafer processing apparatus 100 of the present embodiment, the semiconductor wafer 4 is used for energizing the wafer cassette 1 due to the pressure difference based on the flow rate difference between the processing liquid 7 on the processing surface 3a side and the back surface 3b side of the semiconductor wafer 4. It is held in close contact via the contact 2. Therefore, since the semiconductor wafer 4 is firmly sandwiched between the members for supporting the semiconductor wafer 4 and is not fixed, the wafer may be cracked when the semiconductor wafer 4 is fixed to the member for supporting the semiconductor wafer 4. Absent. Therefore, it is possible to suppress the occurrence of wafer cracking when the semiconductor wafer 4 is attached to or removed from the semiconductor wafer processing apparatus 100.

(Embodiment 2)
The semiconductor wafer processing apparatus according to the second embodiment of the present invention is mainly different from the semiconductor wafer processing apparatus according to the first embodiment in the arrangement of the processing surface of the semiconductor wafer and the counter electrode.

  With reference to FIG. 4, two semiconductor wafers 4 are arranged so that one processing electrode 3 a of two semiconductor wafers 4 faces one counter electrode 5 from both sides of counter electrode 5.

  In the semiconductor wafer processing apparatus 100 of the present embodiment, the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6b (first processing liquid supply unit) disposed on the processing surface 3a side of the semiconductor wafer 4 is the back surface 3b. The pump 17a and the pump 17b are controlled so as to be faster than the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6a (second processing liquid supply unit) disposed on the side (the opposite side of the processing surface 3a). The Further, the flow rate of the processing liquid 7 supplied from the processing liquid supply port 6d (first processing liquid supply unit) disposed on the processing surface 3a side of the semiconductor wafer 4 is the processing liquid supply port 6c disposed on the back surface 3b side. The pump 17a and the pump 17b are controlled so as to be faster than the flow rate of the processing liquid 7 supplied from the (second processing liquid supply unit).

  In addition, since the structure and operation | movement other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  As described above, according to the semiconductor wafer processing apparatus 100 of the present embodiment, the same operational effects as those of the first embodiment are obtained. Further, since the two semiconductor wafers 4 are arranged so that the processing surfaces 3a of the two semiconductor wafers 4 face each other from both sides of the counter electrode 5 with respect to one counter electrode 5, 2 The processing surface 3a of two semiconductor wafers 4 can be processed. Therefore, the number of the counter electrodes 5 can be halved as compared with the case where the processing surface 3a of one semiconductor wafer 4 is processed with one counter electrode 5. Thereby, productivity including production cost can be improved.

(Embodiment 3)
The semiconductor wafer processing apparatus according to the third embodiment of the present invention is mainly different from the semiconductor wafer processing apparatus according to the first embodiment in the configuration of the processing liquid supply member.

  Referring to FIG. 5, the processing liquid supply member has a processing liquid supply port 6, a valve 15, and a processing liquid introduction port 16. A valve 15 is provided between the processing liquid supply port 6 and the processing liquid introduction port 16. The valve 15 is for supplying the treatment liquid 7 to the treatment tank 8. A conductive processing liquid 7 is supplied from the processing liquid supply port 6 into the processing tank 8 by a pump 17.

  In the semiconductor wafer processing apparatus 100 of the present embodiment, the processing liquid 7 is introduced from the processing liquid introduction port 16 to the processing liquid supply port 6 by the valve 15. Then, the processing liquid 7 is supplied into the processing tank 8 from the processing liquid supply port 6. The flow rate of the processing liquid 7 is changed by the valve 15. The conductance of the valve 15b provided in the processing liquid supply port 6b (first processing liquid supply unit) disposed on the processing surface 3a side of the semiconductor wafer 4 is disposed on the back surface 3b side (opposite side of the processing surface 3a). The conductance of the valve 15a provided at the treatment liquid supply port 6a (second treatment liquid supply unit) is controlled to be larger.

  For example, by setting the flow rate of the valve 15b to be greater than the flow rate of the valve 15a, the conductance of the valve 15b is controlled to be greater than the conductance of the valve a.

  Similarly, the conductance of the valve 15d provided at the processing liquid supply port 6d (first processing liquid supply unit) disposed on the processing surface 3a side of the semiconductor wafer 4 is on the back surface 3b side (the opposite side of the processing surface 3a). Control is performed so as to be larger than the conductance of the valve 15c provided in the disposed processing liquid supply port 6c (second processing liquid supply unit).

  In addition, since the structure and operation | movement other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  According to the semiconductor wafer processing apparatus 100 of the present embodiment, the conductance of the valve 15b provided in the processing liquid supply port 6b disposed on the processing surface 3a side of the semiconductor wafer 4 is the processing liquid supply disposed on the back surface side. The conductance is controlled to be larger than the conductance of the valve 15a provided at the port 6a. Thereby, the flow velocity on the processing surface 3a side of the semiconductor wafer 4 can be made faster than the flow velocity on the back surface 3b side. Therefore, it has the same effect as the first embodiment.

  In addition, by providing the valve 15, the flow rate of the processing liquid 7 can be easily adjusted by opening and closing the valve 15 when the processing liquid 7 is introduced from the processing liquid inlet 16.

  Further, when it is desired to change the flow rate of the processing liquid 7 depending on the processing content, the flow rate of the processing liquid 7 can be easily adjusted by opening and closing the valve 15, so that the operation can be easily performed.

(Embodiment 4)
The semiconductor wafer processing apparatus according to the fourth embodiment of the present invention is mainly different from the semiconductor wafer processing apparatus according to the first embodiment in the configuration of the processing liquid supply member.

  Referring to FIG. 6, the processing liquid supply member has a processing liquid supply port 6 and a processing liquid introduction port 16. A plurality of treatment liquid supply ports 6 are configured to branch from the treatment liquid introduction port 16. The treatment liquid supply ports 6a and 6b have different treatment liquid ejection diameters.

  In the semiconductor wafer processing apparatus 100 of the present embodiment, the conductance of the processing liquid inlet 16 is controlled to be sufficiently larger than the conductance of the processing liquid supply port 6. For example, when the diameter of the processing liquid inlet 16 is set sufficiently larger than the diameter of the processing liquid supply port 6, the conductance of the processing liquid inlet 16 is controlled to be sufficiently larger than the conductance of the processing liquid supply port 6. Is done.

  Further, the conductance of the treatment liquid supply port 6b (first treatment liquid supply unit) disposed on the treatment surface 3a side of the semiconductor wafer 4 is the treatment liquid supply port disposed on the back surface 3b side (the opposite side of the treatment surface 3a). It is controlled to be larger than the conductance of 6a (second processing liquid supply unit). For example, by setting the diameter of the processing liquid supply port 6b to be larger than the diameter of the processing liquid supply port 6a, the conductance of the processing liquid supply port 6b is controlled to be larger than the conductance of the processing liquid supply port 6b.

  Similarly, the conductance of the treatment liquid supply port 6d (first treatment liquid supply unit) disposed on the treatment surface 3a side of the semiconductor wafer 4 is the treatment liquid supply port 6c (second treatment liquid supply) disposed on the back surface 3b side. Part) is controlled to be larger than the conductance.

  In addition, since the structure and operation | movement other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  According to the semiconductor wafer processing apparatus 100 of the present embodiment, the conductance of the processing liquid inlet 16 is controlled to be sufficiently larger than the conductance of the processing liquid supply port 6. Further, the conductance of the processing liquid supply port 6b disposed on the processing surface 3a side of the semiconductor wafer 4 is controlled to be larger than the conductance of the processing liquid supply port 6a disposed on the back surface 3b side (the opposite side of the processing surface 3a). Has been. As a result, the flow rate of the treatment liquid 7 supplied from the treatment liquid supply port 6b can be made faster than the flow rate of the treatment liquid 7 supplied from the treatment liquid supply port 6a. Therefore, it has the same effect as the first embodiment.

  In addition, since the flow rate of the treatment liquid 7 is controlled by the treatment liquid introduction port 16 and the treatment liquid supply port 6, the flow rate of the treatment liquid 7 supplied from the treatment liquid supply ports 6a, 6b, 6c, and 6d is regulated. Kept at the value. Thereby, the process liquid 7 can always be introduced on the same conditions. Therefore, the semiconductor wafer 4 can be processed stably.

  Further, since the flow rate of the treatment liquid 7 can be controlled without providing a member for controlling the flow rate of the treatment liquid 7 in addition to the treatment liquid introduction port 16 and the treatment liquid supply port 6, the production process and production cost Can improve productivity.

  In the first to fourth embodiments, the configuration in which the semiconductor wafer 4 is brought into close contact with the wafer cassette 1 by controlling the flow rate at which the processing liquid 7 is supplied in the processing liquid supply member has been described. Is not limited to this configuration. The configuration in which the semiconductor wafer 4 is closely attached to the wafer cassette 1 may be a flow rate control member that changes the flow rate of the processing liquid 7 using a fan or the like. The flow rate control member includes a configuration for controlling the flow rate other than the treatment liquid supply member that controls the flow rate of the treatment liquid 7 by supplying the treatment liquid 7.

  In addition, about the structure of the semiconductor wafer 4 and the counter electrode 5, and the structure of a process liquid supply member, the structure with which each structure of Embodiment 1-4 was combined timely may be sufficient.

  Each embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor wafer processing apparatus that performs wet processing on a semiconductor wafer.

  DESCRIPTION OF SYMBOLS 1 Wafer cassette, 2 Contact for electricity supply, 3 Processing surface, 4 Semiconductor wafer, 5 Counter electrode, 6, 6a, 6b, 6c, 6d Processing liquid supply port, 7 Processing liquid, 8 Processing tank, 9 Processing liquid discharge port, 10 Potentiostat, 11 Reference electrode, 12 Wafer support groove, 13 Counter electrode insertion port, 14 Current connection connection line, 15 Valve, 16 Treatment liquid introduction port, 17, 17a, 17b, 17c, 17d Pump 18 Internal space, 100 Semiconductor Wafer processing equipment.

Claims (6)

A semiconductor wafer processing apparatus for processing a semiconductor wafer,
A wafer cassette for holding the semiconductor wafer;
A flat counter electrode whose surface is arranged parallel to the processing surface of the semiconductor wafer arranged in the wafer cassette;
A treatment tank having an internal space into which a treatment liquid can be introduced and capable of arranging the semiconductor wafer, the wafer cassette and the counter electrode in the internal space;
A semiconductor wafer processing apparatus, comprising: a flow rate control member for controlling the flow rate of the processing liquid on the processing surface side of the semiconductor wafer to be higher than the flow rate of the processing liquid on the back side of the processing surface.   The semiconductor wafer processing apparatus according to claim 1, wherein the flow rate control member is a processing liquid supply member for supplying a processing liquid to the processing tank.   The semiconductor wafer processing apparatus according to claim 2, wherein the processing liquid supply member includes a pump.   The semiconductor wafer processing apparatus according to claim 2, wherein the processing liquid supply member has a valve.   The processing liquid supply member includes a first processing liquid supply unit that supplies a processing liquid from the processing surface side of the semiconductor wafer, and a second processing liquid supply unit that supplies a processing liquid from the back surface side of the semiconductor wafer. The semiconductor wafer processing apparatus in any one of Claims 2-4 containing these.   6. The semiconductor wafer processing apparatus according to claim 5, wherein the first and second processing liquid supply sections have different processing liquid ejection diameters.

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